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[/] [pci/] [tags/] [rel_7/] [bench/] [verilog/] [pci_testbench_defines.v] - Blame information for rev 15

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//===================================================================================
//  Changeable testbench defines (constants) - tested together with 
//    pci_user_constants.v file, and not when regression testing!
//===================================================================================
 
// define whether or not testbench should stop executing after error is detected
`define STOP_ON_FAILURE
 
`ifdef REGRESSION
`else // Following DEFINES are used only without regression testing (together with pci_user_constants) !!!
    // wishbone frequncy in GHz
    `define WB_FREQ 0.025
 
    // values of image registers of PCI bridge device - valid are only upper 20 bits, others must be ZERO !
    `define TAR0_BASE_ADDR_0    32'h1000_0000
    `define TAR0_BASE_ADDR_1    32'h2000_0000
    `define TAR0_BASE_ADDR_2    32'h3000_0000
    `define TAR0_BASE_ADDR_3    32'h4000_0000
    `define TAR0_BASE_ADDR_4    32'h5000_0000
    `define TAR0_BASE_ADDR_5    32'h6000_0000
 
    `define TAR0_ADDR_MASK_0    32'hFFFF_F000 // when BA0 is used to access configuration space, this is NOT important!
    `define TAR0_ADDR_MASK_1    32'hFFFF_F000
    `define TAR0_ADDR_MASK_2    32'hFFFF_F000
    `define TAR0_ADDR_MASK_3    32'hFFFF_F000
    `define TAR0_ADDR_MASK_4    32'hFFFF_F000
    `define TAR0_ADDR_MASK_5    32'hFFFF_F000
 
    `define TAR0_TRAN_ADDR_0    32'h5000_0000 // when BA0 is used to access configuration space, this is NOT important!
    `define TAR0_TRAN_ADDR_1    32'h4000_0000
    `define TAR0_TRAN_ADDR_2    32'h3000_0000
    `define TAR0_TRAN_ADDR_3    32'h2000_0000
    `define TAR0_TRAN_ADDR_4    32'h1000_0000
    `define TAR0_TRAN_ADDR_5    32'h0000_0000
 
    // values of image registers of PCI behavioral target devices !
    `define BEH_TAR1_MEM_START 32'h7000_0000
    `define BEH_TAR1_MEM_END   32'h7000_0FFF
    `define BEH_TAR1_IO_START  32'h8000_0001
    `define BEH_TAR1_IO_END    32'h8000_0FFF
 
    `define BEH_TAR2_MEM_START 32'h9000_0000
    `define BEH_TAR2_MEM_END   32'h9000_0FFF
    `define BEH_TAR2_IO_START  32'hA000_0001
    `define BEH_TAR2_IO_END    32'hA000_0FFF
`endif
 
//===================================================================================
//  User-unchangeable testbench defines (constants)
//===================================================================================
 
// setup and hold time definitions for WISHBONE - used in BFMs for signal generation
`define Tsetup 2
`define Thold  2
 
// how many clock cycles should model wait for design's response - integer 32 bit value
`define WAIT_FOR_RESPONSE 6
 
// maximum number of transactions allowed in single call to block or cab transfer routines
`define MAX_BLK_SIZE  1024
 
// maximum retry terminations allows for WISHBONE master to repeat an access
`define WB_TB_MAX_RTY 1000
 
 
// some common types and defines
`define WB_ADDR_WIDTH 32
`define WB_DATA_WIDTH 32
`define WB_SEL_WIDTH `WB_DATA_WIDTH/8
`define WB_TAG_WIDTH 4
`define WB_ADDR_TYPE [(`WB_ADDR_WIDTH - 1):0]
`define WB_DATA_TYPE [(`WB_DATA_WIDTH - 1):0]
`define WB_SEL_TYPE  [(`WB_SEL_WIDTH  - 1):0]
`define WB_TAG_TYPE  [(`WB_TAG_WIDTH  - 1):0]
 
// definitions file only for testbench usage
// wishbone master behavioral defines
// flags type for wishbone cycle initialization
`define CYC_FLAG_TYPE [0:0]
// cab flag field in cycle initialization data
`define CYC_CAB_FLAG [0]
// read cycle stimulus - consists of:
//    - address field - which address read will be performed from
//    - sel field     - what byte select value should be
//    - tag field     - what tag values should be put on the bus
`define READ_STIM_TYPE [(`WB_ADDR_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH - 1):0]
`define READ_STIM_LENGTH (`WB_ADDR_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH)
`define READ_ADDRESS  [(`WB_ADDR_WIDTH - 1):0]
`define READ_SEL      [(`WB_ADDR_WIDTH + `WB_SEL_WIDTH - 1):`WB_ADDR_WIDTH]
`define READ_TAG_STIM [(`WB_ADDR_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH - 1):(`WB_ADDR_WIDTH + `WB_SEL_WIDTH)]
 
// read cycle return type consists of:
//    - read data field
//    - tag field received from WISHBONE
//    - wishbone slave response fields - ACK, ERR and RTY
//    - test bench error indicator (when testcase has not used wb master model properly)
//    - how much data was actually transfered
`define READ_RETURN_TYPE [(32 + 4 + `WB_DATA_WIDTH + `WB_TAG_WIDTH - 1):0]
`define READ_DATA        [(32 + `WB_DATA_WIDTH + 4 - 1):32 + 4]
`define READ_TAG_RET     [(32 + 4 + `WB_DATA_WIDTH + `WB_TAG_WIDTH - 1):(`WB_DATA_WIDTH + 32 + 4)]
`define READ_RETURN_LENGTH (32 + 4 + `WB_DATA_WIDTH + `WB_TAG_WIDTH - 1)
 
// write cycle stimulus type consists of
//    - address field
//    - data field
//    - sel field
//    - tag field
`define WRITE_STIM_TYPE [(`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH - 1):0]
`define WRITE_ADDRESS       [(`WB_ADDR_WIDTH - 1):0]
`define WRITE_DATA          [(`WB_ADDR_WIDTH + `WB_DATA_WIDTH - 1):`WB_ADDR_WIDTH]
`define WRITE_SEL           [(`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH - 1):(`WB_ADDR_WIDTH + `WB_DATA_WIDTH)]
`define WRITE_TAG_STIM      [(`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH - 1):(`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH)]
 
// length of WRITE_STIMULUS
`define WRITE_STIM_LENGTH (`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH)
 
// write cycle return type consists of:
//    - test bench error indicator (when testcase has not used wb master model properly)
//    - wishbone slave response fields - ACK, ERR and RTY
//    - tag field received from WISHBONE
//    - how much data was actually transfered
`define WRITE_RETURN_TYPE [(32 + 4 + `WB_TAG_WIDTH - 1):0]
`define WRITE_TAG_RET     [(32 + 4 + `WB_TAG_WIDTH - 1):32 + 4]
 
// this four fields are common to both read and write routines return values
`define TB_ERROR_BIT [0]
`define CYC_ACK [1]
`define CYC_RTY [2]
`define CYC_ERR [3]
`define CYC_RESPONSE [3:1]
`define CYC_ACTUAL_TRANSFER [35:4]
 
// block transfer flags
`define WB_TRANSFER_FLAGS [41:0]
// consists of:
// - number of transfer cycles to perform
// - flag that enables retry termination handling - if disabled, block transfer routines will return on any termination other than acknowledge
// - flag indicating CAB transfer is to be performed - ignored by all single transfer routines
// - number of initial wait states to insert
// - number of subsequent wait states to insert
`define WB_TRANSFER_SIZE     [41:10]
`define WB_TRANSFER_AUTO_RTY [8]
`define WB_TRANSFER_CAB      [9]
`define INIT_WAITS           [3:0]
`define SUBSEQ_WAITS         [7:4]
 

Line No.	Rev	Author	Line
1	15	mihad	`//===================================================================================`
2			`// Changeable testbench defines (constants) - tested together with`
3			`// pci_user_constants.v file, and not when regression testing!`
4			`//===================================================================================`
5
6			`// define whether or not testbench should stop executing after error is detected`
7			`define STOP_ON_FAILURE
8
9			`ifdef REGRESSION
10			`else // Following DEFINES are used only without regression testing (together with pci_user_constants) !!!
11			`// wishbone frequncy in GHz`
12			`define WB_FREQ 0.025
13
14			`// values of image registers of PCI bridge device - valid are only upper 20 bits, others must be ZERO !`
15			`define TAR0_BASE_ADDR_0 32'h1000_0000
16			`define TAR0_BASE_ADDR_1 32'h2000_0000
17			`define TAR0_BASE_ADDR_2 32'h3000_0000
18			`define TAR0_BASE_ADDR_3 32'h4000_0000
19			`define TAR0_BASE_ADDR_4 32'h5000_0000
20			`define TAR0_BASE_ADDR_5 32'h6000_0000
21
22			`define TAR0_ADDR_MASK_0 32'hFFFF_F000 // when BA0 is used to access configuration space, this is NOT important!
23			`define TAR0_ADDR_MASK_1 32'hFFFF_F000
24			`define TAR0_ADDR_MASK_2 32'hFFFF_F000
25			`define TAR0_ADDR_MASK_3 32'hFFFF_F000
26			`define TAR0_ADDR_MASK_4 32'hFFFF_F000
27			`define TAR0_ADDR_MASK_5 32'hFFFF_F000
28
29			`define TAR0_TRAN_ADDR_0 32'h5000_0000 // when BA0 is used to access configuration space, this is NOT important!
30			`define TAR0_TRAN_ADDR_1 32'h4000_0000
31			`define TAR0_TRAN_ADDR_2 32'h3000_0000
32			`define TAR0_TRAN_ADDR_3 32'h2000_0000
33			`define TAR0_TRAN_ADDR_4 32'h1000_0000
34			`define TAR0_TRAN_ADDR_5 32'h0000_0000
35
36			`// values of image registers of PCI behavioral target devices !`
37			`define BEH_TAR1_MEM_START 32'h7000_0000
38			`define BEH_TAR1_MEM_END 32'h7000_0FFF
39			`define BEH_TAR1_IO_START 32'h8000_0001
40			`define BEH_TAR1_IO_END 32'h8000_0FFF
41
42			`define BEH_TAR2_MEM_START 32'h9000_0000
43			`define BEH_TAR2_MEM_END 32'h9000_0FFF
44			`define BEH_TAR2_IO_START 32'hA000_0001
45			`define BEH_TAR2_IO_END 32'hA000_0FFF
46			`endif
47
48			`//===================================================================================`
49			`// User-unchangeable testbench defines (constants)`
50			`//===================================================================================`
51
52			`// setup and hold time definitions for WISHBONE - used in BFMs for signal generation`
53			`define Tsetup 2
54			`define Thold 2
55
56			`// how many clock cycles should model wait for design's response - integer 32 bit value`
57			`define WAIT_FOR_RESPONSE 6
58
59			`// maximum number of transactions allowed in single call to block or cab transfer routines`
60			`define MAX_BLK_SIZE 1024
61
62			`// maximum retry terminations allows for WISHBONE master to repeat an access`
63			`define WB_TB_MAX_RTY 1000
64
65
66			`// some common types and defines`
67			`define WB_ADDR_WIDTH 32
68			`define WB_DATA_WIDTH 32
69			`define WB_SEL_WIDTH `WB_DATA_WIDTH/8
70			`define WB_TAG_WIDTH 4
71			`define WB_ADDR_TYPE [(`WB_ADDR_WIDTH - 1):0]
72			`define WB_DATA_TYPE [(`WB_DATA_WIDTH - 1):0]
73			`define WB_SEL_TYPE [(`WB_SEL_WIDTH - 1):0]
74			`define WB_TAG_TYPE [(`WB_TAG_WIDTH - 1):0]
75
76			`// definitions file only for testbench usage`
77			`// wishbone master behavioral defines`
78			`// flags type for wishbone cycle initialization`
79			`define CYC_FLAG_TYPE [0:0]
80			`// cab flag field in cycle initialization data`
81			`define CYC_CAB_FLAG [0]
82			`// read cycle stimulus - consists of:`
83			`// - address field - which address read will be performed from`
84			`// - sel field - what byte select value should be`
85			`// - tag field - what tag values should be put on the bus`
86			`define READ_STIM_TYPE [(`WB_ADDR_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH - 1):0]
87			`define READ_STIM_LENGTH (`WB_ADDR_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH)
88			`define READ_ADDRESS [(`WB_ADDR_WIDTH - 1):0]
89			`define READ_SEL [(`WB_ADDR_WIDTH + `WB_SEL_WIDTH - 1):`WB_ADDR_WIDTH]
90			`define READ_TAG_STIM [(`WB_ADDR_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH - 1):(`WB_ADDR_WIDTH + `WB_SEL_WIDTH)]
91
92			`// read cycle return type consists of:`
93			`// - read data field`
94			`// - tag field received from WISHBONE`
95			`// - wishbone slave response fields - ACK, ERR and RTY`
96			`// - test bench error indicator (when testcase has not used wb master model properly)`
97			`// - how much data was actually transfered`
98			`define READ_RETURN_TYPE [(32 + 4 + `WB_DATA_WIDTH + `WB_TAG_WIDTH - 1):0]
99			`define READ_DATA [(32 + `WB_DATA_WIDTH + 4 - 1):32 + 4]
100			`define READ_TAG_RET [(32 + 4 + `WB_DATA_WIDTH + `WB_TAG_WIDTH - 1):(`WB_DATA_WIDTH + 32 + 4)]
101			`define READ_RETURN_LENGTH (32 + 4 + `WB_DATA_WIDTH + `WB_TAG_WIDTH - 1)
102
103			`// write cycle stimulus type consists of`
104			`// - address field`
105			`// - data field`
106			`// - sel field`
107			`// - tag field`
108			`define WRITE_STIM_TYPE [(`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH - 1):0]
109			`define WRITE_ADDRESS [(`WB_ADDR_WIDTH - 1):0]
110			`define WRITE_DATA [(`WB_ADDR_WIDTH + `WB_DATA_WIDTH - 1):`WB_ADDR_WIDTH]
111			`define WRITE_SEL [(`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH - 1):(`WB_ADDR_WIDTH + `WB_DATA_WIDTH)]
112			`define WRITE_TAG_STIM [(`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH - 1):(`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH)]
113
114			`// length of WRITE_STIMULUS`
115			`define WRITE_STIM_LENGTH (`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH)
116
117			`// write cycle return type consists of:`
118			`// - test bench error indicator (when testcase has not used wb master model properly)`
119			`// - wishbone slave response fields - ACK, ERR and RTY`
120			`// - tag field received from WISHBONE`
121			`// - how much data was actually transfered`
122			`define WRITE_RETURN_TYPE [(32 + 4 + `WB_TAG_WIDTH - 1):0]
123			`define WRITE_TAG_RET [(32 + 4 + `WB_TAG_WIDTH - 1):32 + 4]
124
125			`// this four fields are common to both read and write routines return values`
126			`define TB_ERROR_BIT [0]
127			`define CYC_ACK [1]
128			`define CYC_RTY [2]
129			`define CYC_ERR [3]
130			`define CYC_RESPONSE [3:1]
131			`define CYC_ACTUAL_TRANSFER [35:4]
132
133			`// block transfer flags`
134			`define WB_TRANSFER_FLAGS [41:0]
135			`// consists of:`
136			`// - number of transfer cycles to perform`
137			`// - flag that enables retry termination handling - if disabled, block transfer routines will return on any termination other than acknowledge`
138			`// - flag indicating CAB transfer is to be performed - ignored by all single transfer routines`
139			`// - number of initial wait states to insert`
140			`// - number of subsequent wait states to insert`
141			`define WB_TRANSFER_SIZE [41:10]
142			`define WB_TRANSFER_AUTO_RTY [8]
143			`define WB_TRANSFER_CAB [9]
144			`define INIT_WAITS [3:0]
145			`define SUBSEQ_WAITS [7:4]
146

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[/] [pci/] [tags/] [rel_7/] [bench/] [verilog/] [pci_testbench_defines.v] - Blame information for rev 15