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[/] [pci/] [tags/] [rel_7/] [bench/] [verilog/] [pci_testbench_defines.v] - Blame information for rev 45

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//===================================================================================
//  Changeable testbench defines (constants) - tested together with 
//    pci_user_constants.v file, and not when regression testing!
//===================================================================================
 
// define whether or not testbench should stop executing after error is detected
`define STOP_ON_FAILURE
 
`ifdef REGRESSION
`else // Following DEFINES are used only without regression testing (together with pci_user_constants) !!!
    // wishbone frequncy in GHz
    `define WB_FREQ 0.05
 
    // values of image registers of PCI bridge device - valid are only upper 20 bits, others must be ZERO !
    `define TAR0_BASE_ADDR_0    32'h1000_0000
    `define TAR0_BASE_ADDR_1    32'h2000_0000
    `define TAR0_BASE_ADDR_2    32'h4000_0000
    `define TAR0_BASE_ADDR_3    32'h6000_0000
    `define TAR0_BASE_ADDR_4    32'h8000_0000
    `define TAR0_BASE_ADDR_5    32'hA000_0000
 
    `define TAR0_ADDR_MASK_0    32'hFFFF_F000 // when BA0 is used to access configuration space, this is NOT important!
    `define TAR0_ADDR_MASK_1    32'hFFFF_F000
    `define TAR0_ADDR_MASK_2    32'hFFFF_F000
    `define TAR0_ADDR_MASK_3    32'hFFFF_F000
    `define TAR0_ADDR_MASK_4    32'hFFFF_F000
    `define TAR0_ADDR_MASK_5    32'hFFFF_F000
 
    `define TAR0_TRAN_ADDR_0    32'hC000_0000 // when BA0 is used to access configuration space, this is NOT important!
    `define TAR0_TRAN_ADDR_1    32'hA000_0000
    `define TAR0_TRAN_ADDR_2    32'h8000_0000
    `define TAR0_TRAN_ADDR_3    32'h6000_0000
    `define TAR0_TRAN_ADDR_4    32'h4000_0000
    `define TAR0_TRAN_ADDR_5    32'h2000_0000
 
    // values of image registers of PCI behavioral target devices !
    `define BEH_TAR1_MEM_START 32'hC000_0000
    `define BEH_TAR1_MEM_END   32'hC000_0FFF
    `define BEH_TAR1_IO_START  32'hD000_0001
    `define BEH_TAR1_IO_END    32'hD000_0FFF
 
    `define BEH_TAR2_MEM_START 32'hE000_0000
    `define BEH_TAR2_MEM_END   32'hE000_0FFF
    `define BEH_TAR2_IO_START  32'hF000_0001
    `define BEH_TAR2_IO_END    32'hF000_0FFF
 
    // IDSEL lines of each individual Target is connected to one address line
    // following defines set the address line IDSEL is connected to
    // TAR0 = DUT - bridge
    // TAR1 = behavioral target 1
    // TAR2 = behavioral target 2
 
    `define TAR0_IDSEL_INDEX    11
    `define TAR1_IDSEL_INDEX    12
    `define TAR2_IDSEL_INDEX    13
 
    // next 3 defines are derived from previous three defines
    `define TAR0_IDSEL_ADDR     (32'h0000_0001 << `TAR0_IDSEL_INDEX)
    `define TAR1_IDSEL_ADDR     (32'h0000_0001 << `TAR1_IDSEL_INDEX)
    `define TAR2_IDSEL_ADDR     (32'h0000_0001 << `TAR2_IDSEL_INDEX)
`endif
 
//===================================================================================
//  User-unchangeable testbench defines (constants)
//===================================================================================
 
// setup and hold time definitions for WISHBONE - used in BFMs for signal generation
`define Tsetup 0.5
`define Thold  0.5
 
// how many clock cycles should model wait for design's response - integer 32 bit value
`define WAIT_FOR_RESPONSE 6
 
// maximum number of transactions allowed in single call to block or cab transfer routines
`define MAX_BLK_SIZE  512
 
// maximum retry terminations allows for WISHBONE master to repeat an access
`define WB_TB_MAX_RTY 10000
 
 
// some common types and defines
`define WB_ADDR_WIDTH 32
`define WB_DATA_WIDTH 32
`define WB_SEL_WIDTH `WB_DATA_WIDTH/8
`define WB_TAG_WIDTH 4
`define WB_ADDR_TYPE [(`WB_ADDR_WIDTH - 1):0]
`define WB_DATA_TYPE [(`WB_DATA_WIDTH - 1):0]
`define WB_SEL_TYPE  [(`WB_SEL_WIDTH  - 1):0]
`define WB_TAG_TYPE  [(`WB_TAG_WIDTH  - 1):0]
 
// definitions file only for testbench usage
// wishbone master behavioral defines
// flags type for wishbone cycle initialization
`define CYC_FLAG_TYPE [0:0]
// cab flag field in cycle initialization data
`define CYC_CAB_FLAG [0]
// read cycle stimulus - consists of:
//    - address field - which address read will be performed from
//    - sel field     - what byte select value should be
//    - tag field     - what tag values should be put on the bus
`define READ_STIM_TYPE [(`WB_ADDR_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH - 1):0]
`define READ_STIM_LENGTH (`WB_ADDR_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH)
`define READ_ADDRESS  [(`WB_ADDR_WIDTH - 1):0]
`define READ_SEL      [(`WB_ADDR_WIDTH + `WB_SEL_WIDTH - 1):`WB_ADDR_WIDTH]
`define READ_TAG_STIM [(`WB_ADDR_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH - 1):(`WB_ADDR_WIDTH + `WB_SEL_WIDTH)]
 
// read cycle return type consists of:
//    - read data field
//    - tag field received from WISHBONE
//    - wishbone slave response fields - ACK, ERR and RTY
//    - test bench error indicator (when testcase has not used wb master model properly)
//    - how much data was actually transfered
`define READ_RETURN_TYPE [(32 + 4 + `WB_DATA_WIDTH + `WB_TAG_WIDTH - 1):0]
`define READ_DATA        [(32 + `WB_DATA_WIDTH + 4 - 1):32 + 4]
`define READ_TAG_RET     [(32 + 4 + `WB_DATA_WIDTH + `WB_TAG_WIDTH - 1):(`WB_DATA_WIDTH + 32 + 4)]
`define READ_RETURN_LENGTH (32 + 4 + `WB_DATA_WIDTH + `WB_TAG_WIDTH - 1)
 
// write cycle stimulus type consists of
//    - address field
//    - data field
//    - sel field
//    - tag field
`define WRITE_STIM_TYPE [(`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH - 1):0]
`define WRITE_ADDRESS       [(`WB_ADDR_WIDTH - 1):0]
`define WRITE_DATA          [(`WB_ADDR_WIDTH + `WB_DATA_WIDTH - 1):`WB_ADDR_WIDTH]
`define WRITE_SEL           [(`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH - 1):(`WB_ADDR_WIDTH + `WB_DATA_WIDTH)]
`define WRITE_TAG_STIM      [(`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH - 1):(`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH)]
 
// length of WRITE_STIMULUS
`define WRITE_STIM_LENGTH (`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH)
 
// write cycle return type consists of:
//    - test bench error indicator (when testcase has not used wb master model properly)
//    - wishbone slave response fields - ACK, ERR and RTY
//    - tag field received from WISHBONE
//    - how much data was actually transfered
`define WRITE_RETURN_TYPE [(32 + 4 + `WB_TAG_WIDTH - 1):0]
`define WRITE_TAG_RET     [(32 + 4 + `WB_TAG_WIDTH - 1):32 + 4]
 
// this four fields are common to both read and write routines return values
`define TB_ERROR_BIT [0]
`define CYC_ACK [1]
`define CYC_RTY [2]
`define CYC_ERR [3]
`define CYC_RESPONSE [3:1]
`define CYC_ACTUAL_TRANSFER [35:4]
 
// block transfer flags
`define WB_TRANSFER_FLAGS [41:0]
// consists of:
// - number of transfer cycles to perform
// - flag that enables retry termination handling - if disabled, block transfer routines will return on any termination other than acknowledge
// - flag indicating CAB transfer is to be performed - ignored by all single transfer routines
// - number of initial wait states to insert
// - number of subsequent wait states to insert
`define WB_TRANSFER_SIZE     [41:10]
`define WB_TRANSFER_AUTO_RTY [8]
`define WB_TRANSFER_CAB      [9]
`define INIT_WAITS           [3:0]
`define SUBSEQ_WAITS         [7:4]
 

Line No.	Rev	Author	Line
1	15	mihad	`//===================================================================================`
2			`// Changeable testbench defines (constants) - tested together with`
3			`// pci_user_constants.v file, and not when regression testing!`
4			`//===================================================================================`
5
6			`// define whether or not testbench should stop executing after error is detected`
7			`define STOP_ON_FAILURE
8
9			`ifdef REGRESSION
10			`else // Following DEFINES are used only without regression testing (together with pci_user_constants) !!!
11			`// wishbone frequncy in GHz`
12	26	mihad	`define WB_FREQ 0.05
13	15	mihad
14			`// values of image registers of PCI bridge device - valid are only upper 20 bits, others must be ZERO !`
15			`define TAR0_BASE_ADDR_0 32'h1000_0000
16			`define TAR0_BASE_ADDR_1 32'h2000_0000
17	26	mihad	`define TAR0_BASE_ADDR_2 32'h4000_0000
18			`define TAR0_BASE_ADDR_3 32'h6000_0000
19			`define TAR0_BASE_ADDR_4 32'h8000_0000
20			`define TAR0_BASE_ADDR_5 32'hA000_0000
21	15	mihad
22			`define TAR0_ADDR_MASK_0 32'hFFFF_F000 // when BA0 is used to access configuration space, this is NOT important!
23			`define TAR0_ADDR_MASK_1 32'hFFFF_F000
24			`define TAR0_ADDR_MASK_2 32'hFFFF_F000
25			`define TAR0_ADDR_MASK_3 32'hFFFF_F000
26			`define TAR0_ADDR_MASK_4 32'hFFFF_F000
27			`define TAR0_ADDR_MASK_5 32'hFFFF_F000
28
29	26	mihad	`define TAR0_TRAN_ADDR_0 32'hC000_0000 // when BA0 is used to access configuration space, this is NOT important!
30			`define TAR0_TRAN_ADDR_1 32'hA000_0000
31			`define TAR0_TRAN_ADDR_2 32'h8000_0000
32			`define TAR0_TRAN_ADDR_3 32'h6000_0000
33			`define TAR0_TRAN_ADDR_4 32'h4000_0000
34			`define TAR0_TRAN_ADDR_5 32'h2000_0000
35	15	mihad
36			`// values of image registers of PCI behavioral target devices !`
37	26	mihad	`define BEH_TAR1_MEM_START 32'hC000_0000
38			`define BEH_TAR1_MEM_END 32'hC000_0FFF
39			`define BEH_TAR1_IO_START 32'hD000_0001
40			`define BEH_TAR1_IO_END 32'hD000_0FFF
41	15	mihad
42	26	mihad	`define BEH_TAR2_MEM_START 32'hE000_0000
43			`define BEH_TAR2_MEM_END 32'hE000_0FFF
44			`define BEH_TAR2_IO_START 32'hF000_0001
45			`define BEH_TAR2_IO_END 32'hF000_0FFF
46	45	mihad
47			`// IDSEL lines of each individual Target is connected to one address line`
48			`// following defines set the address line IDSEL is connected to`
49			`// TAR0 = DUT - bridge`
50			`// TAR1 = behavioral target 1`
51			`// TAR2 = behavioral target 2`
52
53			`define TAR0_IDSEL_INDEX 11
54			`define TAR1_IDSEL_INDEX 12
55			`define TAR2_IDSEL_INDEX 13
56
57			`// next 3 defines are derived from previous three defines`
58			`define TAR0_IDSEL_ADDR (32'h0000_0001 << `TAR0_IDSEL_INDEX)
59			`define TAR1_IDSEL_ADDR (32'h0000_0001 << `TAR1_IDSEL_INDEX)
60			`define TAR2_IDSEL_ADDR (32'h0000_0001 << `TAR2_IDSEL_INDEX)
61	15	mihad	`endif
62
63			`//===================================================================================`
64			`// User-unchangeable testbench defines (constants)`
65			`//===================================================================================`
66
67			`// setup and hold time definitions for WISHBONE - used in BFMs for signal generation`
68	26	mihad	`define Tsetup 0.5
69			`define Thold 0.5
70	15	mihad
71			`// how many clock cycles should model wait for design's response - integer 32 bit value`
72			`define WAIT_FOR_RESPONSE 6
73
74			`// maximum number of transactions allowed in single call to block or cab transfer routines`
75	26	mihad	`define MAX_BLK_SIZE 512
76	15	mihad
77			`// maximum retry terminations allows for WISHBONE master to repeat an access`
78	26	mihad	`define WB_TB_MAX_RTY 10000
79	15	mihad
80
81			`// some common types and defines`
82			`define WB_ADDR_WIDTH 32
83			`define WB_DATA_WIDTH 32
84			`define WB_SEL_WIDTH `WB_DATA_WIDTH/8
85			`define WB_TAG_WIDTH 4
86			`define WB_ADDR_TYPE [(`WB_ADDR_WIDTH - 1):0]
87			`define WB_DATA_TYPE [(`WB_DATA_WIDTH - 1):0]
88			`define WB_SEL_TYPE [(`WB_SEL_WIDTH - 1):0]
89			`define WB_TAG_TYPE [(`WB_TAG_WIDTH - 1):0]
90
91			`// definitions file only for testbench usage`
92			`// wishbone master behavioral defines`
93			`// flags type for wishbone cycle initialization`
94			`define CYC_FLAG_TYPE [0:0]
95			`// cab flag field in cycle initialization data`
96			`define CYC_CAB_FLAG [0]
97			`// read cycle stimulus - consists of:`
98			`// - address field - which address read will be performed from`
99			`// - sel field - what byte select value should be`
100			`// - tag field - what tag values should be put on the bus`
101			`define READ_STIM_TYPE [(`WB_ADDR_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH - 1):0]
102			`define READ_STIM_LENGTH (`WB_ADDR_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH)
103			`define READ_ADDRESS [(`WB_ADDR_WIDTH - 1):0]
104			`define READ_SEL [(`WB_ADDR_WIDTH + `WB_SEL_WIDTH - 1):`WB_ADDR_WIDTH]
105			`define READ_TAG_STIM [(`WB_ADDR_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH - 1):(`WB_ADDR_WIDTH + `WB_SEL_WIDTH)]
106
107			`// read cycle return type consists of:`
108			`// - read data field`
109			`// - tag field received from WISHBONE`
110			`// - wishbone slave response fields - ACK, ERR and RTY`
111			`// - test bench error indicator (when testcase has not used wb master model properly)`
112			`// - how much data was actually transfered`
113			`define READ_RETURN_TYPE [(32 + 4 + `WB_DATA_WIDTH + `WB_TAG_WIDTH - 1):0]
114			`define READ_DATA [(32 + `WB_DATA_WIDTH + 4 - 1):32 + 4]
115			`define READ_TAG_RET [(32 + 4 + `WB_DATA_WIDTH + `WB_TAG_WIDTH - 1):(`WB_DATA_WIDTH + 32 + 4)]
116			`define READ_RETURN_LENGTH (32 + 4 + `WB_DATA_WIDTH + `WB_TAG_WIDTH - 1)
117
118			`// write cycle stimulus type consists of`
119			`// - address field`
120			`// - data field`
121			`// - sel field`
122			`// - tag field`
123			`define WRITE_STIM_TYPE [(`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH - 1):0]
124			`define WRITE_ADDRESS [(`WB_ADDR_WIDTH - 1):0]
125			`define WRITE_DATA [(`WB_ADDR_WIDTH + `WB_DATA_WIDTH - 1):`WB_ADDR_WIDTH]
126			`define WRITE_SEL [(`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH - 1):(`WB_ADDR_WIDTH + `WB_DATA_WIDTH)]
127			`define WRITE_TAG_STIM [(`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH - 1):(`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH)]
128
129			`// length of WRITE_STIMULUS`
130			`define WRITE_STIM_LENGTH (`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH)
131
132			`// write cycle return type consists of:`
133			`// - test bench error indicator (when testcase has not used wb master model properly)`
134			`// - wishbone slave response fields - ACK, ERR and RTY`
135			`// - tag field received from WISHBONE`
136			`// - how much data was actually transfered`
137			`define WRITE_RETURN_TYPE [(32 + 4 + `WB_TAG_WIDTH - 1):0]
138			`define WRITE_TAG_RET [(32 + 4 + `WB_TAG_WIDTH - 1):32 + 4]
139
140			`// this four fields are common to both read and write routines return values`
141			`define TB_ERROR_BIT [0]
142			`define CYC_ACK [1]
143			`define CYC_RTY [2]
144			`define CYC_ERR [3]
145			`define CYC_RESPONSE [3:1]
146			`define CYC_ACTUAL_TRANSFER [35:4]
147
148			`// block transfer flags`
149			`define WB_TRANSFER_FLAGS [41:0]
150			`// consists of:`
151			`// - number of transfer cycles to perform`
152			`// - flag that enables retry termination handling - if disabled, block transfer routines will return on any termination other than acknowledge`
153			`// - flag indicating CAB transfer is to be performed - ignored by all single transfer routines`
154			`// - number of initial wait states to insert`
155			`// - number of subsequent wait states to insert`
156			`define WB_TRANSFER_SIZE [41:10]
157			`define WB_TRANSFER_AUTO_RTY [8]
158			`define WB_TRANSFER_CAB [9]
159			`define INIT_WAITS [3:0]
160			`define SUBSEQ_WAITS [7:4]
161

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[/] [pci/] [tags/] [rel_7/] [bench/] [verilog/] [pci_testbench_defines.v] - Blame information for rev 45