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[/] [pci/] [tags/] [rel_7/] [bench/] [verilog/] [pci_unsupported_commands_master.v] - Blame information for rev 154

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`include "bus_commands.v"
module pci_unsupported_commands_master
(
    CLK,
    AD,
    CBE,
    RST,
    REQ,
    GNT,
    FRAME,
    IRDY,
    DEVSEL,
    TRDY,
    STOP,
    PAR
);
 
parameter normal       = 0 ;
parameter disconnect   = 1 ;
parameter retry        = 2 ;
parameter target_abort = 3 ;
parameter master_abort = 4 ;
parameter error        = 5 ;
 
input CLK ;
inout [31:0] AD ;
inout [3:0]  CBE ;
input  RST ;
output REQ ;
input  GNT ;
inout FRAME ;
inout IRDY ;
input  DEVSEL ;
input  TRDY ;
input  STOP ;
inout  PAR ;
 
reg [31:0] AD_int ;
reg        AD_en ;
 
reg [3:0] CBE_int ;
reg       CBE_en ;
 
reg FRAME_int ;
reg FRAME_en ;
 
reg IRDY_int ;
reg IRDY_en ;
 
reg PAR_int ;
reg PAR_en ;
 
assign AD    = AD_en    ? AD_int    : 32'hzzzz_zzzz ;
assign CBE   = CBE_en   ? CBE_int   : 4'hz ;
assign FRAME = FRAME_en ? FRAME_int : 1'bz ;
assign IRDY  = IRDY_en  ? IRDY_int  : 1'bz ;
assign PAR   = PAR_en   ? PAR_int   : 1'bz ;
 
reg         REQ ;
 
event e_finish_transaction ;
event e_transfers_done ;
 
reg write ;
reg make_parity_error_after_last_dataphase ;
 
initial
begin
    REQ      = 1'b1 ;
    AD_en    = 1'b0 ;
    CBE_en   = 1'b0 ;
    FRAME_en = 1'b0 ;
    IRDY_en  = 1'b0 ;
    PAR_en   = 1'b0 ;
    write = 1'b0 ;
    make_parity_error_after_last_dataphase = 1'b0 ;
end
 
task unsupported_reference ;
    input [31:0] addr1 ;
    input [31:0] addr2 ;
    input [3:0]  bc1 ;
    input [3:0]  bc2 ;
    input [3:0]  be ;
    input [31:0] data ;
    input        make_addr_perr1 ;
    input        make_addr_perr2 ;
    output       ok ;
    integer      i ;
    reg          dual_address ;
    reg  [2:0]   received_termination ;
begin:main
    ok = 1 ;
    dual_address = (bc1 == `BC_DUAL_ADDR_CYC) ;
 
    get_bus_ownership(ok) ;
    if (ok !== 1'b1)
        disable main ;
 
    addr_phase1(addr1, bc1) ;
 
    if ( dual_address )
    begin
        write = bc2[0] ;
        addr_phase2(addr2, bc2, make_addr_perr1) ;
        first_and_last_data_phase(bc2[0], data, be, make_addr_perr2, 1'b0, received_termination) ;
        finish_transaction(bc2[0], 1'b0) ;
    end
    else
    begin
        write = bc1[0] ;
        first_and_last_data_phase(bc1[0], data, be, make_addr_perr1, 1'b0, received_termination) ;
        finish_transaction(bc1[0], 1'b0) ;
    end
 
    if (received_termination !== master_abort)
    begin
        ok = 0 ;
    end
end
endtask // master_reference
 
// task added for target overflow testing
// master writes the addresses to the coresponding locations
task normal_write_transfer ;
    input  [31:0] start_address ;
    input  [3:0]  bus_command ;
    input  [31:0] size ;
    input  [2:0]  wait_cycles ;
    output [31:0] actual_transfer ;
    output [2:0]  received_termination ;
    reg ok ;
    reg [31:0] current_address ;
begin:main
 
    write = 1'b1 ;
    get_bus_ownership (ok) ;
    if (ok !== 1'b1)
    begin
        received_termination = error ;
        disable main ;
    end
 
    make_parity_error_after_last_dataphase = 1'b0 ;
 
    addr_phase1(start_address, bus_command) ;
    actual_transfer = 0 ;
    if (size == 1)
    begin
        first_and_last_data_phase (1'b1, ~start_address, 4'hF, 1'b0, 1'b0, received_termination) ;
        if ((received_termination == normal) || (received_termination == disconnect))
            actual_transfer = 1 ;
 
        -> e_finish_transaction ;
    end
    else
    begin
        current_address = start_address ;
        first_data_phase (1'b1, ~start_address, 4'hF, 1'b0, 1'b0, received_termination) ;
        if ((received_termination == normal) || (received_termination == disconnect))
            actual_transfer = 1 ;
 
        if (received_termination == master_abort)
        begin
            -> e_transfers_done ;
        end
 
        while ((actual_transfer < (size - 1)) && (received_termination == normal))
        begin
            current_address = current_address + 4 ;
            insert_waits(1'b1, wait_cycles, received_termination) ;
            if (received_termination === normal)
            begin
                subsequent_data_phase(1'b1, ~current_address, 4'hF, 1'b0, received_termination) ;
                if ((received_termination == normal) || (received_termination == disconnect))
                    actual_transfer = actual_transfer + 1 ;
            end
        end
 
        if (received_termination == normal)
        begin
            current_address = current_address + 4 ;
            insert_waits(1'b1, wait_cycles, received_termination) ;
            if (received_termination === normal)
            begin
                last_data_phase(1'b1, ~current_address, 4'hF, 1'b0, received_termination) ;
                if ((received_termination == normal) || (received_termination == disconnect))
                    actual_transfer = actual_transfer + 1 ;
 
                -> e_finish_transaction ;
            end
            else
                -> e_transfers_done ;
        end
        else
            -> e_transfers_done ;
    end
end
endtask // normal_write_transfer
 
task get_bus_ownership ;
    output  ok ;
    integer deadlock ;
begin
    deadlock = 0 ;
    @(posedge CLK) ;
    while( ((GNT !== 0) || (FRAME !== 1'b1) || (IRDY !== 1'b1)) && (deadlock < 5000) )
    begin
        REQ <= #6 1'b0 ;
        @(posedge CLK) ;
        deadlock = deadlock + 1 ;
    end
 
    if (GNT !== 0)
    begin
        $display("*E, PCI Master could not get ownership of the bus in 5000 cycles") ;
        ok = 0 ;
    end
    else
    begin
        ok = 1 ;
    end
 
    REQ <= #6 1'b1 ;
end
endtask // get_bus_ownership
 
task addr_phase1 ;
    input [31:0] address ;
    input [3:0]  bus_command ;
begin
    FRAME_en  <= #6 1'b1 ;
    FRAME_int <= #6 1'b0 ;
 
    AD_en     <= #6 1'b1 ;
    AD_int    <= #6 address ;
 
    CBE_en    <= #6 1'b1 ;
    CBE_int   <= #6 bus_command ;
    @(posedge CLK) ;
end
endtask // addr_phase1
 
task addr_phase2 ;
    input [31:0] address ;
    input [3:0]  bus_command ;
    input        make_parity_error;
begin
    PAR_int <= #6 ^{AD, CBE, make_parity_error} ;
    PAR_en  <= #6 1'b1 ;
    AD_int  <= #6 address ;
    CBE_int <= #6 bus_command ;
    @(posedge CLK) ;
end
endtask
 
task first_and_last_data_phase ;
    input         rw ;
    input  [31:0] data ;
    input  [3:0]  be ;
    input         make_addr_parity_error ;
    input         make_data_parity_error ;
    output [2:0]  received_termination ;
    integer i ;
begin
    FRAME_int <= #6 1'b1 ;
    first_data_phase (rw, data, be, make_addr_parity_error, make_data_parity_error, received_termination) ;
end
endtask // first_and_last_data_phase
 
task first_data_phase ;
    input         rw ;
    input  [31:0] data ;
    input  [3:0]  be ;
    input         make_addr_parity_error ;
    input         make_data_parity_error ;
    output [2:0]  received_termination ;
    integer       i ;
begin
    PAR_int  <= #6 ^{AD, CBE, make_addr_parity_error} ;
    PAR_en   <= #6 1'b1 ;
    IRDY_en  <= #6 1'b1 ;
    IRDY_int <= #6 1'b0 ;
    CBE_int  <= #6 ~be ;
    if (rw)
        AD_int <= #6 data ;
    else
        AD_en <= #6 1'b0 ;
 
    @(posedge CLK) ;
    if (!rw)
        PAR_en <= #6 1'b0 ;
    else
        PAR_int <= #6 ^{AD, CBE, make_data_parity_error} ;
 
    i = 1 ;
    while ( (i < 5) && (DEVSEL === 1'b1) )
    begin
        @(posedge CLK) ;
        i = i + 1 ;
    end
 
    if (DEVSEL === 1'b1)
    begin
        received_termination = master_abort ;
    end
    else
    begin
        get_termination(received_termination);
    end
end
endtask // first_data_phase
 
task subsequent_data_phase ;
    input         rw ;
    input  [31:0] data ;
    input  [3:0]  be ;
    input         make_parity_error ;
    output [2:0]  received_termination ;
begin
    if (rw)
    begin
        PAR_int <= #6 ^{AD, CBE, make_parity_error} ;
        AD_int  <= #6 data ;
    end
 
    IRDY_int <= #6 1'b0 ;
    CBE_int <= #6 ~be ;
    @(posedge CLK);
    get_termination(received_termination);
end
endtask // subsequent_data_phase
 
task last_data_phase ;
    input         rw ;
    input  [31:0] data ;
    input  [3:0]  be ;
    input         make_parity_error ;
    output [2:0]  received_termination ;
begin
    FRAME_int <= #6 1'b1 ;
    IRDY_int  <= #6 1'b0 ;
    if (rw)
    begin
        PAR_int <= #6 ^{AD, CBE, make_parity_error} ;
        AD_int <= #6 data ;
    end
 
    CBE_int <= #6 ~be ;
 
    @(posedge CLK);
    get_termination(received_termination);
end
endtask // subsequent_data_phase
 
task get_termination ;
    output [2:0] received_termination ;
begin
    while ((TRDY === 1'b1) && (STOP === 1'b1))
        @(posedge CLK) ;
 
    if ( DEVSEL !== 1'b0 )
        received_termination = target_abort ;
    else if (TRDY !== 1'b1)
    begin
        if (STOP !== 1'b1)
            received_termination = disconnect ;
        else
            received_termination = normal ;
    end
    else
        received_termination = retry ;
end
endtask // get_termination
 
task finish_transaction ;
    input rw ;
    input make_parity_error ;
begin
    if (rw)
        PAR_int <= #6 ^{AD, CBE, make_parity_error} ;
 
    IRDY_int <= #6 1'b1 ;
    FRAME_en <= #6 1'b0 ;
    AD_en    <= #6 1'b0 ;
    CBE_en   <= #6 1'b0 ;
 
    @(posedge CLK) ;
    PAR_en  <= #6 1'b0 ;
    IRDY_en <= #6 1'b0 ;
end
endtask // finish_transaction
 
always@(e_finish_transaction)
begin
    finish_transaction (write, make_parity_error_after_last_dataphase) ;
end
 
always@(e_transfers_done)
begin
 
    if (FRAME !== 1'b1)
    begin
        FRAME_int <= #6 1'b1 ;
        IRDY_int  <= #6 1'b0 ;
        if (write)
            PAR_int <= #6 ^{CBE, AD} ;
 
        @(posedge CLK) ;
    end
 
    -> e_finish_transaction ;
end
 
task insert_waits ;
    input rw ;
    input  [2:0] wait_cycles ;
    output [2:0] termination ;
    reg   [2:0] wait_cycles_left ;
    reg         stop_without_trdy_received ;
begin
    stop_without_trdy_received = 1'b0 ;
    wait_cycles_left = wait_cycles ;
 
    termination = normal ;
 
    PAR_int <= #6 ^{AD, CBE} ;
 
    for (wait_cycles_left = wait_cycles ; (wait_cycles_left > 0) && !stop_without_trdy_received ; wait_cycles_left = wait_cycles_left - 1'b1)
    begin
        IRDY_int <= #6 1'b1 ;
        @(posedge CLK) ;
 
        PAR_int <= #6 ^{AD, CBE, 1'b1} ;
 
        if ((STOP !== 1'b1) && (TRDY !== 1'b0))
        begin
            stop_without_trdy_received = 1'b1 ;
            if (DEVSEL !== 1'b0)
                termination = target_abort ;
            else
                termination = retry ;
        end
    end
end
endtask // insert_waits
endmodule
 

Line No.	Rev	Author	Line
1	15	mihad	`include "bus_commands.v"
2			`module pci_unsupported_commands_master`
3			`(`
4			`CLK,`
5			`AD,`
6			`CBE,`
7			`RST,`
8			`REQ,`
9			`GNT,`
10			`FRAME,`
11			`IRDY,`
12			`DEVSEL,`
13			`TRDY,`
14			`STOP,`
15			`PAR`
16			`);`
17
18	73	mihad	`parameter normal = 0 ;`
19			`parameter disconnect = 1 ;`
20			`parameter retry = 2 ;`
21			`parameter target_abort = 3 ;`
22			`parameter master_abort = 4 ;`
23			`parameter error = 5 ;`
24
25	15	mihad	`input CLK ;`
26	73	mihad	`inout [31:0] AD ;`
27			`inout [3:0] CBE ;`
28	15	mihad	`input RST ;`
29			`output REQ ;`
30			`input GNT ;`
31	73	mihad	`inout FRAME ;`
32			`inout IRDY ;`
33	15	mihad	`input DEVSEL ;`
34			`input TRDY ;`
35			`input STOP ;`
36	73	mihad	`inout PAR ;`
37	15	mihad
38	73	mihad	`reg [31:0] AD_int ;`
39			`reg AD_en ;`
40
41			`reg [3:0] CBE_int ;`
42			`reg CBE_en ;`
43
44			`reg FRAME_int ;`
45			`reg FRAME_en ;`
46
47			`reg IRDY_int ;`
48			`reg IRDY_en ;`
49
50			`reg PAR_int ;`
51			`reg PAR_en ;`
52
53			`assign AD = AD_en ? AD_int : 32'hzzzz_zzzz ;`
54			`assign CBE = CBE_en ? CBE_int : 4'hz ;`
55			`assign FRAME = FRAME_en ? FRAME_int : 1'bz ;`
56			`assign IRDY = IRDY_en ? IRDY_int : 1'bz ;`
57			`assign PAR = PAR_en ? PAR_int : 1'bz ;`
58
59	15	mihad	`reg REQ ;`
60
61	73	mihad	`event e_finish_transaction ;`
62			`event e_transfers_done ;`
63
64			`reg write ;`
65			`reg make_parity_error_after_last_dataphase ;`
66
67	15	mihad	`initial`
68			`begin`
69	73	mihad	`REQ = 1'b1 ;`
70			`AD_en = 1'b0 ;`
71			`CBE_en = 1'b0 ;`
72			`FRAME_en = 1'b0 ;`
73			`IRDY_en = 1'b0 ;`
74			`PAR_en = 1'b0 ;`
75			`write = 1'b0 ;`
76			`make_parity_error_after_last_dataphase = 1'b0 ;`
77	15	mihad	`end`
78
79	73	mihad	`task unsupported_reference ;`
80	15	mihad	`input [31:0] addr1 ;`
81			`input [31:0] addr2 ;`
82			`input [3:0] bc1 ;`
83			`input [3:0] bc2 ;`
84			`input [3:0] be ;`
85			`input [31:0] data ;`
86			`input make_addr_perr1 ;`
87			`input make_addr_perr2 ;`
88			`output ok ;`
89			`integer i ;`
90			`reg dual_address ;`
91	73	mihad	`reg [2:0] received_termination ;`
92			`begin:main`
93	15	mihad	`ok = 1 ;`
94			dual_address = (bc1 == `BC_DUAL_ADDR_CYC) ;
95	73	mihad
96			`get_bus_ownership(ok) ;`
97			`if (ok !== 1'b1)`
98			`disable main ;`
99
100			`addr_phase1(addr1, bc1) ;`
101
102			`if ( dual_address )`
103	15	mihad	`begin`
104	73	mihad	`write = bc2[0] ;`
105			`addr_phase2(addr2, bc2, make_addr_perr1) ;`
106			`first_and_last_data_phase(bc2[0], data, be, make_addr_perr2, 1'b0, received_termination) ;`
107			`finish_transaction(bc2[0], 1'b0) ;`
108	15	mihad	`end`
109	73	mihad	`else`
110			`begin`
111			`write = bc1[0] ;`
112			`first_and_last_data_phase(bc1[0], data, be, make_addr_perr1, 1'b0, received_termination) ;`
113			`finish_transaction(bc1[0], 1'b0) ;`
114			`end`
115	15	mihad
116	73	mihad	`if (received_termination !== master_abort)`
117			`begin`
118			`ok = 0 ;`
119			`end`
120			`end`
121			`endtask // master_reference`
122	15	mihad
123	73	mihad	`// task added for target overflow testing`
124			`// master writes the addresses to the coresponding locations`
125			`task normal_write_transfer ;`
126			`input [31:0] start_address ;`
127			`input [3:0] bus_command ;`
128			`input [31:0] size ;`
129			`input [2:0] wait_cycles ;`
130			`output [31:0] actual_transfer ;`
131			`output [2:0] received_termination ;`
132			`reg ok ;`
133			`reg [31:0] current_address ;`
134			`begin:main`
135
136			`write = 1'b1 ;`
137			`get_bus_ownership (ok) ;`
138			`if (ok !== 1'b1)`
139	15	mihad	`begin`
140	73	mihad	`received_termination = error ;`
141			`disable main ;`
142	15	mihad	`end`
143	73	mihad
144			`make_parity_error_after_last_dataphase = 1'b0 ;`
145
146			`addr_phase1(start_address, bus_command) ;`
147			`actual_transfer = 0 ;`
148			`if (size == 1)`
149			`begin`
150			`first_and_last_data_phase (1'b1, ~start_address, 4'hF, 1'b0, 1'b0, received_termination) ;`
151			`if ((received_termination == normal) \|\| (received_termination == disconnect))`
152			`actual_transfer = 1 ;`
153
154			`-> e_finish_transaction ;`
155			`end`
156	15	mihad	`else`
157			`begin`
158	73	mihad	`current_address = start_address ;`
159			`first_data_phase (1'b1, ~start_address, 4'hF, 1'b0, 1'b0, received_termination) ;`
160			`if ((received_termination == normal) \|\| (received_termination == disconnect))`
161			`actual_transfer = 1 ;`
162
163			`if (received_termination == master_abort)`
164			`begin`
165			`-> e_transfers_done ;`
166			`end`
167
168			`while ((actual_transfer < (size - 1)) && (received_termination == normal))`
169			`begin`
170			`current_address = current_address + 4 ;`
171			`insert_waits(1'b1, wait_cycles, received_termination) ;`
172			`if (received_termination === normal)`
173			`begin`
174			`subsequent_data_phase(1'b1, ~current_address, 4'hF, 1'b0, received_termination) ;`
175			`if ((received_termination == normal) \|\| (received_termination == disconnect))`
176			`actual_transfer = actual_transfer + 1 ;`
177			`end`
178			`end`
179
180			`if (received_termination == normal)`
181			`begin`
182	89	mihad	`current_address = current_address + 4 ;`
183	73	mihad	`insert_waits(1'b1, wait_cycles, received_termination) ;`
184			`if (received_termination === normal)`
185			`begin`
186			`last_data_phase(1'b1, ~current_address, 4'hF, 1'b0, received_termination) ;`
187			`if ((received_termination == normal) \|\| (received_termination == disconnect))`
188			`actual_transfer = actual_transfer + 1 ;`
189
190			`-> e_finish_transaction ;`
191			`end`
192			`else`
193			`-> e_transfers_done ;`
194			`end`
195	15	mihad	`else`
196	73	mihad	`-> e_transfers_done ;`
197	15	mihad	`end`
198	73	mihad	`end`
199			`endtask // normal_write_transfer`
200	15	mihad
201	73	mihad	`task get_bus_ownership ;`
202			`output ok ;`
203			`integer deadlock ;`
204			`begin`
205			`deadlock = 0 ;`
206	15	mihad	`@(posedge CLK) ;`
207	73	mihad	`while( ((GNT !== 0) \|\| (FRAME !== 1'b1) \|\| (IRDY !== 1'b1)) && (deadlock < 5000) )`
208	15	mihad	`begin`
209	73	mihad	`REQ <= #6 1'b0 ;`
210			`@(posedge CLK) ;`
211			`deadlock = deadlock + 1 ;`
212	15	mihad	`end`
213	73	mihad
214			`if (GNT !== 0)`
215			`begin`
216			`$display("*E, PCI Master could not get ownership of the bus in 5000 cycles") ;`
217			`ok = 0 ;`
218			`end`
219	15	mihad	`else`
220			`begin`
221	73	mihad	`ok = 1 ;`
222	15	mihad	`end`
223
224	73	mihad	`REQ <= #6 1'b1 ;`
225			`end`
226			`endtask // get_bus_ownership`
227
228			`task addr_phase1 ;`
229			`input [31:0] address ;`
230			`input [3:0] bus_command ;`
231			`begin`
232			`FRAME_en <= #6 1'b1 ;`
233			`FRAME_int <= #6 1'b0 ;`
234
235			`AD_en <= #6 1'b1 ;`
236			`AD_int <= #6 address ;`
237
238			`CBE_en <= #6 1'b1 ;`
239			`CBE_int <= #6 bus_command ;`
240	15	mihad	`@(posedge CLK) ;`
241	73	mihad	`end`
242			`endtask // addr_phase1`
243
244			`task addr_phase2 ;`
245			`input [31:0] address ;`
246			`input [3:0] bus_command ;`
247			`input make_parity_error;`
248			`begin`
249			`PAR_int <= #6 ^{AD, CBE, make_parity_error} ;`
250			`PAR_en <= #6 1'b1 ;`
251			`AD_int <= #6 address ;`
252			`CBE_int <= #6 bus_command ;`
253			`@(posedge CLK) ;`
254			`end`
255			`endtask`
256
257			`task first_and_last_data_phase ;`
258			`input rw ;`
259			`input [31:0] data ;`
260			`input [3:0] be ;`
261			`input make_addr_parity_error ;`
262			`input make_data_parity_error ;`
263			`output [2:0] received_termination ;`
264			`integer i ;`
265			`begin`
266			`FRAME_int <= #6 1'b1 ;`
267			`first_data_phase (rw, data, be, make_addr_parity_error, make_data_parity_error, received_termination) ;`
268			`end`
269			`endtask // first_and_last_data_phase`
270
271			`task first_data_phase ;`
272			`input rw ;`
273			`input [31:0] data ;`
274			`input [3:0] be ;`
275			`input make_addr_parity_error ;`
276			`input make_data_parity_error ;`
277			`output [2:0] received_termination ;`
278			`integer i ;`
279			`begin`
280			`PAR_int <= #6 ^{AD, CBE, make_addr_parity_error} ;`
281			`PAR_en <= #6 1'b1 ;`
282			`IRDY_en <= #6 1'b1 ;`
283			`IRDY_int <= #6 1'b0 ;`
284	92	mihad	`CBE_int <= #6 ~be ;`
285	73	mihad	`if (rw)`
286			`AD_int <= #6 data ;`
287	15	mihad	`else`
288	73	mihad	`AD_en <= #6 1'b0 ;`
289	15	mihad
290	73	mihad	`@(posedge CLK) ;`
291			`if (!rw)`
292			`PAR_en <= #6 1'b0 ;`
293			`else`
294			`PAR_int <= #6 ^{AD, CBE, make_data_parity_error} ;`
295
296			`i = 1 ;`
297			`while ( (i < 5) && (DEVSEL === 1'b1) )`
298	15	mihad	`begin`
299			`@(posedge CLK) ;`
300			`i = i + 1 ;`
301			`end`
302
303	73	mihad	`if (DEVSEL === 1'b1)`
304	15	mihad	`begin`
305	73	mihad	`received_termination = master_abort ;`
306	15	mihad	`end`
307	73	mihad	`else`
308			`begin`
309			`get_termination(received_termination);`
310			`end`
311			`end`
312			`endtask // first_data_phase`
313	15	mihad
314	73	mihad	`task subsequent_data_phase ;`
315			`input rw ;`
316			`input [31:0] data ;`
317			`input [3:0] be ;`
318			`input make_parity_error ;`
319			`output [2:0] received_termination ;`
320			`begin`
321			`if (rw)`
322			`begin`
323			`PAR_int <= #6 ^{AD, CBE, make_parity_error} ;`
324			`AD_int <= #6 data ;`
325			`end`
326	15	mihad
327	73	mihad	`IRDY_int <= #6 1'b0 ;`
328	92	mihad	`CBE_int <= #6 ~be ;`
329	73	mihad	`@(posedge CLK);`
330			`get_termination(received_termination);`
331			`end`
332			`endtask // subsequent_data_phase`
333
334			`task last_data_phase ;`
335			`input rw ;`
336			`input [31:0] data ;`
337			`input [3:0] be ;`
338			`input make_parity_error ;`
339			`output [2:0] received_termination ;`
340			`begin`
341			`FRAME_int <= #6 1'b1 ;`
342			`IRDY_int <= #6 1'b0 ;`
343			`if (rw)`
344			`begin`
345			`PAR_int <= #6 ^{AD, CBE, make_parity_error} ;`
346			`AD_int <= #6 data ;`
347			`end`
348
349	92	mihad	`CBE_int <= #6 ~be ;`
350	73	mihad
351			`@(posedge CLK);`
352			`get_termination(received_termination);`
353			`end`
354			`endtask // subsequent_data_phase`
355
356			`task get_termination ;`
357			`output [2:0] received_termination ;`
358			`begin`
359			`while ((TRDY === 1'b1) && (STOP === 1'b1))`
360			`@(posedge CLK) ;`
361
362			`if ( DEVSEL !== 1'b0 )`
363			`received_termination = target_abort ;`
364			`else if (TRDY !== 1'b1)`
365			`begin`
366			`if (STOP !== 1'b1)`
367			`received_termination = disconnect ;`
368			`else`
369			`received_termination = normal ;`
370			`end`
371			`else`
372			`received_termination = retry ;`
373			`end`
374			`endtask // get_termination`
375
376			`task finish_transaction ;`
377			`input rw ;`
378			`input make_parity_error ;`
379			`begin`
380			`if (rw)`
381			`PAR_int <= #6 ^{AD, CBE, make_parity_error} ;`
382
383			`IRDY_int <= #6 1'b1 ;`
384			`FRAME_en <= #6 1'b0 ;`
385			`AD_en <= #6 1'b0 ;`
386			`CBE_en <= #6 1'b0 ;`
387
388	15	mihad	`@(posedge CLK) ;`
389	73	mihad	`PAR_en <= #6 1'b0 ;`
390			`IRDY_en <= #6 1'b0 ;`
391	15	mihad	`end`
392	73	mihad	`endtask // finish_transaction`
393
394			`always@(e_finish_transaction)`
395			`begin`
396			`finish_transaction (write, make_parity_error_after_last_dataphase) ;`
397			`end`
398
399			`always@(e_transfers_done)`
400			`begin`
401
402			`if (FRAME !== 1'b1)`
403			`begin`
404			`FRAME_int <= #6 1'b1 ;`
405			`IRDY_int <= #6 1'b0 ;`
406			`if (write)`
407			`PAR_int <= #6 ^{CBE, AD} ;`
408
409			`@(posedge CLK) ;`
410			`end`
411
412			`-> e_finish_transaction ;`
413			`end`
414
415			`task insert_waits ;`
416			`input rw ;`
417			`input [2:0] wait_cycles ;`
418			`output [2:0] termination ;`
419			`reg [2:0] wait_cycles_left ;`
420			`reg stop_without_trdy_received ;`
421			`begin`
422			`stop_without_trdy_received = 1'b0 ;`
423			`wait_cycles_left = wait_cycles ;`
424
425			`termination = normal ;`
426
427			`PAR_int <= #6 ^{AD, CBE} ;`
428
429			`for (wait_cycles_left = wait_cycles ; (wait_cycles_left > 0) && !stop_without_trdy_received ; wait_cycles_left = wait_cycles_left - 1'b1)`
430			`begin`
431			`IRDY_int <= #6 1'b1 ;`
432			`@(posedge CLK) ;`
433
434			`PAR_int <= #6 ^{AD, CBE, 1'b1} ;`
435
436			`if ((STOP !== 1'b1) && (TRDY !== 1'b0))`
437			`begin`
438			`stop_without_trdy_received = 1'b1 ;`
439			`if (DEVSEL !== 1'b0)`
440			`termination = target_abort ;`
441			`else`
442			`termination = retry ;`
443			`end`
444			`end`
445			`end`
446			`endtask // insert_waits`
447	15	mihad	`endmodule`
448

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