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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  File name "wb_bus_mon.v"                                    ////
////                                                              ////
////  This file is part of the "PCI bridge" project               ////
////  http://www.opencores.org/cores/pci/                         ////
////                                                              ////
////  Author(s):                                                  ////
////      - mihad@opencores.org                                   ////
////      - Miha Dolenc                                           ////
////                                                              ////
////  All additional information is avaliable in the README.pdf   ////
////  file.                                                       ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2  2002/08/13 11:03:51  mihad
// Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image
//
// Revision 1.1  2002/02/01 13:39:43  mihad
// Initial testbench import. Still under development
//
// Revision 1.1  2001/08/06 18:12:58  mihad
// Pocasi delamo kompletno zadevo
//
//
 
`include "pci_testbench_defines.v"
// WISHBONE bus monitor module - it connects to WISHBONE master signals and
// monitors for any illegal combinations appearing on the bus.
module WB_BUS_MON(
                    CLK_I,
                    RST_I,
                            ACK_I,
                    ADDR_O,
                    CYC_O,
                    DAT_I,
                    DAT_O,
                    ERR_I,
                    RTY_I,
                    SEL_O,
                    STB_O,
                    WE_O,
                    TAG_I,
                    TAG_O,
                    CAB_O,
                    log_file_desc
                  ) ;
 
input                           CLK_I  ;
input                           RST_I  ;
input                           ACK_I  ;
input   [(`WB_ADDR_WIDTH-1):0]  ADDR_O ;
input                           CYC_O  ;
input   [(`WB_DATA_WIDTH-1):0]  DAT_I  ;
input   [(`WB_DATA_WIDTH-1):0]  DAT_O  ;
input                           ERR_I  ;
input                           RTY_I  ;
input   [(`WB_SEL_WIDTH-1):0]   SEL_O  ;
input                           STB_O  ;
input                           WE_O   ;
input   [(`WB_TAG_WIDTH-1):0] TAG_I  ;
input   [(`WB_TAG_WIDTH-1):0] TAG_O  ;
input                           CAB_O  ;
input [31:0] log_file_desc ;
 
always@(posedge CLK_I)
begin
    if (RST_I !== 1'b0)
    begin
        // when reset is applied, all control signals must be low
        if (CYC_O !== 1'b0)
        begin
            message_out("CYC_O active under reset") ;
        end
 
        if (STB_O !== 1'b0)
        begin
            message_out("STB_O active under reset") ;
        end
 
        if (ACK_I !== 1'b0)
            message_out("ACK_I active under reset") ;
 
        if (ERR_I !== 1'b0)
        begin
            message_out("ERR_I active under reset") ;
        end
 
        if (RTY_I !== 1'b0)
        begin
            message_out("RTY_I active under reset") ;
        end
 
    end // reset
    else
    if (CYC_O !== 1'b1)
    begin
        // when cycle indicator is low, all control signals must be low
        if (STB_O !== 1'b0)
        begin
            message_out("STB_O active without CYC_O being active") ;
        end
 
        if (ACK_I !== 1'b0)
        begin
            message_out("ACK_I active without CYC_O being active") ;
        end
 
        if (ERR_I !== 1'b0)
        begin
            message_out("ERR_I active without CYC_O being active") ;
        end
 
        if (RTY_I !== 1'b0)
        begin
            message_out("RTY_I active without CYC_O being active") ;
        end
 
    end // ~CYC_O
end
 
reg [`WB_DATA_WIDTH-1:0] previous_data_o ;
reg [`WB_DATA_WIDTH-1:0] previous_data_i ;
reg [`WB_ADDR_WIDTH-1:0] previous_address ;
reg [`WB_SEL_WIDTH-1:0] previous_sel ;
reg [`WB_TAG_WIDTH-1:0] previous_tag ;
reg                     previous_stb ;
reg                     previous_ack ;
reg                     previous_err ;
reg                     previous_rty ;
reg                     previous_cyc ;
reg                     previous_we  ;
 
always@(posedge CLK_I or posedge RST_I)
begin
    if (RST_I)
    begin
        previous_stb        <= 1'b0 ;
        previous_ack        <= 1'b0 ;
        previous_err        <= 1'b0 ;
        previous_rty        <= 1'b0 ;
        previous_cyc        <= 1'b0 ;
        previous_tag        <= 'd0  ;
        previous_we         <= 1'b0 ;
        previous_data_o     <= 0    ;
        previous_data_i     <= 0    ;
        previous_address    <= 0    ;
        previous_sel        <= 0    ;
    end
    else
    begin
        previous_stb        <= STB_O    ;
        previous_ack        <= ACK_I    ;
        previous_err        <= ERR_I    ;
        previous_rty        <= RTY_I    ;
        previous_cyc        <= CYC_O    ;
        previous_tag        <= TAG_O    ;
        previous_we         <= WE_O     ;
        previous_data_o     <= DAT_O    ;
        previous_data_i     <= DAT_I    ;
        previous_address    <= ADDR_O   ;
        previous_sel        <= SEL_O    ;
    end
end
 
// cycle monitor
always@(posedge CLK_I)
begin:cycle_monitor_blk
    reg master_can_change ;
    reg slave_can_change  ;
 
    if ((CYC_O !== 1'b0) & (RST_I !== 1'b1)) // cycle in progress
    begin
        // check for two control signals active at same edge
        if ( (ACK_I !== 1'b0) & (RTY_I !== 1'b0) )
        begin
            message_out("ACK_I and RTY_I asserted at the same time during cycle") ;
        end
 
        if ( (ACK_I !== 1'b0) & (ERR_I !== 1'b0) )
        begin
            message_out("ACK_I and ERR_I asserted at the same time during cycle") ;
        end
 
        if ( (RTY_I !== 1'b0) & (ERR_I !== 1'b0) )
        begin
            message_out("RTY_I and ERR_I asserted at the same time during cycle") ;
        end
 
        if (previous_cyc === 1'b1)
        begin
            if (previous_stb === 1'b1)
            begin
                if ((previous_ack === 1'b1) | (previous_rty === 1'b1) | (previous_err === 1'b1))
                    master_can_change = 1'b1 ;
                else
                    master_can_change = 1'b0 ;
            end
            else
            begin
                master_can_change = 1'b1 ;
            end
 
            if ((previous_ack === 1'b1) | (previous_err === 1'b1) | (previous_rty === 1'b1))
            begin
                if (previous_stb === 1'b1)
                    slave_can_change = 1'b1 ;
                else
                    slave_can_change = 1'b0 ;
            end
            else
            begin
                slave_can_change = 1'b1 ;
            end
        end
        else
        begin
            master_can_change = 1'b1 ;
            slave_can_change  = 1'b1 ;
        end
    end
    else
    begin
        master_can_change = 1'b1 ;
        slave_can_change  = 1'b1 ;
    end
 
    if (master_can_change !== 1'b1)
    begin
        if (CYC_O !== previous_cyc)
        begin
            message_out("Master violated WISHBONE protocol by changing the value of CYC_O signal at inappropriate time!") ;
        end
 
        if (STB_O !== previous_stb)
        begin
            message_out("Master violated WISHBONE protocol by changing the value of STB_O signal at inappropriate time!") ;
        end
 
        if (TAG_O !== previous_tag)
        begin
            message_out("Master violated WISHBONE protocol by changing the value of TAG_O signals at inappropriate time!") ;
        end
 
        if (ADDR_O !== previous_address)
        begin
            message_out("Master violated WISHBONE protocol by changing the value of ADR_O signals at inappropriate time!") ;
        end
 
        if (SEL_O !== previous_sel)
        begin
            message_out("Master violated WISHBONE protocol by changing the value of SEL_O signals at inappropriate time!") ;
        end
 
        if (WE_O !== previous_we)
        begin
            message_out("Master violated WISHBONE protocol by changing the value of WE_O signal at inappropriate time!") ;
        end
 
        if (WE_O !== 1'b0)
        begin
            if (DAT_O !== previous_data_o)
            begin
                message_out("Master violated WISHBONE protocol by changing the value of DAT_O signals at inappropriate time!") ;
            end
        end
    end
 
    if (slave_can_change !== 1'b1)
    begin
        if (previous_ack !== ACK_I)
        begin
            message_out("Slave violated WISHBONE protocol by changing the value of ACK_O signal at inappropriate time!") ;
        end
 
        if (previous_rty !== RTY_I)
        begin
            message_out("Slave violated WISHBONE protocol by changing the value of RTY_O signal at inappropriate time!") ;
        end
 
        if (previous_err !== ERR_I)
        begin
            message_out("Slave violated WISHBONE protocol by changing the value of ERR_O signal at inappropriate time!") ;
        end
 
        if (previous_data_i !== DAT_I)
        begin
            message_out("Slave violated WISHBONE protocol by changing the value of DAT_O signals at inappropriate time!") ;
        end
    end
end // cycle monitor
 
// CAB_O monitor - CAB_O musn't change during one cycle
reg [1:0] first_cab_val ;
always@(posedge CLK_I or RST_I)
begin
    if ((CYC_O === 0) || RST_I)
        first_cab_val <= 2'b00 ;
    else
    begin
        // cycle in progress - is this first clock edge in a cycle ?
        if (first_cab_val[1] === 1'b0)
            first_cab_val <= {1'b1, CAB_O} ;
        else if ( first_cab_val[0] !== CAB_O )
        begin
            $display("CAB_O value changed during cycle") ;
            $fdisplay(log_file_desc, "CAB_O value changed during cycle") ;
        end
    end
end // CAB_O monitor
 
// WE_O monitor for consecutive address bursts
reg [1:0] first_we_val ;
always@(posedge CLK_I or posedge RST_I)
begin
    if (~CYC_O || ~CAB_O || RST_I)
        first_we_val <= 2'b00 ;
    else
    if (STB_O)
    begin
        // cycle in progress - is this first clock edge in a cycle ?
        if (first_we_val[1] == 1'b0)
            first_we_val <= {1'b1, WE_O} ;
        else if ( first_we_val[0] != WE_O )
        begin
            $display("WE_O value changed during CAB cycle") ;
            $fdisplay(log_file_desc, "WE_O value changed during CAB cycle") ;
        end
    end
end // CAB_O monitor
 
// address monitor for consecutive address bursts
reg [`WB_ADDR_WIDTH:0] address ;
always@(posedge CLK_I or posedge RST_I)
begin
    if (~CYC_O || ~CAB_O || RST_I)
        address <= {(`WB_ADDR_WIDTH + 1){1'b0}} ;
    else
    begin
        if (STB_O && ACK_I)
        begin
            if (address[`WB_ADDR_WIDTH] == 1'b0)
            begin
                address <= (ADDR_O + `WB_SEL_WIDTH) | { 1'b1, {`WB_ADDR_WIDTH{1'b0}} } ;
            end
            else
            begin
                if ( address[(`WB_ADDR_WIDTH-1):0] != ADDR_O)
                begin
                    $display("Expected ADR_O = 0x%h, Actual = 0x%h", address[(`WB_ADDR_WIDTH-1):0], ADDR_O) ;
                    message_out("Consecutive address burst address incrementing incorrect") ;
                end
                else
                    address <= (ADDR_O + `WB_SEL_WIDTH) | { 1'b1, {`WB_ADDR_WIDTH{1'b0}} } ;
            end
        end
    end
end // address monitor
 
// data monitor
always@(posedge CLK_I or posedge RST_I)
begin:data_monitor_blk
    reg                       last_valid_we     ;
    reg [`WB_SEL_WIDTH - 1:0] last_valid_sel    ;
 
    if ((CYC_O !== 1'b0) & (RST_I !== 1'b1))
    begin
        if (STB_O !== 1'b0)
        begin
            last_valid_we   = WE_O  ;
            last_valid_sel  = SEL_O ;
 
            if ( (ADDR_O ^ ADDR_O) !== 0 )
            begin
                message_out("Master provided invalid ADR_O and qualified it with STB_O") ;
            end
 
            if ( (SEL_O ^ SEL_O) !== 0 )
            begin
                message_out("Master provided invalid SEL_O and qualified it with STB_O") ;
            end
 
            if ( WE_O )
            begin
                if (
                    ( SEL_O[0] & ((DAT_O[ 7:0 ] ^ DAT_O[ 7:0 ]) !== 0) ) |
                    ( SEL_O[1] & ((DAT_O[15:8 ] ^ DAT_O[15:8 ]) !== 0) ) |
                    ( SEL_O[2] & ((DAT_O[23:16] ^ DAT_O[23:16]) !== 0) ) |
                    ( SEL_O[3] & ((DAT_O[31:24] ^ DAT_O[31:24]) !== 0) )
                   )
                begin
                    message_out("Master provided invalid data during write and qualified it with STB_O") ;
                    $display("Byte select value: SEL_O = %b, Data bus value: DAT_O =  %h ", SEL_O, DAT_O) ;
                    $fdisplay(log_file_desc, "Byte select value: SEL_O = %b, Data bus value: DAT_O =  %h ", SEL_O, DAT_O) ;
                end
            end
 
            if ((TAG_O ^ TAG_O) !== 0)
            begin
                message_out("Master provided invalid TAG_O and qualified it with STB_O!") ;
            end
        end
 
        if ((last_valid_we !== 1'b1) & (ACK_I !== 1'b0))
        begin
            if (
                ( SEL_O[0] & ((DAT_I[ 7:0 ] ^ DAT_I[ 7:0 ]) !== 0) ) |
                ( SEL_O[1] & ((DAT_I[15:8 ] ^ DAT_I[15:8 ]) !== 0) ) |
                ( SEL_O[2] & ((DAT_I[23:16] ^ DAT_I[23:16]) !== 0) ) |
                ( SEL_O[3] & ((DAT_I[31:24] ^ DAT_I[31:24]) !== 0) )
               )
            begin
                message_out("Slave provided invalid data during read and qualified it with ACK_I") ;
                $display("Byte select value: SEL_O = %b, Data bus value: DAT_I =  %h ", last_valid_sel, DAT_I) ;
                $fdisplay(log_file_desc, "Byte select value: SEL_O = %b, Data bus value: DAT_I =  %h ", last_valid_sel, DAT_I) ;
            end
        end
    end
    else
    begin
        last_valid_sel = {`WB_SEL_WIDTH{1'bx}} ;
        last_valid_we  = 1'bx ;
    end
end
 
task message_out ;
    input [7999:0] message_i ;
begin
    $display("Time: %t", $time) ;
    $display("%m, %0s", message_i) ;
    $fdisplay(log_file_desc, "Time: %t", $time) ;
    $fdisplay(log_file_desc, "%m, %0s", message_i) ;
end
endtask // display message
 
endmodule // BUS_MON

Line No.	Rev	Author	Line
1	15	mihad	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// File name "wb_bus_mon.v" ////`
4			`//// ////`
5			`//// This file is part of the "PCI bridge" project ////`
6			`//// http://www.opencores.org/cores/pci/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - mihad@opencores.org ////`
10			`//// - Miha Dolenc ////`
11			`//// ////`
12			`//// All additional information is avaliable in the README.pdf ////`
13			`//// file. ////`
14			`//// ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42			`//`
43			`// CVS Revision History`
44			`//`
45			`// $Log: not supported by cvs2svn $`
46	106	mihad	`// Revision 1.2 2002/08/13 11:03:51 mihad`
47			`// Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image`
48			`//`
49	45	mihad	`// Revision 1.1 2002/02/01 13:39:43 mihad`
50			`// Initial testbench import. Still under development`
51			`//`
52	15	mihad	`// Revision 1.1 2001/08/06 18:12:58 mihad`
53			`// Pocasi delamo kompletno zadevo`
54			`//`
55			`//`
56
57			`include "pci_testbench_defines.v"
58			`// WISHBONE bus monitor module - it connects to WISHBONE master signals and`
59			`// monitors for any illegal combinations appearing on the bus.`
60			`module WB_BUS_MON(`
61			`CLK_I,`
62			`RST_I,`
63			`ACK_I,`
64			`ADDR_O,`
65			`CYC_O,`
66			`DAT_I,`
67			`DAT_O,`
68			`ERR_I,`
69			`RTY_I,`
70			`SEL_O,`
71			`STB_O,`
72			`WE_O,`
73			`TAG_I,`
74			`TAG_O,`
75			`CAB_O,`
76			`log_file_desc`
77			`) ;`
78
79			`input CLK_I ;`
80			`input RST_I ;`
81			`input ACK_I ;`
82			input [(`WB_ADDR_WIDTH-1):0] ADDR_O ;
83			`input CYC_O ;`
84			input [(`WB_DATA_WIDTH-1):0] DAT_I ;
85			input [(`WB_DATA_WIDTH-1):0] DAT_O ;
86			`input ERR_I ;`
87			`input RTY_I ;`
88			input [(`WB_SEL_WIDTH-1):0] SEL_O ;
89			`input STB_O ;`
90			`input WE_O ;`
91			input [(`WB_TAG_WIDTH-1):0] TAG_I ;
92			input [(`WB_TAG_WIDTH-1):0] TAG_O ;
93			`input CAB_O ;`
94			`input [31:0] log_file_desc ;`
95
96	106	mihad	`always@(posedge CLK_I)`
97	15	mihad	`begin`
98	106	mihad	`if (RST_I !== 1'b0)`
99	15	mihad	`begin`
100			`// when reset is applied, all control signals must be low`
101	106	mihad	`if (CYC_O !== 1'b0)`
102	15	mihad	`begin`
103	106	mihad	`message_out("CYC_O active under reset") ;`
104	15	mihad	`end`
105	106	mihad
106			`if (STB_O !== 1'b0)`
107	15	mihad	`begin`
108	106	mihad	`message_out("STB_O active under reset") ;`
109	15	mihad	`end`
110	106	mihad
111			`if (ACK_I !== 1'b0)`
112			`message_out("ACK_I active under reset") ;`
113
114			`if (ERR_I !== 1'b0)`
115	15	mihad	`begin`
116	106	mihad	`message_out("ERR_I active under reset") ;`
117	15	mihad	`end`
118	106	mihad
119			`if (RTY_I !== 1'b0)`
120	15	mihad	`begin`
121	106	mihad	`message_out("RTY_I active under reset") ;`
122	15	mihad	`end`
123	106	mihad
124	15	mihad	`end // reset`
125			`else`
126	106	mihad	`if (CYC_O !== 1'b1)`
127	15	mihad	`begin`
128			`// when cycle indicator is low, all control signals must be low`
129	106	mihad	`if (STB_O !== 1'b0)`
130	15	mihad	`begin`
131	106	mihad	`message_out("STB_O active without CYC_O being active") ;`
132	15	mihad	`end`
133	106	mihad
134			`if (ACK_I !== 1'b0)`
135	15	mihad	`begin`
136	106	mihad	`message_out("ACK_I active without CYC_O being active") ;`
137	15	mihad	`end`
138	106	mihad
139			`if (ERR_I !== 1'b0)`
140	15	mihad	`begin`
141	106	mihad	`message_out("ERR_I active without CYC_O being active") ;`
142	15	mihad	`end`
143	106	mihad
144			`if (RTY_I !== 1'b0)`
145	15	mihad	`begin`
146	106	mihad	`message_out("RTY_I active without CYC_O being active") ;`
147	15	mihad	`end`
148	106	mihad
149	15	mihad	`end // ~CYC_O`
150			`end`
151
152	106	mihad	reg [`WB_DATA_WIDTH-1:0] previous_data_o ;
153			reg [`WB_DATA_WIDTH-1:0] previous_data_i ;
154	15	mihad	reg [`WB_ADDR_WIDTH-1:0] previous_address ;
155			reg [`WB_SEL_WIDTH-1:0] previous_sel ;
156	106	mihad	reg [`WB_TAG_WIDTH-1:0] previous_tag ;
157	45	mihad	`reg previous_stb ;`
158			`reg previous_ack ;`
159			`reg previous_err ;`
160			`reg previous_rty ;`
161			`reg previous_cyc ;`
162	106	mihad	`reg previous_we ;`
163	15	mihad
164			`always@(posedge CLK_I or posedge RST_I)`
165			`begin`
166	45	mihad	`if (RST_I)`
167			`begin`
168	106	mihad	`previous_stb <= 1'b0 ;`
169			`previous_ack <= 1'b0 ;`
170			`previous_err <= 1'b0 ;`
171			`previous_rty <= 1'b0 ;`
172			`previous_cyc <= 1'b0 ;`
173			`previous_tag <= 'd0 ;`
174			`previous_we <= 1'b0 ;`
175			`previous_data_o <= 0 ;`
176			`previous_data_i <= 0 ;`
177			`previous_address <= 0 ;`
178			`previous_sel <= 0 ;`
179	45	mihad	`end`
180			`else`
181			`begin`
182	106	mihad	`previous_stb <= STB_O ;`
183			`previous_ack <= ACK_I ;`
184			`previous_err <= ERR_I ;`
185			`previous_rty <= RTY_I ;`
186			`previous_cyc <= CYC_O ;`
187			`previous_tag <= TAG_O ;`
188			`previous_we <= WE_O ;`
189			`previous_data_o <= DAT_O ;`
190			`previous_data_i <= DAT_I ;`
191			`previous_address <= ADDR_O ;`
192			`previous_sel <= SEL_O ;`
193	45	mihad	`end`
194			`end`
195
196			`// cycle monitor`
197			`always@(posedge CLK_I)`
198	106	mihad	`begin:cycle_monitor_blk`
199			`reg master_can_change ;`
200			`reg slave_can_change ;`
201
202			`if ((CYC_O !== 1'b0) & (RST_I !== 1'b1)) // cycle in progress`
203	15	mihad	`begin`
204	106	mihad	`// check for two control signals active at same edge`
205			`if ( (ACK_I !== 1'b0) & (RTY_I !== 1'b0) )`
206	15	mihad	`begin`
207	106	mihad	`message_out("ACK_I and RTY_I asserted at the same time during cycle") ;`
208			`end`
209	15	mihad
210	106	mihad	`if ( (ACK_I !== 1'b0) & (ERR_I !== 1'b0) )`
211			`begin`
212			`message_out("ACK_I and ERR_I asserted at the same time during cycle") ;`
213			`end`
214	15	mihad
215	106	mihad	`if ( (RTY_I !== 1'b0) & (ERR_I !== 1'b0) )`
216			`begin`
217			`message_out("RTY_I and ERR_I asserted at the same time during cycle") ;`
218			`end`
219	15	mihad
220	106	mihad	`if (previous_cyc === 1'b1)`
221			`begin`
222			`if (previous_stb === 1'b1)`
223			`begin`
224			`if ((previous_ack === 1'b1) \| (previous_rty === 1'b1) \| (previous_err === 1'b1))`
225			`master_can_change = 1'b1 ;`
226			`else`
227			`master_can_change = 1'b0 ;`
228	15	mihad	`end`
229			`else`
230			`begin`
231	106	mihad	`master_can_change = 1'b1 ;`
232	15	mihad	`end`
233
234	106	mihad	`if ((previous_ack === 1'b1) \| (previous_err === 1'b1) \| (previous_rty === 1'b1))`
235	15	mihad	`begin`
236	106	mihad	`if (previous_stb === 1'b1)`
237			`slave_can_change = 1'b1 ;`
238			`else`
239			`slave_can_change = 1'b0 ;`
240	15	mihad	`end`
241	106	mihad	`else`
242	15	mihad	`begin`
243	106	mihad	`slave_can_change = 1'b1 ;`
244	15	mihad	`end`
245	106	mihad	`end`
246			`else`
247			`begin`
248			`master_can_change = 1'b1 ;`
249			`slave_can_change = 1'b1 ;`
250			`end`
251			`end`
252			`else`
253			`begin`
254			`master_can_change = 1'b1 ;`
255			`slave_can_change = 1'b1 ;`
256			`end`
257	15	mihad
258	106	mihad	`if (master_can_change !== 1'b1)`
259			`begin`
260			`if (CYC_O !== previous_cyc)`
261			`begin`
262			`message_out("Master violated WISHBONE protocol by changing the value of CYC_O signal at inappropriate time!") ;`
263			`end`
264
265			`if (STB_O !== previous_stb)`
266			`begin`
267			`message_out("Master violated WISHBONE protocol by changing the value of STB_O signal at inappropriate time!") ;`
268			`end`
269
270			`if (TAG_O !== previous_tag)`
271			`begin`
272			`message_out("Master violated WISHBONE protocol by changing the value of TAG_O signals at inappropriate time!") ;`
273			`end`
274
275			`if (ADDR_O !== previous_address)`
276			`begin`
277			`message_out("Master violated WISHBONE protocol by changing the value of ADR_O signals at inappropriate time!") ;`
278			`end`
279
280			`if (SEL_O !== previous_sel)`
281			`begin`
282			`message_out("Master violated WISHBONE protocol by changing the value of SEL_O signals at inappropriate time!") ;`
283			`end`
284
285			`if (WE_O !== previous_we)`
286			`begin`
287			`message_out("Master violated WISHBONE protocol by changing the value of WE_O signal at inappropriate time!") ;`
288			`end`
289
290			`if (WE_O !== 1'b0)`
291			`begin`
292			`if (DAT_O !== previous_data_o)`
293	45	mihad	`begin`
294	106	mihad	`message_out("Master violated WISHBONE protocol by changing the value of DAT_O signals at inappropriate time!") ;`
295	45	mihad	`end`
296	106	mihad	`end`
297			`end`
298	45	mihad
299	106	mihad	`if (slave_can_change !== 1'b1)`
300	45	mihad	`begin`
301	106	mihad	`if (previous_ack !== ACK_I)`
302	45	mihad	`begin`
303	106	mihad	`message_out("Slave violated WISHBONE protocol by changing the value of ACK_O signal at inappropriate time!") ;`
304	45	mihad	`end`
305	106	mihad
306			`if (previous_rty !== RTY_I)`
307			`begin`
308			`message_out("Slave violated WISHBONE protocol by changing the value of RTY_O signal at inappropriate time!") ;`
309			`end`
310
311			`if (previous_err !== ERR_I)`
312			`begin`
313			`message_out("Slave violated WISHBONE protocol by changing the value of ERR_O signal at inappropriate time!") ;`
314			`end`
315
316			`if (previous_data_i !== DAT_I)`
317			`begin`
318			`message_out("Slave violated WISHBONE protocol by changing the value of DAT_O signals at inappropriate time!") ;`
319			`end`
320	45	mihad	`end`
321	15	mihad	`end // cycle monitor`
322
323			`// CAB_O monitor - CAB_O musn't change during one cycle`
324			`reg [1:0] first_cab_val ;`
325			`always@(posedge CLK_I or RST_I)`
326			`begin`
327			`if ((CYC_O === 0) \|\| RST_I)`
328			`first_cab_val <= 2'b00 ;`
329			`else`
330			`begin`
331			`// cycle in progress - is this first clock edge in a cycle ?`
332			`if (first_cab_val[1] === 1'b0)`
333			`first_cab_val <= {1'b1, CAB_O} ;`
334			`else if ( first_cab_val[0] !== CAB_O )`
335			`begin`
336			`$display("CAB_O value changed during cycle") ;`
337			`$fdisplay(log_file_desc, "CAB_O value changed during cycle") ;`
338			`end`
339			`end`
340			`end // CAB_O monitor`
341
342			`// WE_O monitor for consecutive address bursts`
343			`reg [1:0] first_we_val ;`
344			`always@(posedge CLK_I or posedge RST_I)`
345			`begin`
346			`if (~CYC_O \|\| ~CAB_O \|\| RST_I)`
347			`first_we_val <= 2'b00 ;`
348			`else`
349			`if (STB_O)`
350			`begin`
351			`// cycle in progress - is this first clock edge in a cycle ?`
352			`if (first_we_val[1] == 1'b0)`
353			`first_we_val <= {1'b1, WE_O} ;`
354			`else if ( first_we_val[0] != WE_O )`
355			`begin`
356			`$display("WE_O value changed during CAB cycle") ;`
357			`$fdisplay(log_file_desc, "WE_O value changed during CAB cycle") ;`
358			`end`
359			`end`
360			`end // CAB_O monitor`
361
362			`// address monitor for consecutive address bursts`
363			reg [`WB_ADDR_WIDTH:0] address ;
364			`always@(posedge CLK_I or posedge RST_I)`
365			`begin`
366			`if (~CYC_O \|\| ~CAB_O \|\| RST_I)`
367			address <= {(`WB_ADDR_WIDTH + 1){1'b0}} ;
368			`else`
369			`begin`
370			`if (STB_O && ACK_I)`
371			`begin`
372			if (address[`WB_ADDR_WIDTH] == 1'b0)
373	106	mihad	`begin`
374			address <= (ADDR_O + `WB_SEL_WIDTH) \| { 1'b1, {`WB_ADDR_WIDTH{1'b0}} } ;
375			`end`
376	15	mihad	`else`
377			`begin`
378			if ( address[(`WB_ADDR_WIDTH-1):0] != ADDR_O)
379			`begin`
380	106	mihad	$display("Expected ADR_O = 0x%h, Actual = 0x%h", address[(`WB_ADDR_WIDTH-1):0], ADDR_O) ;
381			`message_out("Consecutive address burst address incrementing incorrect") ;`
382	15	mihad	`end`
383			`else`
384	106	mihad	address <= (ADDR_O + `WB_SEL_WIDTH) \| { 1'b1, {`WB_ADDR_WIDTH{1'b0}} } ;
385	15	mihad	`end`
386			`end`
387			`end`
388			`end // address monitor`
389
390			`// data monitor`
391			`always@(posedge CLK_I or posedge RST_I)`
392	106	mihad	`begin:data_monitor_blk`
393			`reg last_valid_we ;`
394			reg [`WB_SEL_WIDTH - 1:0] last_valid_sel ;
395
396			`if ((CYC_O !== 1'b0) & (RST_I !== 1'b1))`
397	15	mihad	`begin`
398	106	mihad	`if (STB_O !== 1'b0)`
399	15	mihad	`begin`
400	106	mihad	`last_valid_we = WE_O ;`
401			`last_valid_sel = SEL_O ;`
402
403			`if ( (ADDR_O ^ ADDR_O) !== 0 )`
404	15	mihad	`begin`
405	106	mihad	`message_out("Master provided invalid ADR_O and qualified it with STB_O") ;`
406	15	mihad	`end`
407	106	mihad
408			`if ( (SEL_O ^ SEL_O) !== 0 )`
409			`begin`
410			`message_out("Master provided invalid SEL_O and qualified it with STB_O") ;`
411			`end`
412	15	mihad
413	106	mihad	`if ( WE_O )`
414			`begin`
415			`if (`
416			`( SEL_O[0] & ((DAT_O[ 7:0 ] ^ DAT_O[ 7:0 ]) !== 0) ) \|`
417			`( SEL_O[1] & ((DAT_O[15:8 ] ^ DAT_O[15:8 ]) !== 0) ) \|`
418			`( SEL_O[2] & ((DAT_O[23:16] ^ DAT_O[23:16]) !== 0) ) \|`
419			`( SEL_O[3] & ((DAT_O[31:24] ^ DAT_O[31:24]) !== 0) )`
420			`)`
421			`begin`
422			`message_out("Master provided invalid data during write and qualified it with STB_O") ;`
423			`$display("Byte select value: SEL_O = %b, Data bus value: DAT_O = %h ", SEL_O, DAT_O) ;`
424			`$fdisplay(log_file_desc, "Byte select value: SEL_O = %b, Data bus value: DAT_O = %h ", SEL_O, DAT_O) ;`
425			`end`
426			`end`
427
428			`if ((TAG_O ^ TAG_O) !== 0)`
429			`begin`
430			`message_out("Master provided invalid TAG_O and qualified it with STB_O!") ;`
431			`end`
432	15	mihad	`end`
433	106	mihad
434			`if ((last_valid_we !== 1'b1) & (ACK_I !== 1'b0))`
435	15	mihad	`begin`
436			`if (`
437	106	mihad	`( SEL_O[0] & ((DAT_I[ 7:0 ] ^ DAT_I[ 7:0 ]) !== 0) ) \|`
438			`( SEL_O[1] & ((DAT_I[15:8 ] ^ DAT_I[15:8 ]) !== 0) ) \|`
439			`( SEL_O[2] & ((DAT_I[23:16] ^ DAT_I[23:16]) !== 0) ) \|`
440			`( SEL_O[3] & ((DAT_I[31:24] ^ DAT_I[31:24]) !== 0) )`
441	15	mihad	`)`
442			`begin`
443	106	mihad	`message_out("Slave provided invalid data during read and qualified it with ACK_I") ;`
444			`$display("Byte select value: SEL_O = %b, Data bus value: DAT_I = %h ", last_valid_sel, DAT_I) ;`
445			`$fdisplay(log_file_desc, "Byte select value: SEL_O = %b, Data bus value: DAT_I = %h ", last_valid_sel, DAT_I) ;`
446	15	mihad	`end`
447			`end`
448			`end`
449	106	mihad	`else`
450			`begin`
451			last_valid_sel = {`WB_SEL_WIDTH{1'bx}} ;
452			`last_valid_we = 1'bx ;`
453			`end`
454	15	mihad	`end`
455
456	106	mihad	`task message_out ;`
457			`input [7999:0] message_i ;`
458	15	mihad	`begin`
459	106	mihad	`$display("Time: %t", $time) ;`
460			`$display("%m, %0s", message_i) ;`
461			`$fdisplay(log_file_desc, "Time: %t", $time) ;`
462			`$fdisplay(log_file_desc, "%m, %0s", message_i) ;`
463	15	mihad	`end`
464	106	mihad	`endtask // display message`
465
466	15	mihad	`endmodule // BUS_MON`

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