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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  File name "wb_master_behavioral.v"                          ////
////                                                              ////
////  This file is part of the "PCI bridge" project               ////
////  http://www.opencores.org/cores/pci/                         ////
////                                                              ////
////  Author(s):                                                  ////
////      - Miha Dolenc (mihad@opencores.org)                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Miha Dolenc, mihad@opencores.org          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2  2003/06/12 02:30:39  mihad
// Update!
//
// Revision 1.1  2002/02/01 13:39:43  mihad
// Initial testbench import. Still under development
//
 
`include "pci_testbench_defines.v"
module WB_MASTER_BEHAVIORAL
(
    CLK_I,
    RST_I,
    TAG_I,
    TAG_O,
    ACK_I,
    ADR_O,
    CYC_O,
    DAT_I,
    DAT_O,
    ERR_I,
    RTY_I,
    SEL_O,
    STB_O,
    WE_O,
    CAB_O
);
 
    input                    CLK_I;
    input                    RST_I;
    input    `WB_TAG_TYPE    TAG_I;
    output   `WB_TAG_TYPE    TAG_O;
    input                    ACK_I;
    output   `WB_ADDR_TYPE   ADR_O;
    output                   CYC_O;
    input    `WB_DATA_TYPE   DAT_I;
    output   `WB_DATA_TYPE   DAT_O;
    input                    ERR_I;
    input                    RTY_I;
    output   `WB_SEL_TYPE    SEL_O;
    output                   STB_O;
    output                   WE_O;
    output                   CAB_O;
 
// instantiate low level master module
WB_MASTER32 wbm_low_level
(
    .CLK_I(CLK_I),
    .RST_I(RST_I),
    .TAG_I(TAG_I),
    .TAG_O(TAG_O),
    .ACK_I(ACK_I),
    .ADR_O(ADR_O),
    .CYC_O(CYC_O),
    .DAT_I(DAT_I),
    .DAT_O(DAT_O),
    .ERR_I(ERR_I),
    .RTY_I(RTY_I),
    .SEL_O(SEL_O),
    .STB_O(STB_O),
    .WE_O(WE_O),
    .CAB_O(CAB_O)
) ;
 
// block read and write buffers definition
// single write buffer
reg `WRITE_STIM_TYPE  blk_write_data    [0:(`MAX_BLK_SIZE - 1)] ;
// read stimulus buffer - addresses, tags, selects etc.
reg `READ_STIM_TYPE   blk_read_data_in  [0:(`MAX_BLK_SIZE - 1)] ;
// read return buffer - data and tags received while performing block reads
reg `READ_RETURN_TYPE blk_read_data_out [0:(`MAX_BLK_SIZE - 1)] ;
 
// single write task
task wb_single_write ;
    input `WRITE_STIM_TYPE write_data ;
    input `WB_TRANSFER_FLAGS   write_flags ;
    inout `WRITE_RETURN_TYPE return ;
    reg in_use ;
    reg cab ;
    reg ok ;
    integer cyc_count ;
    integer rty_count ;
    reg retry ;
    reg [2:0] use_cti ;
    reg [1:0] use_bte ;
begin:main
 
    return`TB_ERROR_BIT = 1'b0 ;
    cab = 0 ;
    return`CYC_ACTUAL_TRANSFER = 0 ;
    rty_count = 0 ;
 
    // check if task was called before previous call finished
    if ( in_use === 1 )
    begin
        $display("*E, wb_single_write routine re-entered! Time %t ", $time) ;
        return`TB_ERROR_BIT = 1'b1 ;
        disable main ;
    end
 
    in_use = 1 ;
 
    retry = 1 ;
 
    use_cti = {$random} % 8 ;
    if (use_cti === 3'b010)
        use_cti = 3'b111 ;
    else if (use_cti === 3'b001)
        use_cti = 3'b000 ;
 
    use_bte = {$random} % 4 ;
 
    write_data`WRITE_TAG_STIM = {use_cti, use_bte} ;
 
    while (retry === 1)
    begin
        // synchronize operation to clock
        if (write_flags`WB_FAST_B2B !== 1'b1)
            @(posedge CLK_I) ;
 
        wbm_low_level.start_cycle(cab, 1'b1, write_flags`WB_FAST_B2B, ok) ;
        if ( ok !== 1 )
        begin
            $display("*E, Failed to initialize cycle! Routine wb_single_write, Time %t ", $time) ;
            return`TB_ERROR_BIT = 1'b1 ;
            disable main ;
        end
 
        // first insert initial wait states
        cyc_count = write_flags`INIT_WAITS ;
        while ( cyc_count > 0 )
        begin
            @(posedge CLK_I) ;
            cyc_count = cyc_count - 1 ;
        end
 
        wbm_low_level.wbm_write(write_data, return) ;
 
        if ( return`CYC_ERR === 0 && return`CYC_ACK === 0 && return`CYC_RTY === 1 && write_flags`WB_TRANSFER_AUTO_RTY === 1 && return`TB_ERROR_BIT === 0)
        begin
            if ( rty_count === `WB_TB_MAX_RTY )
            begin
                 $display("*E, maximum number of retries received - access will not be repeated anymore! Routine wb_single_write, Time %t ", $time) ;
                 retry = 0 ;
            end
            else
            begin
                retry     = 1 ;
                rty_count = rty_count + 1 ;
            end
        end
        else
            retry = 0 ;
 
        // if test bench error bit is set, there is no meaning in introducing subsequent wait states
        if ( return`TB_ERROR_BIT !== 0 )
        begin
            @(posedge CLK_I) ;
            wbm_low_level.end_cycle ;
            disable main ;
        end
 
        cyc_count = write_flags`SUBSEQ_WAITS ;
        while ( cyc_count > 0 )
        begin
            @(posedge CLK_I) ;
            cyc_count = cyc_count - 1 ;
        end
 
        wbm_low_level.end_cycle ;
    end
 
    in_use = 0 ;
 
end //main
endtask // wb_single_write
 
task wb_single_read ;
    input `READ_STIM_TYPE read_data ;
    input `WB_TRANSFER_FLAGS   read_flags ;
    inout `READ_RETURN_TYPE return ;
    reg in_use ;
    reg cab ;
    reg ok ;
    integer cyc_count ;
    integer rty_count ;
    reg retry ;
    reg [2:0] use_cti ;
    reg [1:0] use_bte ;
begin:main
 
    return`TB_ERROR_BIT = 1'b0 ;
    cab = 0 ;
    rty_count = 0 ;
    return`CYC_ACTUAL_TRANSFER = 0 ;
 
    // check if task was called before previous call finished
    if ( in_use === 1 )
    begin
        $display("*E, wb_single_read routine re-entered! Time %t ", $time) ;
        return`TB_ERROR_BIT = 1'b1 ;
        disable main ;
    end
 
    in_use = 1 ;
 
    retry = 1 ;
 
    use_cti = {$random} % 8 ;
    if (use_cti === 3'b010)
        use_cti = 3'b111 ;
    else if (use_cti === 3'b001)
        use_cti = 3'b000 ;
 
    use_bte = {$random} % 4 ;
 
    read_data`READ_TAG_STIM = {use_cti, use_bte} ;
 
    while (retry === 1)
    begin
        // synchronize operation to clock
        if (read_flags`WB_FAST_B2B !== 1'b1)
            @(posedge CLK_I) ;
 
        wbm_low_level.start_cycle(cab, 1'b0, read_flags`WB_FAST_B2B, ok) ;
        if ( ok !== 1 )
        begin
            $display("*E, Failed to initialize cycle! Routine wb_single_read, Time %t ", $time) ;
            return`TB_ERROR_BIT = 1'b1 ;
            disable main ;
        end
 
        // first insert initial wait states
        cyc_count = read_flags`INIT_WAITS ;
        while ( cyc_count > 0 )
        begin
            @(posedge CLK_I) ;
            cyc_count = cyc_count - 1 ;
        end
 
        wbm_low_level.wbm_read(read_data, return) ;
 
        if ( return`CYC_ERR === 0 && return`CYC_ACK === 0 && return`CYC_RTY === 1 && read_flags`WB_TRANSFER_AUTO_RTY === 1 && return`TB_ERROR_BIT === 0)
        begin
           if ( rty_count === `WB_TB_MAX_RTY )
            begin
                 $display("*E, maximum number of retries received - access will not be repeated anymore! Routine wb_single_read, Time %t ", $time) ;
                 retry = 0 ;
            end
            else
            begin
                retry     = 1 ;
                rty_count = rty_count + 1 ;
            end
        end
        else
        begin
            retry = 0 ;
        end
 
        // if test bench error bit is set, there is no meaning in introducing subsequent wait states
        if ( return`TB_ERROR_BIT !== 0 )
        begin
            @(posedge CLK_I) ;
            wbm_low_level.end_cycle ;
            disable main ;
        end
 
        cyc_count = read_flags`SUBSEQ_WAITS ;
        while ( cyc_count > 0 )
        begin
            @(posedge CLK_I) ;
            cyc_count = cyc_count - 1 ;
        end
 
        wbm_low_level.end_cycle ;
    end
 
    in_use = 0 ;
 
end //main
endtask // wb_single_read
 
task wb_RMW_read ;
    input `READ_STIM_TYPE read_data ;
    input `WB_TRANSFER_FLAGS   read_flags ;
    inout `READ_RETURN_TYPE return ;
    reg in_use ;
    reg cab ;
    reg ok ;
    integer cyc_count ;
    integer rty_count ;
    reg retry ;
    reg [2:0] use_cti ;
    reg [1:0] use_bte ;
begin:main
 
    return`TB_ERROR_BIT = 1'b0 ;
    cab = 0 ;
    rty_count = 0 ;
    return`CYC_ACTUAL_TRANSFER = 0 ;
 
    // check if task was called before previous call finished
    if ( in_use === 1 )
    begin
        $display("*E, wb_RMW_read routine re-entered! Time %t ", $time) ;
        return`TB_ERROR_BIT = 1'b1 ;
        disable main ;
    end
 
    in_use = 1 ;
 
    retry = 1 ;
 
    use_cti = {$random} % 8 ;
    if (use_cti === 3'b010)
        use_cti = 3'b111 ;
    else if (use_cti === 3'b001)
        use_cti = 3'b000 ;
 
    use_bte = {$random} % 4 ;
 
    read_data`READ_TAG_STIM = {use_cti, use_bte} ;
 
    while (retry === 1)
    begin
        // synchronize operation to clock
        if (read_flags`WB_FAST_B2B !== 1'b1)
            @(posedge CLK_I) ;
 
        wbm_low_level.start_cycle(cab, 1'b0, read_flags`WB_FAST_B2B, ok) ;
        if ( ok !== 1 )
        begin
            $display("*E, Failed to initialize cycle! Routine wb_RMW_read, Time %t ", $time) ;
            return`TB_ERROR_BIT = 1'b1 ;
            disable main ;
        end
 
        // first insert initial wait states
        cyc_count = read_flags`INIT_WAITS ;
        while ( cyc_count > 0 )
        begin
            @(posedge CLK_I) ;
            cyc_count = cyc_count - 1 ;
        end
 
        wbm_low_level.wbm_read(read_data, return) ;
 
        if ( return`CYC_ERR === 0 && return`CYC_ACK === 0 && return`CYC_RTY === 1 && read_flags`WB_TRANSFER_AUTO_RTY === 1 && return`TB_ERROR_BIT === 0)
        begin
           if ( rty_count === `WB_TB_MAX_RTY )
            begin
                 $display("*E, maximum number of retries received - access will not be repeated anymore! Routine wb_RMW_read, Time %t ", $time) ;
                 retry = 0 ;
            end
            else
            begin
                retry     = 1 ;
                rty_count = rty_count + 1 ;
            end
        end
        else
        begin
            retry = 0 ;
        end
 
        // if test bench error bit is set, there is no meaning in introducing subsequent wait states
        if ( return`TB_ERROR_BIT !== 0 )
        begin
            @(posedge CLK_I) ;
            wbm_low_level.end_cycle ;
            disable main ;
        end
 
        cyc_count = read_flags`SUBSEQ_WAITS ;
        while ( cyc_count > 0 )
        begin
            @(posedge CLK_I) ;
            cyc_count = cyc_count - 1 ;
        end
 
        if (retry === 1)
            wbm_low_level.end_cycle ;
        else
            wbm_low_level.modify_cycle ;
    end
 
    in_use = 0 ;
 
end //main
endtask // wb_RMW_read
 
task wb_RMW_write ;
    input `WRITE_STIM_TYPE write_data ;
    input `WB_TRANSFER_FLAGS   write_flags ;
    inout `WRITE_RETURN_TYPE return ;
    reg in_use ;
    reg cab ;
    reg ok ;
    integer cyc_count ;
    integer rty_count ;
    reg retry ;
    reg [2:0] use_cti ;
    reg [1:0] use_bte ;
begin:main
 
    return`TB_ERROR_BIT = 1'b0 ;
    cab = 0 ;
    return`CYC_ACTUAL_TRANSFER = 0 ;
    rty_count = 0 ;
 
    // check if task was called before previous call finished
    if ( in_use === 1 )
    begin
        $display("*E, wb_RMW_write routine re-entered! Time %t ", $time) ;
        return`TB_ERROR_BIT = 1'b1 ;
        disable main ;
    end
 
    in_use = 1 ;
 
    retry = 1 ;
 
    use_cti = {$random} % 8 ;
    if (use_cti === 3'b010)
        use_cti = 3'b111 ;
    else if (use_cti === 3'b001)
        use_cti = 3'b000 ;
 
    use_bte = {$random} % 4 ;
 
    write_data`WRITE_TAG_STIM = {use_cti, use_bte} ;
 
    while (retry === 1)
    begin
        // synchronize operation to clock
        if (write_flags`WB_FAST_B2B !== 1'b1)
            @(posedge CLK_I) ;
 
        ok = 1 ;
        if (rty_count !== 0)
            wbm_low_level.start_cycle(cab, 1'b1, write_flags`WB_FAST_B2B, ok) ;
 
        if ( ok !== 1 )
        begin
            $display("*E, Failed to initialize cycle! Routine wb_single_write, Time %t ", $time) ;
            return`TB_ERROR_BIT = 1'b1 ;
            disable main ;
        end
 
        // first insert initial wait states
        cyc_count = write_flags`INIT_WAITS ;
        while ( cyc_count > 0 )
        begin
            @(posedge CLK_I) ;
            cyc_count = cyc_count - 1 ;
        end
 
        wbm_low_level.wbm_write(write_data, return) ;
 
        if ( return`CYC_ERR === 0 && return`CYC_ACK === 0 && return`CYC_RTY === 1 && write_flags`WB_TRANSFER_AUTO_RTY === 1 && return`TB_ERROR_BIT === 0)
        begin
            if ( rty_count === `WB_TB_MAX_RTY )
            begin
                 $display("*E, maximum number of retries received - access will not be repeated anymore! Routine wb_single_write, Time %t ", $time) ;
                 retry = 0 ;
            end
            else
            begin
                retry     = 1 ;
                rty_count = rty_count + 1 ;
            end
        end
        else
            retry = 0 ;
 
        // if test bench error bit is set, there is no meaning in introducing subsequent wait states
        if ( return`TB_ERROR_BIT !== 0 )
        begin
            @(posedge CLK_I) ;
            wbm_low_level.end_cycle ;
            disable main ;
        end
 
        cyc_count = write_flags`SUBSEQ_WAITS ;
        while ( cyc_count > 0 )
        begin
            @(posedge CLK_I) ;
            cyc_count = cyc_count - 1 ;
        end
 
        wbm_low_level.end_cycle ;
    end
 
    in_use = 0 ;
 
end //main
endtask // wb_RMW_write
 
task wb_block_write ;
    input  `WB_TRANSFER_FLAGS write_flags ;
    inout  `WRITE_RETURN_TYPE return ;
 
    reg in_use ;
    reg `WRITE_STIM_TYPE  current_write ;
    reg cab ;
    reg ok ;
    integer cyc_count ;
    integer rty_count ;
    reg end_blk ;
    reg [2:0] use_cti    ;
    reg [1:0] use_bte    ;
begin:main
 
    return`CYC_ACTUAL_TRANSFER = 0 ;
    rty_count = 0 ;
 
    // check if task was called before previous call finished
    if ( in_use === 1 )
    begin
        $display("*E, wb_block_write routine re-entered! Time %t ", $time) ;
        return`TB_ERROR_BIT = 1'b1 ;
        disable main ;
    end
 
    if (write_flags`WB_TRANSFER_SIZE > `MAX_BLK_SIZE)
    begin
        $display("*E, number of transfers passed to wb_block_write routine exceeds defined maximum transaction length! Time %t", $time) ;
        return`TB_ERROR_BIT = 1'b1 ;
        disable main ;
    end
 
    in_use = 1 ;
    if (write_flags`WB_FAST_B2B !== 1'b1)
        @(posedge CLK_I) ;
 
    cab = write_flags`WB_TRANSFER_CAB ;
 
    current_write = blk_write_data[0] ;
 
    if (cab)
    begin:select_burst_type_blk
        reg [31:0] burst_start_adr ;
 
        use_cti = 3'b010 ;
 
        burst_start_adr = current_write`WRITE_ADDRESS ;
        if (burst_start_adr[5:2] === 4'b0000)
            use_bte = {$random} % 4 ;
        else if (burst_start_adr[4:2] === 3'b000)
            use_bte = {$random} % 3 ;
        else if (burst_start_adr[3:2] === 2'b00)
            use_bte = {$random} % 2 ;
        else
            use_bte = 2'b00 ;
    end
    else
    begin
        if ( (current_write`WRITE_TAG_STIM === 0) | (current_write`WRITE_TAG_STIM === {`WB_TAG_WIDTH{1'bx}}) )
        begin
            use_cti = {$random} % 8 ;
            if (use_cti === 3'b010)
                use_cti = 3'b111 ;
            else if (use_cti === 3'b001)
                use_cti = 3'b000 ;
 
            use_bte = {$random} % 4 ;
        end
        else
        begin
            {use_cti, use_bte} = current_write`WRITE_TAG_STIM ;
        end
    end
 
    wbm_low_level.start_cycle(cab, 1'b1, write_flags`WB_FAST_B2B, ok) ;
    if ( ok !== 1 )
    begin
        $display("*E, Failed to initialize cycle! Routine wb_block_write, Time %t ", $time) ;
        return`TB_ERROR_BIT = 1'b1 ;
        disable main ;
    end
 
    // insert initial wait states
    cyc_count = write_flags`INIT_WAITS ;
    while ( cyc_count > 0 )
    begin
        @(posedge CLK_I) ;
        cyc_count = cyc_count - 1 ;
    end
 
    end_blk = 0 ;
    while (end_blk === 0)
    begin
 
        // collect data for current data beat
        current_write = blk_write_data[return`CYC_ACTUAL_TRANSFER] ;
 
        if (cab)
        begin
            if ((return`CYC_ACTUAL_TRANSFER + 1'b1) >= write_flags`WB_TRANSFER_SIZE)
                use_cti = 3'b111 ;
        end
 
        current_write`WRITE_TAG_STIM = {use_cti, use_bte} ;
 
        wbm_low_level.wbm_write(current_write, return) ;
 
        // check result of write operation
        // check for severe test error
        if (return`TB_ERROR_BIT !== 0)
        begin
           @(posedge CLK_I) ;
           wbm_low_level.end_cycle ;
           disable main ;
        end
 
        // slave returned error or error signal had invalid value
        if (return`CYC_ERR !== 0)
            end_blk = 1 ;
 
        if (
            (return`CYC_RTY !== 0) && (return`CYC_RTY !== 1) ||
            (return`CYC_ACK !== 0) && (return`CYC_ACK !== 1) ||
            (return`CYC_ERR !== 0) && (return`CYC_ERR !== 1)
           )
        begin
            end_blk = 1 ;
            $display("*E, at least one slave response signal was invalid when cycle finished! Routine wb_block_write, Time %t ", $time) ;
            $display("ACK = %b \t RTY_O = %b \t ERR_O = %b \t", return`CYC_ACK, return`CYC_RTY, return`CYC_ERR) ;
        end
 
        if ((return`CYC_RTY === 1) && (write_flags`WB_TRANSFER_AUTO_RTY !== 1))
            end_blk = 1 ;
 
        if ((return`CYC_RTY === 1) && (write_flags`WB_TRANSFER_AUTO_RTY === 1))
        begin
            if ( rty_count === `WB_TB_MAX_RTY )
            begin
                 $display("*E, maximum number of retries received - access will not be repeated anymore! Routine wb_block_write, Time %t ", $time) ;
                 end_blk = 1 ;
            end
            else
            begin
                if (cab)
                begin
                    use_bte = 2'b00 ;
                end
 
                rty_count = rty_count + 1 ;
            end
        end
        else
            rty_count = 0 ;
 
        // check if slave responded at all
        if (return`CYC_RESPONSE === 0)
            end_blk = 1 ;
 
        // check if all intended data was transfered
        if (return`CYC_ACTUAL_TRANSFER === write_flags`WB_TRANSFER_SIZE)
            end_blk = 1 ;
 
        // insert subsequent wait cycles, if transfer is supposed to continue
        if ( end_blk === 0 )
        begin
            cyc_count = write_flags`SUBSEQ_WAITS ;
            while ( cyc_count > 0 )
            begin
                @(posedge CLK_I) ;
                cyc_count = cyc_count - 1 ;
            end
        end
 
        if ( (end_blk === 0) && (return`CYC_RTY === 1) )
        begin
            if (write_flags`WB_FAST_B2B !== 1'b1)
            begin
                wbm_low_level.end_cycle ;
                @(posedge CLK_I) ;
                wbm_low_level.start_cycle(cab, 1'b1, 1'b0, ok) ;
                if ( ok !== 1 )
                begin
                    $display("*E, Failed to initialize cycle! Routine wb_block_write, Time %t ", $time) ;
                    return`TB_ERROR_BIT = 1'b1 ;
                    end_blk = 1 ;
                end
            end
        end
    end //while
 
    wbm_low_level.end_cycle ;
    in_use = 0 ;
end //main
endtask //wb_block_write
 
task wb_block_read ;
    input  `WB_TRANSFER_FLAGS      read_flags ;
    inout `READ_RETURN_TYPE       return ;
 
    reg in_use ;
    reg `READ_STIM_TYPE  current_read ;
    reg cab ;
    reg ok ;
    integer cyc_count ;
    integer rty_count ;
    reg end_blk ;
    integer transfered ;
    reg [2:0] use_cti ;
    reg [1:0] use_bte ;
begin:main
 
    return`CYC_ACTUAL_TRANSFER = 0 ;
    transfered = 0 ;
    rty_count = 0 ;
 
    // check if task was called before previous call finished
    if ( in_use === 1 )
    begin
        $display("*E, wb_block_read routine re-entered! Time %t ", $time) ;
        return`TB_ERROR_BIT = 1'b1 ;
        disable main ;
    end
 
    if (read_flags`WB_TRANSFER_SIZE > `MAX_BLK_SIZE)
    begin
        $display("*E, number of transfers passed to wb_block_read routine exceeds defined maximum transaction length! Time %t", $time) ;
        return`TB_ERROR_BIT = 1'b1 ;
        disable main ;
    end
 
    in_use = 1 ;
    @(posedge CLK_I) ;
    cab = read_flags`WB_TRANSFER_CAB ;
 
    if (cab)
    begin:select_burst_type_blk
        reg [31:0] burst_start_adr ;
 
        use_cti = 3'b010 ;
 
        current_read = blk_read_data_in[0] ;
        burst_start_adr = current_read`READ_ADDRESS ;
        if (burst_start_adr[5:2] === 4'b0000)
            use_bte = {$random} % 4 ;
        else if (burst_start_adr[4:2] === 3'b000)
            use_bte = {$random} % 3 ;
        else if (burst_start_adr[3:2] === 2'b00)
            use_bte = {$random} % 2 ;
        else
            use_bte = 2'b00 ;
    end
 
    wbm_low_level.start_cycle(cab, 1'b0, read_flags`WB_FAST_B2B, ok) ;
 
    if ( ok !== 1 )
    begin
        $display("*E, Failed to initialize cycle! Routine wb_block_read, Time %t ", $time) ;
        return`TB_ERROR_BIT = 1'b1 ;
        disable main ;
    end
 
    // insert initial wait states
    cyc_count = read_flags`INIT_WAITS ;
    while ( cyc_count > 0 )
    begin
        @(posedge CLK_I) ;
        cyc_count = cyc_count - 1 ;
    end
 
    end_blk = 0 ;
    while (end_blk === 0)
    begin
        // collect data for current data beat
        current_read = blk_read_data_in[return`CYC_ACTUAL_TRANSFER] ;
 
        if (cab)
        begin
            if ((return`CYC_ACTUAL_TRANSFER + 1'b1) >= read_flags`WB_TRANSFER_SIZE)
                use_cti = 3'b111 ;
        end
 
        current_read`READ_TAG_STIM = {use_cti, use_bte} ;
 
        wbm_low_level.wbm_read(current_read, return) ;
 
        if ( transfered !== return`CYC_ACTUAL_TRANSFER )
        begin
            blk_read_data_out[transfered] = return ;
            transfered = return`CYC_ACTUAL_TRANSFER ;
        end
 
        // check result of read operation
        // check for severe test error
        if (return`TB_ERROR_BIT !== 0)
        begin
           @(posedge CLK_I) ;
           wbm_low_level.end_cycle ;
           disable main ;
        end
 
        // slave returned error or error signal had invalid value
        if (return`CYC_ERR !== 0)
            end_blk = 1 ;
 
        if (
            (return`CYC_RTY !== 0) && (return`CYC_RTY !== 1) ||
            (return`CYC_ACK !== 0) && (return`CYC_ACK !== 1) ||
            (return`CYC_ERR !== 0) && (return`CYC_ERR !== 1)
           )
        begin
            end_blk = 1 ;
            $display("*E, at least one slave response signal was invalid when cycle finished! Routine wb_block_read, Time %t ", $time) ;
            $display("ACK = %b \t RTY_O = %b \t ERR_O = %b \t", return`CYC_ACK, return`CYC_RTY, return`CYC_ERR) ;
        end
 
        if ((return`CYC_RTY === 1) && (read_flags`WB_TRANSFER_AUTO_RTY !== 1))
            end_blk = 1 ;
 
        if ((return`CYC_RTY === 1) && (read_flags`WB_TRANSFER_AUTO_RTY === 1))
        begin
            if ( rty_count === `WB_TB_MAX_RTY )
            begin
                 $display("*E, maximum number of retries received - access will not be repeated anymore! Routine wb_block_read, Time %t ", $time) ;
                 end_blk = 1 ;
            end
            else
            begin
                if (cab)
                begin
                    use_bte = 2'b00 ;
                end
 
                rty_count = rty_count + 1 ;
            end
        end
        else
            rty_count = 0 ;
 
        // check if slave responded at all
        if (return`CYC_RESPONSE === 0)
            end_blk = 1 ;
 
        // check if all intended data was transfered
        if (return`CYC_ACTUAL_TRANSFER === read_flags`WB_TRANSFER_SIZE)
            end_blk = 1 ;
 
        // insert subsequent wait cycles, if transfer is supposed to continue
        if ( end_blk === 0 )
        begin
            cyc_count = read_flags`SUBSEQ_WAITS ;
            while ( cyc_count > 0 )
            begin
                @(posedge CLK_I) ;
                cyc_count = cyc_count - 1 ;
            end
        end
 
        if ( (end_blk === 0) && (return`CYC_RTY === 1) )
        begin
            if (read_flags`WB_FAST_B2B !== 1'b1)
            begin
                wbm_low_level.end_cycle ;
                @(posedge CLK_I) ;
                wbm_low_level.start_cycle(cab, 1'b0, 1'b0, ok) ;
                if ( ok !== 1 )
                begin
                    $display("*E, Failed to initialize cycle! Routine wb_block_read, Time %t ", $time) ;
                    return`TB_ERROR_BIT = 1'b1 ;
                    end_blk = 1 ;
                end
            end
        end
    end //while
 
    wbm_low_level.end_cycle ;
    in_use = 0 ;
end //main
endtask //wb_block_read
 
task shift_write_buffer ;
    input [31:0] shift_num ;
    integer i ;
begin
    if (shift_num < `MAX_BLK_SIZE)
    begin
 
        for (i = 0 ; i + shift_num < `MAX_BLK_SIZE ; i = i + 1)
        begin
            blk_write_data[i] = blk_write_data[i + shift_num] ;
        end
 
        for (i = (`MAX_BLK_SIZE - shift_num) ; i < `MAX_BLK_SIZE ; i = i + 1)
            blk_write_data[i] = {1024{1'bx}} ;
    end
end
endtask // shift_write_buffer
 
endmodule
 

Line No.	Rev	Author	Line
1	15	mihad	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// File name "wb_master_behavioral.v" ////`
4			`//// ////`
5			`//// This file is part of the "PCI bridge" project ////`
6			`//// http://www.opencores.org/cores/pci/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Miha Dolenc (mihad@opencores.org) ////`
10			`//// ////`
11			`//////////////////////////////////////////////////////////////////////`
12			`//// ////`
13			`//// Copyright (C) 2000 Miha Dolenc, mihad@opencores.org ////`
14			`//// ////`
15			`//// This source file may be used and distributed without ////`
16			`//// restriction provided that this copyright statement is not ////`
17			`//// removed from the file and that any derivative work contains ////`
18			`//// the original copyright notice and the associated disclaimer. ////`
19			`//// ////`
20			`//// This source file is free software; you can redistribute it ////`
21			`//// and/or modify it under the terms of the GNU Lesser General ////`
22			`//// Public License as published by the Free Software Foundation; ////`
23			`//// either version 2.1 of the License, or (at your option) any ////`
24			`//// later version. ////`
25			`//// ////`
26			`//// This source is distributed in the hope that it will be ////`
27			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
28			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
29			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
30			`//// details. ////`
31			`//// ////`
32			`//// You should have received a copy of the GNU Lesser General ////`
33			`//// Public License along with this source; if not, download it ////`
34			`//// from http://www.opencores.org/lgpl.shtml ////`
35			`//// ////`
36			`//////////////////////////////////////////////////////////////////////`
37			`//`
38			`// CVS Revision History`
39			`//`
40			`// $Log: not supported by cvs2svn $`
41	106	mihad	`// Revision 1.2 2003/06/12 02:30:39 mihad`
42			`// Update!`
43			`//`
44	92	mihad	`// Revision 1.1 2002/02/01 13:39:43 mihad`
45			`// Initial testbench import. Still under development`
46			`//`
47	15	mihad
48			`include "pci_testbench_defines.v"
49			`module WB_MASTER_BEHAVIORAL`
50			`(`
51			`CLK_I,`
52			`RST_I,`
53			`TAG_I,`
54			`TAG_O,`
55			`ACK_I,`
56			`ADR_O,`
57			`CYC_O,`
58			`DAT_I,`
59			`DAT_O,`
60			`ERR_I,`
61			`RTY_I,`
62			`SEL_O,`
63			`STB_O,`
64			`WE_O,`
65			`CAB_O`
66			`);`
67
68			`input CLK_I;`
69			`input RST_I;`
70			input `WB_TAG_TYPE TAG_I;
71			output `WB_TAG_TYPE TAG_O;
72			`input ACK_I;`
73			output `WB_ADDR_TYPE ADR_O;
74			`output CYC_O;`
75			input `WB_DATA_TYPE DAT_I;
76			output `WB_DATA_TYPE DAT_O;
77			`input ERR_I;`
78			`input RTY_I;`
79			output `WB_SEL_TYPE SEL_O;
80			`output STB_O;`
81			`output WE_O;`
82			`output CAB_O;`
83
84			`// instantiate low level master module`
85			`WB_MASTER32 wbm_low_level`
86			`(`
87			`.CLK_I(CLK_I),`
88			`.RST_I(RST_I),`
89			`.TAG_I(TAG_I),`
90			`.TAG_O(TAG_O),`
91			`.ACK_I(ACK_I),`
92			`.ADR_O(ADR_O),`
93			`.CYC_O(CYC_O),`
94			`.DAT_I(DAT_I),`
95			`.DAT_O(DAT_O),`
96			`.ERR_I(ERR_I),`
97			`.RTY_I(RTY_I),`
98			`.SEL_O(SEL_O),`
99			`.STB_O(STB_O),`
100			`.WE_O(WE_O),`
101			`.CAB_O(CAB_O)`
102			`) ;`
103
104			`// block read and write buffers definition`
105			`// single write buffer`
106			reg `WRITE_STIM_TYPE blk_write_data [0:(`MAX_BLK_SIZE - 1)] ;
107			`// read stimulus buffer - addresses, tags, selects etc.`
108			reg `READ_STIM_TYPE blk_read_data_in [0:(`MAX_BLK_SIZE - 1)] ;
109			`// read return buffer - data and tags received while performing block reads`
110			reg `READ_RETURN_TYPE blk_read_data_out [0:(`MAX_BLK_SIZE - 1)] ;
111
112			`// single write task`
113			`task wb_single_write ;`
114			input `WRITE_STIM_TYPE write_data ;
115			input `WB_TRANSFER_FLAGS write_flags ;
116			inout `WRITE_RETURN_TYPE return ;
117			`reg in_use ;`
118			`reg cab ;`
119			`reg ok ;`
120			`integer cyc_count ;`
121			`integer rty_count ;`
122			`reg retry ;`
123	106	mihad	`reg [2:0] use_cti ;`
124			`reg [1:0] use_bte ;`
125	15	mihad	`begin:main`
126
127			return`TB_ERROR_BIT = 1'b0 ;
128			`cab = 0 ;`
129			return`CYC_ACTUAL_TRANSFER = 0 ;
130			`rty_count = 0 ;`
131
132			`// check if task was called before previous call finished`
133			`if ( in_use === 1 )`
134			`begin`
135			`$display("*E, wb_single_write routine re-entered! Time %t ", $time) ;`
136			return`TB_ERROR_BIT = 1'b1 ;
137			`disable main ;`
138			`end`
139
140			`in_use = 1 ;`
141
142			`retry = 1 ;`
143
144	106	mihad	`use_cti = {$random} % 8 ;`
145			`if (use_cti === 3'b010)`
146			`use_cti = 3'b111 ;`
147			`else if (use_cti === 3'b001)`
148			`use_cti = 3'b000 ;`
149
150			`use_bte = {$random} % 4 ;`
151
152			write_data`WRITE_TAG_STIM = {use_cti, use_bte} ;
153
154	15	mihad	`while (retry === 1)`
155			`begin`
156			`// synchronize operation to clock`
157	92	mihad	if (write_flags`WB_FAST_B2B !== 1'b1)
158			`@(posedge CLK_I) ;`
159	15	mihad
160	92	mihad	wbm_low_level.start_cycle(cab, 1'b1, write_flags`WB_FAST_B2B, ok) ;
161	15	mihad	`if ( ok !== 1 )`
162			`begin`
163			`$display("*E, Failed to initialize cycle! Routine wb_single_write, Time %t ", $time) ;`
164			return`TB_ERROR_BIT = 1'b1 ;
165			`disable main ;`
166			`end`
167
168			`// first insert initial wait states`
169			cyc_count = write_flags`INIT_WAITS ;
170			`while ( cyc_count > 0 )`
171			`begin`
172			`@(posedge CLK_I) ;`
173			`cyc_count = cyc_count - 1 ;`
174			`end`
175
176			`wbm_low_level.wbm_write(write_data, return) ;`
177
178			if ( return`CYC_ERR === 0 && return`CYC_ACK === 0 && return`CYC_RTY === 1 && write_flags`WB_TRANSFER_AUTO_RTY === 1 && return`TB_ERROR_BIT === 0)
179			`begin`
180			if ( rty_count === `WB_TB_MAX_RTY )
181			`begin`
182			`$display("*E, maximum number of retries received - access will not be repeated anymore! Routine wb_single_write, Time %t ", $time) ;`
183			`retry = 0 ;`
184			`end`
185			`else`
186			`begin`
187			`retry = 1 ;`
188			`rty_count = rty_count + 1 ;`
189			`end`
190			`end`
191			`else`
192			`retry = 0 ;`
193
194			`// if test bench error bit is set, there is no meaning in introducing subsequent wait states`
195			if ( return`TB_ERROR_BIT !== 0 )
196			`begin`
197			`@(posedge CLK_I) ;`
198			`wbm_low_level.end_cycle ;`
199			`disable main ;`
200			`end`
201
202			cyc_count = write_flags`SUBSEQ_WAITS ;
203			`while ( cyc_count > 0 )`
204			`begin`
205			`@(posedge CLK_I) ;`
206			`cyc_count = cyc_count - 1 ;`
207			`end`
208
209			`wbm_low_level.end_cycle ;`
210			`end`
211
212			`in_use = 0 ;`
213
214			`end //main`
215			`endtask // wb_single_write`
216
217			`task wb_single_read ;`
218			input `READ_STIM_TYPE read_data ;
219			input `WB_TRANSFER_FLAGS read_flags ;
220			inout `READ_RETURN_TYPE return ;
221			`reg in_use ;`
222			`reg cab ;`
223			`reg ok ;`
224			`integer cyc_count ;`
225			`integer rty_count ;`
226			`reg retry ;`
227	106	mihad	`reg [2:0] use_cti ;`
228			`reg [1:0] use_bte ;`
229	15	mihad	`begin:main`
230
231			return`TB_ERROR_BIT = 1'b0 ;
232			`cab = 0 ;`
233			`rty_count = 0 ;`
234			return`CYC_ACTUAL_TRANSFER = 0 ;
235
236			`// check if task was called before previous call finished`
237			`if ( in_use === 1 )`
238			`begin`
239			`$display("*E, wb_single_read routine re-entered! Time %t ", $time) ;`
240			return`TB_ERROR_BIT = 1'b1 ;
241			`disable main ;`
242			`end`
243
244			`in_use = 1 ;`
245
246			`retry = 1 ;`
247
248	106	mihad	`use_cti = {$random} % 8 ;`
249			`if (use_cti === 3'b010)`
250			`use_cti = 3'b111 ;`
251			`else if (use_cti === 3'b001)`
252			`use_cti = 3'b000 ;`
253
254			`use_bte = {$random} % 4 ;`
255
256			read_data`READ_TAG_STIM = {use_cti, use_bte} ;
257
258	15	mihad	`while (retry === 1)`
259			`begin`
260			`// synchronize operation to clock`
261	92	mihad	if (read_flags`WB_FAST_B2B !== 1'b1)
262			`@(posedge CLK_I) ;`
263	15	mihad
264	92	mihad	wbm_low_level.start_cycle(cab, 1'b0, read_flags`WB_FAST_B2B, ok) ;
265	15	mihad	`if ( ok !== 1 )`
266			`begin`
267			`$display("*E, Failed to initialize cycle! Routine wb_single_read, Time %t ", $time) ;`
268			return`TB_ERROR_BIT = 1'b1 ;
269			`disable main ;`
270			`end`
271
272			`// first insert initial wait states`
273			cyc_count = read_flags`INIT_WAITS ;
274			`while ( cyc_count > 0 )`
275			`begin`
276			`@(posedge CLK_I) ;`
277			`cyc_count = cyc_count - 1 ;`
278			`end`
279
280			`wbm_low_level.wbm_read(read_data, return) ;`
281
282			if ( return`CYC_ERR === 0 && return`CYC_ACK === 0 && return`CYC_RTY === 1 && read_flags`WB_TRANSFER_AUTO_RTY === 1 && return`TB_ERROR_BIT === 0)
283			`begin`
284			if ( rty_count === `WB_TB_MAX_RTY )
285			`begin`
286			`$display("*E, maximum number of retries received - access will not be repeated anymore! Routine wb_single_read, Time %t ", $time) ;`
287			`retry = 0 ;`
288			`end`
289			`else`
290			`begin`
291			`retry = 1 ;`
292			`rty_count = rty_count + 1 ;`
293			`end`
294			`end`
295			`else`
296			`begin`
297			`retry = 0 ;`
298			`end`
299
300			`// if test bench error bit is set, there is no meaning in introducing subsequent wait states`
301			if ( return`TB_ERROR_BIT !== 0 )
302			`begin`
303			`@(posedge CLK_I) ;`
304			`wbm_low_level.end_cycle ;`
305			`disable main ;`
306			`end`
307
308			cyc_count = read_flags`SUBSEQ_WAITS ;
309			`while ( cyc_count > 0 )`
310			`begin`
311			`@(posedge CLK_I) ;`
312			`cyc_count = cyc_count - 1 ;`
313			`end`
314
315			`wbm_low_level.end_cycle ;`
316			`end`
317
318			`in_use = 0 ;`
319
320			`end //main`
321			`endtask // wb_single_read`
322
323			`task wb_RMW_read ;`
324			input `READ_STIM_TYPE read_data ;
325			input `WB_TRANSFER_FLAGS read_flags ;
326			inout `READ_RETURN_TYPE return ;
327			`reg in_use ;`
328			`reg cab ;`
329			`reg ok ;`
330			`integer cyc_count ;`
331			`integer rty_count ;`
332			`reg retry ;`
333	106	mihad	`reg [2:0] use_cti ;`
334			`reg [1:0] use_bte ;`
335	15	mihad	`begin:main`
336
337			return`TB_ERROR_BIT = 1'b0 ;
338			`cab = 0 ;`
339			`rty_count = 0 ;`
340			return`CYC_ACTUAL_TRANSFER = 0 ;
341
342			`// check if task was called before previous call finished`
343			`if ( in_use === 1 )`
344			`begin`
345			`$display("*E, wb_RMW_read routine re-entered! Time %t ", $time) ;`
346			return`TB_ERROR_BIT = 1'b1 ;
347			`disable main ;`
348			`end`
349
350			`in_use = 1 ;`
351
352			`retry = 1 ;`
353
354	106	mihad	`use_cti = {$random} % 8 ;`
355			`if (use_cti === 3'b010)`
356			`use_cti = 3'b111 ;`
357			`else if (use_cti === 3'b001)`
358			`use_cti = 3'b000 ;`
359
360			`use_bte = {$random} % 4 ;`
361
362			read_data`READ_TAG_STIM = {use_cti, use_bte} ;
363
364	15	mihad	`while (retry === 1)`
365			`begin`
366			`// synchronize operation to clock`
367	92	mihad	if (read_flags`WB_FAST_B2B !== 1'b1)
368			`@(posedge CLK_I) ;`
369	15	mihad
370	92	mihad	wbm_low_level.start_cycle(cab, 1'b0, read_flags`WB_FAST_B2B, ok) ;
371	15	mihad	`if ( ok !== 1 )`
372			`begin`
373			`$display("*E, Failed to initialize cycle! Routine wb_RMW_read, Time %t ", $time) ;`
374			return`TB_ERROR_BIT = 1'b1 ;
375			`disable main ;`
376			`end`
377
378			`// first insert initial wait states`
379			cyc_count = read_flags`INIT_WAITS ;
380			`while ( cyc_count > 0 )`
381			`begin`
382			`@(posedge CLK_I) ;`
383			`cyc_count = cyc_count - 1 ;`
384			`end`
385
386			`wbm_low_level.wbm_read(read_data, return) ;`
387
388			if ( return`CYC_ERR === 0 && return`CYC_ACK === 0 && return`CYC_RTY === 1 && read_flags`WB_TRANSFER_AUTO_RTY === 1 && return`TB_ERROR_BIT === 0)
389			`begin`
390			if ( rty_count === `WB_TB_MAX_RTY )
391			`begin`
392			`$display("*E, maximum number of retries received - access will not be repeated anymore! Routine wb_RMW_read, Time %t ", $time) ;`
393			`retry = 0 ;`
394			`end`
395			`else`
396			`begin`
397			`retry = 1 ;`
398			`rty_count = rty_count + 1 ;`
399			`end`
400			`end`
401			`else`
402			`begin`
403			`retry = 0 ;`
404			`end`
405
406			`// if test bench error bit is set, there is no meaning in introducing subsequent wait states`
407			if ( return`TB_ERROR_BIT !== 0 )
408			`begin`
409			`@(posedge CLK_I) ;`
410			`wbm_low_level.end_cycle ;`
411			`disable main ;`
412			`end`
413
414			cyc_count = read_flags`SUBSEQ_WAITS ;
415			`while ( cyc_count > 0 )`
416			`begin`
417			`@(posedge CLK_I) ;`
418			`cyc_count = cyc_count - 1 ;`
419			`end`
420
421			`if (retry === 1)`
422			`wbm_low_level.end_cycle ;`
423			`else`
424			`wbm_low_level.modify_cycle ;`
425			`end`
426
427			`in_use = 0 ;`
428
429			`end //main`
430			`endtask // wb_RMW_read`
431
432			`task wb_RMW_write ;`
433			input `WRITE_STIM_TYPE write_data ;
434			input `WB_TRANSFER_FLAGS write_flags ;
435			inout `WRITE_RETURN_TYPE return ;
436			`reg in_use ;`
437			`reg cab ;`
438			`reg ok ;`
439			`integer cyc_count ;`
440			`integer rty_count ;`
441			`reg retry ;`
442	106	mihad	`reg [2:0] use_cti ;`
443			`reg [1:0] use_bte ;`
444	15	mihad	`begin:main`
445
446			return`TB_ERROR_BIT = 1'b0 ;
447			`cab = 0 ;`
448			return`CYC_ACTUAL_TRANSFER = 0 ;
449			`rty_count = 0 ;`
450
451			`// check if task was called before previous call finished`
452			`if ( in_use === 1 )`
453			`begin`
454			`$display("*E, wb_RMW_write routine re-entered! Time %t ", $time) ;`
455			return`TB_ERROR_BIT = 1'b1 ;
456			`disable main ;`
457			`end`
458
459			`in_use = 1 ;`
460
461			`retry = 1 ;`
462
463	106	mihad	`use_cti = {$random} % 8 ;`
464			`if (use_cti === 3'b010)`
465			`use_cti = 3'b111 ;`
466			`else if (use_cti === 3'b001)`
467			`use_cti = 3'b000 ;`
468
469			`use_bte = {$random} % 4 ;`
470
471			write_data`WRITE_TAG_STIM = {use_cti, use_bte} ;
472
473	15	mihad	`while (retry === 1)`
474			`begin`
475			`// synchronize operation to clock`
476	92	mihad	if (write_flags`WB_FAST_B2B !== 1'b1)
477			`@(posedge CLK_I) ;`
478
479	15	mihad	`ok = 1 ;`
480			`if (rty_count !== 0)`
481	92	mihad	wbm_low_level.start_cycle(cab, 1'b1, write_flags`WB_FAST_B2B, ok) ;
482	15	mihad
483			`if ( ok !== 1 )`
484			`begin`
485			`$display("*E, Failed to initialize cycle! Routine wb_single_write, Time %t ", $time) ;`
486			return`TB_ERROR_BIT = 1'b1 ;
487			`disable main ;`
488			`end`
489
490			`// first insert initial wait states`
491			cyc_count = write_flags`INIT_WAITS ;
492			`while ( cyc_count > 0 )`
493			`begin`
494			`@(posedge CLK_I) ;`
495			`cyc_count = cyc_count - 1 ;`
496			`end`
497
498			`wbm_low_level.wbm_write(write_data, return) ;`
499
500			if ( return`CYC_ERR === 0 && return`CYC_ACK === 0 && return`CYC_RTY === 1 && write_flags`WB_TRANSFER_AUTO_RTY === 1 && return`TB_ERROR_BIT === 0)

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[/] [pci/] [tags/] [rel_7/] [bench/] [verilog/] [wb_master_behavioral.v] - Blame information for rev 106