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[/] [pci/] [tags/] [rel_7/] [bench/] [verilog/] [wb_slave_behavioral.v] - Blame information for rev 15

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  File name: wb_slave_behavioral.v                            ////
////                                                              ////
////  This file is part of the "PCI bridge" project               ////
////  http://www.opencores.org/cores/pci/                         ////
////                                                              ////
////  Author(s):                                                  ////
////      - Tadej Markovic, tadej@opencores.org                   ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Tadej Markovic, tadej@opencores.org       ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
`include "pci_testbench_defines.v"
`include "timescale.v"
module WB_SLAVE_BEHAVIORAL
(
        CLK_I,
        RST_I,
        ACK_O,
        ADR_I,
        CYC_I,
        DAT_O,
        DAT_I,
        ERR_O,
        RTY_O,
        SEL_I,
        STB_I,
        WE_I,
        CAB_I
);
 
/*----------------------------------------------------------------------------------------------------------------------
WISHBONE signals
----------------------------------------------------------------------------------------------------------------------*/
input                                   CLK_I ;
input                                   RST_I ;
output                                  ACK_O ;
input   `WB_ADDR_TYPE   ADR_I ;
input                                   CYC_I ;
output  `WB_DATA_TYPE   DAT_O ;
input   `WB_DATA_TYPE   DAT_I ;
output                                  ERR_O ;
output                                  RTY_O ;
input   `WB_SEL_TYPE    SEL_I ;
input                                   STB_I ;
input                                   WE_I ;
input                                   CAB_I ;
 
//reg                           ACK_O ;
//reg                           ERR_O ;
//reg                           RTY_O ;
reg             [31:0]   DAT_O ;
 
/*----------------------------------------------------------------------------------------------------------------------
Asynchronous dual-port RAM signals for storing and fetching the data
----------------------------------------------------------------------------------------------------------------------*/
reg     [31:0]   wb_memory [0:1023] ; // data for WB memory - 16 LSB addresses are connected
reg             [31:0]   mem_wr_data_out ;
reg             [31:0]   mem_rd_data_in ;
 
/*----------------------------------------------------------------------------------------------------------------------
Maximum values for WAIT and RETRY counters and which response !!!
----------------------------------------------------------------------------------------------------------------------*/
reg             [2:0]    a_e_r_resp ;            // tells with which cycle_termination_signal must wb_slave respond !
reg                             wait_cyc ;
reg             [7:0]    max_retry ;
 
// assign registers to default state while in reset
always@(RST_I)
begin
    if (RST_I)
    begin
        a_e_r_resp      <= 3'b000 ; // do not respond
        wait_cyc        <= 1'b0 ;       // no wait cycles
        max_retry       <= 8'h0 ;       // no retries
    end
end //reset
 
task cycle_response ;
        input [2:0]              ack_err_rty_resp ;      // acknowledge, error or retry response input flags
        input                   wait_cycles ;           // if wait cycles before each data termination cycle (ack, err or rty)
        input [7:0]              retry_cycles ;          // noumber of retry cycles before acknowledge cycle
begin
    // assign values
    a_e_r_resp  <= #1 ack_err_rty_resp ;
        wait_cyc        <= #1 wait_cycles ;
    max_retry   <= #1 retry_cycles ;
end
endtask // cycle_response
 
/*----------------------------------------------------------------------------------------------------------------------
Internal signals and logic
----------------------------------------------------------------------------------------------------------------------*/
reg                             calc_ack ;
reg                             calc_err ;
reg                             calc_rty ;
 
reg             [7:0]    retry_cnt ;
reg             [7:0]    retry_num ;
reg                             retry_expired ;
reg                             retry_rst ;
 
// RESET retry counter
always@(posedge RST_I or posedge CLK_I)
begin
        if (RST_I)
                retry_rst <= 1'b1 ;
        else
                retry_rst <= calc_ack || calc_err ;
end
 
// Retry counter
always@(posedge retry_rst or negedge calc_rty)
begin
        if (retry_rst)
                retry_cnt <= #`FF_DELAY 8'h00 ;
        else
                retry_cnt <= #`FF_DELAY retry_num ;
end
always@(retry_cnt or max_retry)
begin
        if (retry_cnt < max_retry)
        begin
                retry_num = retry_cnt + 1'b1 ;
                retry_expired = #10 1'b0 ;
        end
        else
        begin
                retry_num = retry_cnt ;
                retry_expired = #10 1'b1 ;
        end
end
 
reg             [1:0]    wait_cnt ;
reg             [1:0]    wait_num ;
reg                             wait_expired ;
reg                             reset_wait ;
 
always@(posedge RST_I or posedge CLK_I)
begin
        if (RST_I)
                reset_wait <= #`FF_DELAY 1'b1 ;
        else
                reset_wait <= #`FF_DELAY (wait_expired || ~STB_I) ;
end
 
// Wait counter
always@(posedge reset_wait or posedge CLK_I)
begin
        if (reset_wait)
                wait_cnt <= #`FF_DELAY 4'h0 ;
        else
                wait_cnt <= #`FF_DELAY wait_num ;
end
always@(wait_cnt or wait_cyc or STB_I or a_e_r_resp or retry_expired)
begin
        if ((wait_cyc) && (STB_I))
        begin
                if (wait_cnt < 2'h2)
                begin
                        wait_num = wait_cnt + 1'b1 ;
                        wait_expired = 1'b0 ;
                        calc_ack = 1'b0 ;
                        calc_err = 1'b0 ;
                        calc_rty = 1'b0 ;
                end
                else
                begin
                        wait_num = wait_cnt ;
                        wait_expired = 1'b1 ;
                        if (a_e_r_resp == 3'b100)
                        begin
                                calc_ack = 1'b1 ;
                                calc_err = 1'b0 ;
                                calc_rty = 1'b0 ;
                        end
                        else
                        if (a_e_r_resp == 3'b010)
                        begin
                                calc_ack = 1'b0 ;
                                calc_err = 1'b1 ;
                                calc_rty = 1'b0 ;
                        end
                        else
                        if (a_e_r_resp == 3'b001)
                        begin
                                calc_err = 1'b0 ;
                                if (retry_expired)
                                begin
                                        calc_ack = 1'b1 ;
                                        calc_rty = 1'b0 ;
                                end
                                else
                                begin
                                        calc_ack = 1'b0 ;
                                        calc_rty = 1'b1 ;
                                end
                        end
                        else
                        begin
                                calc_ack = 1'b0 ;
                                calc_err = 1'b0 ;
                                calc_rty = 1'b0 ;
                        end
                end
        end
        else
        if ((~wait_cyc) && (STB_I))
        begin
                wait_num = 2'h0 ;
                wait_expired = 1'b1 ;
                if (a_e_r_resp == 3'b100)
                begin
                        calc_ack = 1'b1 ;
                        calc_err = 1'b0 ;
                        calc_rty = 1'b0 ;
                end
                else
                if (a_e_r_resp == 3'b010)
                begin
                        calc_ack = 1'b0 ;
                        calc_err = 1'b1 ;
                        calc_rty = 1'b0 ;
                end
                else
                if (a_e_r_resp == 3'b001)
                begin
                        calc_err = 1'b0 ;
                        if (retry_expired)
                        begin
                                calc_ack = 1'b1 ;
                                calc_rty = 1'b0 ;
                        end
                        else
                        begin
                                calc_ack = 1'b0 ;
                                calc_rty = 1'b1 ;
                        end
                end
                else
                begin
                        calc_ack = 1'b0 ;
                        calc_err = 1'b0 ;
                        calc_rty = 1'b0 ;
                end
        end
        else
        begin
                wait_num = 2'h0 ;
                wait_expired = 1'b0 ;
                calc_ack = 1'b0 ;
                calc_err = 1'b0 ;
                calc_rty = 1'b0 ;
        end
end
 
wire    rd_sel = (CYC_I && STB_I && ~WE_I) ;
wire    wr_sel = (CYC_I && STB_I && WE_I) ;
 
// Generate cycle termination signals
assign  ACK_O = calc_ack && STB_I ;
assign  ERR_O = calc_err && STB_I ;
assign  RTY_O = calc_rty && STB_I ;
 
// Assign address to asynchronous memory
always@(ADR_I or RST_I)
begin
        if (RST_I) // this is added because at start of test bench we need address change in order to get data!
                mem_rd_data_in = 32'hxxxx_xxxx ;
        else
                mem_rd_data_in = wb_memory[ADR_I[11:2]] ;
end
 
// assign outputs to unknown state while in reset
always@(RST_I)
begin
    if (RST_I)
    begin
                DAT_O <= 32'hxxxx_xxxx ;
    end
end //reset
 
// Data input/output interface
always@(rd_sel or wr_sel or mem_rd_data_in or DAT_I or SEL_I or mem_wr_data_out)
begin
        if (rd_sel)
        begin
                DAT_O = mem_rd_data_in ;
        end
end
always@(posedge CLK_I)
begin
    if (wr_sel)
    begin
        mem_wr_data_out         = wb_memory[ADR_I[11:2]] ;
 
        if ( SEL_I[3] )
            mem_wr_data_out[31:24] = DAT_I[31:24] ;
 
        if ( SEL_I[2] )
            mem_wr_data_out[23:16] = DAT_I[23:16] ;
 
        if ( SEL_I[1] )
            mem_wr_data_out[15: 8] = DAT_I[15: 8] ;
 
        if ( SEL_I[0] )
            mem_wr_data_out[ 7: 0] = DAT_I[ 7: 0] ;
 
        wb_memory[ADR_I[11:2]] <= mem_wr_data_out ;
    end
end
 
endmodule

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[/] [pci/] [tags/] [rel_7/] [bench/] [verilog/] [wb_slave_behavioral.v] - Blame information for rev 15

Line No.	Rev	Author	Line
1	15	mihad	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// File name: wb_slave_behavioral.v ////`
4			`//// ////`
5			`//// This file is part of the "PCI bridge" project ////`
6			`//// http://www.opencores.org/cores/pci/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Tadej Markovic, tadej@opencores.org ////`
10			`//// ////`
11			`//// All additional information is avaliable in the README.txt ////`
12			`//// file. ////`
13			`//// ////`
14			`//// ////`
15			`//////////////////////////////////////////////////////////////////////`
16			`//// ////`
17			`//// Copyright (C) 2000 Tadej Markovic, tadej@opencores.org ////`
18			`//// ////`
19			`//// This source file may be used and distributed without ////`
20			`//// restriction provided that this copyright statement is not ////`
21			`//// removed from the file and that any derivative work contains ////`
22			`//// the original copyright notice and the associated disclaimer. ////`
23			`//// ////`
24			`//// This source file is free software; you can redistribute it ////`
25			`//// and/or modify it under the terms of the GNU Lesser General ////`
26			`//// Public License as published by the Free Software Foundation; ////`
27			`//// either version 2.1 of the License, or (at your option) any ////`
28			`//// later version. ////`
29			`//// ////`
30			`//// This source is distributed in the hope that it will be ////`
31			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
32			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
33			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
34			`//// details. ////`
35			`//// ////`
36			`//// You should have received a copy of the GNU Lesser General ////`
37			`//// Public License along with this source; if not, download it ////`
38			`//// from http://www.opencores.org/lgpl.shtml ////`
39			`//// ////`
40			`//////////////////////////////////////////////////////////////////////`
41			`//`
42			`// CVS Revision History`
43			`//`
44			`// $Log: not supported by cvs2svn $`
45			`//`
46
47			`include "pci_testbench_defines.v"
48			`include "timescale.v"
49			`module WB_SLAVE_BEHAVIORAL`
50			`(`
51			`CLK_I,`
52			`RST_I,`
53			`ACK_O,`
54			`ADR_I,`
55			`CYC_I,`
56			`DAT_O,`
57			`DAT_I,`
58			`ERR_O,`
59			`RTY_O,`
60			`SEL_I,`
61			`STB_I,`
62			`WE_I,`
63			`CAB_I`
64			`);`
65
66			`/*----------------------------------------------------------------------------------------------------------------------`
67			`WISHBONE signals`
68			`----------------------------------------------------------------------------------------------------------------------*/`
69			`input CLK_I ;`
70			`input RST_I ;`
71			`output ACK_O ;`
72			input `WB_ADDR_TYPE ADR_I ;
73			`input CYC_I ;`
74			output `WB_DATA_TYPE DAT_O ;
75			input `WB_DATA_TYPE DAT_I ;
76			`output ERR_O ;`
77			`output RTY_O ;`
78			input `WB_SEL_TYPE SEL_I ;
79			`input STB_I ;`
80			`input WE_I ;`
81			`input CAB_I ;`
82
83			`//reg ACK_O ;`
84			`//reg ERR_O ;`
85			`//reg RTY_O ;`
86			`reg [31:0] DAT_O ;`
87
88			`/*----------------------------------------------------------------------------------------------------------------------`
89			`Asynchronous dual-port RAM signals for storing and fetching the data`
90			`----------------------------------------------------------------------------------------------------------------------*/`
91			`reg [31:0] wb_memory [0:1023] ; // data for WB memory - 16 LSB addresses are connected`
92			`reg [31:0] mem_wr_data_out ;`
93			`reg [31:0] mem_rd_data_in ;`
94
95			`/*----------------------------------------------------------------------------------------------------------------------`
96			`Maximum values for WAIT and RETRY counters and which response !!!`
97			`----------------------------------------------------------------------------------------------------------------------*/`
98			`reg [2:0] a_e_r_resp ; // tells with which cycle_termination_signal must wb_slave respond !`
99			`reg wait_cyc ;`
100			`reg [7:0] max_retry ;`
101
102			`// assign registers to default state while in reset`
103			`always@(RST_I)`
104			`begin`
105			`if (RST_I)`
106			`begin`
107			`a_e_r_resp <= 3'b000 ; // do not respond`
108			`wait_cyc <= 1'b0 ; // no wait cycles`
109			`max_retry <= 8'h0 ; // no retries`
110			`end`
111			`end //reset`
112
113			`task cycle_response ;`
114			`input [2:0] ack_err_rty_resp ; // acknowledge, error or retry response input flags`
115			`input wait_cycles ; // if wait cycles before each data termination cycle (ack, err or rty)`
116			`input [7:0] retry_cycles ; // noumber of retry cycles before acknowledge cycle`
117			`begin`
118			`// assign values`
119			`a_e_r_resp <= #1 ack_err_rty_resp ;`
120			`wait_cyc <= #1 wait_cycles ;`
121			`max_retry <= #1 retry_cycles ;`
122			`end`
123			`endtask // cycle_response`
124
125			`/*----------------------------------------------------------------------------------------------------------------------`
126			`Internal signals and logic`
127			`----------------------------------------------------------------------------------------------------------------------*/`
128			`reg calc_ack ;`
129			`reg calc_err ;`
130			`reg calc_rty ;`
131
132			`reg [7:0] retry_cnt ;`
133			`reg [7:0] retry_num ;`
134			`reg retry_expired ;`
135			`reg retry_rst ;`
136
137			`// RESET retry counter`
138			`always@(posedge RST_I or posedge CLK_I)`
139			`begin`
140			`if (RST_I)`
141			`retry_rst <= 1'b1 ;`
142			`else`
143			`retry_rst <= calc_ack \|\| calc_err ;`
144			`end`
145
146			`// Retry counter`
147			`always@(posedge retry_rst or negedge calc_rty)`
148			`begin`
149			`if (retry_rst)`
150			retry_cnt <= #`FF_DELAY 8'h00 ;
151			`else`
152			retry_cnt <= #`FF_DELAY retry_num ;
153			`end`
154			`always@(retry_cnt or max_retry)`
155			`begin`
156			`if (retry_cnt < max_retry)`
157			`begin`
158			`retry_num = retry_cnt + 1'b1 ;`
159			`retry_expired = #10 1'b0 ;`
160			`end`
161			`else`
162			`begin`
163			`retry_num = retry_cnt ;`
164			`retry_expired = #10 1'b1 ;`
165			`end`
166			`end`
167
168			`reg [1:0] wait_cnt ;`
169			`reg [1:0] wait_num ;`
170			`reg wait_expired ;`
171			`reg reset_wait ;`
172
173			`always@(posedge RST_I or posedge CLK_I)`
174			`begin`
175			`if (RST_I)`
176			reset_wait <= #`FF_DELAY 1'b1 ;
177			`else`
178			reset_wait <= #`FF_DELAY (wait_expired \|\| ~STB_I) ;
179			`end`
180
181			`// Wait counter`
182			`always@(posedge reset_wait or posedge CLK_I)`
183			`begin`
184			`if (reset_wait)`
185			wait_cnt <= #`FF_DELAY 4'h0 ;
186			`else`
187			wait_cnt <= #`FF_DELAY wait_num ;
188			`end`
189			`always@(wait_cnt or wait_cyc or STB_I or a_e_r_resp or retry_expired)`
190			`begin`
191			`if ((wait_cyc) && (STB_I))`
192			`begin`
193			`if (wait_cnt < 2'h2)`
194			`begin`
195			`wait_num = wait_cnt + 1'b1 ;`
196			`wait_expired = 1'b0 ;`
197			`calc_ack = 1'b0 ;`
198			`calc_err = 1'b0 ;`
199			`calc_rty = 1'b0 ;`
200			`end`
201			`else`
202			`begin`
203			`wait_num = wait_cnt ;`
204			`wait_expired = 1'b1 ;`
205			`if (a_e_r_resp == 3'b100)`
206			`begin`
207			`calc_ack = 1'b1 ;`
208			`calc_err = 1'b0 ;`
209			`calc_rty = 1'b0 ;`
210			`end`
211			`else`
212			`if (a_e_r_resp == 3'b010)`
213			`begin`
214			`calc_ack = 1'b0 ;`
215			`calc_err = 1'b1 ;`
216			`calc_rty = 1'b0 ;`
217			`end`
218			`else`
219			`if (a_e_r_resp == 3'b001)`
220			`begin`
221			`calc_err = 1'b0 ;`
222			`if (retry_expired)`
223			`begin`
224			`calc_ack = 1'b1 ;`
225			`calc_rty = 1'b0 ;`
226			`end`
227			`else`
228			`begin`
229			`calc_ack = 1'b0 ;`
230			`calc_rty = 1'b1 ;`
231			`end`
232			`end`
233			`else`
234			`begin`
235			`calc_ack = 1'b0 ;`
236			`calc_err = 1'b0 ;`
237			`calc_rty = 1'b0 ;`
238			`end`
239			`end`
240			`end`
241			`else`
242			`if ((~wait_cyc) && (STB_I))`
243			`begin`
244			`wait_num = 2'h0 ;`
245			`wait_expired = 1'b1 ;`
246			`if (a_e_r_resp == 3'b100)`
247			`begin`
248			`calc_ack = 1'b1 ;`
249			`calc_err = 1'b0 ;`
250			`calc_rty = 1'b0 ;`
251			`end`
252			`else`
253			`if (a_e_r_resp == 3'b010)`
254			`begin`
255			`calc_ack = 1'b0 ;`
256			`calc_err = 1'b1 ;`
257			`calc_rty = 1'b0 ;`
258			`end`
259			`else`
260			`if (a_e_r_resp == 3'b001)`
261			`begin`
262			`calc_err = 1'b0 ;`
263			`if (retry_expired)`
264			`begin`
265			`calc_ack = 1'b1 ;`
266			`calc_rty = 1'b0 ;`
267			`end`
268			`else`
269			`begin`
270			`calc_ack = 1'b0 ;`
271			`calc_rty = 1'b1 ;`
272			`end`
273			`end`
274			`else`
275			`begin`
276			`calc_ack = 1'b0 ;`
277			`calc_err = 1'b0 ;`
278			`calc_rty = 1'b0 ;`
279			`end`
280			`end`
281			`else`
282			`begin`
283			`wait_num = 2'h0 ;`
284			`wait_expired = 1'b0 ;`
285			`calc_ack = 1'b0 ;`
286			`calc_err = 1'b0 ;`
287			`calc_rty = 1'b0 ;`
288			`end`
289			`end`
290
291			`wire rd_sel = (CYC_I && STB_I && ~WE_I) ;`
292			`wire wr_sel = (CYC_I && STB_I && WE_I) ;`
293
294			`// Generate cycle termination signals`
295			`assign ACK_O = calc_ack && STB_I ;`
296			`assign ERR_O = calc_err && STB_I ;`
297			`assign RTY_O = calc_rty && STB_I ;`
298
299			`// Assign address to asynchronous memory`
300			`always@(ADR_I or RST_I)`
301			`begin`
302			`if (RST_I) // this is added because at start of test bench we need address change in order to get data!`
303			`mem_rd_data_in = 32'hxxxx_xxxx ;`
304			`else`
305			`mem_rd_data_in = wb_memory[ADR_I[11:2]] ;`
306			`end`
307
308			`// assign outputs to unknown state while in reset`
309			`always@(RST_I)`
310			`begin`
311			`if (RST_I)`
312			`begin`
313			`DAT_O <= 32'hxxxx_xxxx ;`
314			`end`
315			`end //reset`
316
317			`// Data input/output interface`
318			`always@(rd_sel or wr_sel or mem_rd_data_in or DAT_I or SEL_I or mem_wr_data_out)`
319			`begin`
320			`if (rd_sel)`
321			`begin`
322			`DAT_O = mem_rd_data_in ;`
323			`end`
324			`end`
325			`always@(posedge CLK_I)`
326			`begin`
327			`if (wr_sel)`
328			`begin`
329			`mem_wr_data_out = wb_memory[ADR_I[11:2]] ;`
330
331			`if ( SEL_I[3] )`
332			`mem_wr_data_out[31:24] = DAT_I[31:24] ;`
333
334			`if ( SEL_I[2] )`
335			`mem_wr_data_out[23:16] = DAT_I[23:16] ;`
336
337			`if ( SEL_I[1] )`
338			`mem_wr_data_out[15: 8] = DAT_I[15: 8] ;`
339
340			`if ( SEL_I[0] )`
341			`mem_wr_data_out[ 7: 0] = DAT_I[ 7: 0] ;`
342
343			`wb_memory[ADR_I[11:2]] <= mem_wr_data_out ;`
344			`end`
345			`end`
346
347			`endmodule`