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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  File name: wb_slave_behavioral.v                            ////
////                                                              ////
////  This file is part of the "PCI bridge" project               ////
////  http://www.opencores.org/cores/pci/                         ////
////                                                              ////
////  Author(s):                                                  ////
////      - Tadej Markovic, tadej@opencores.org                   ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Tadej Markovic, tadej@opencores.org       ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2002/02/01 13:39:43  mihad
// Initial testbench import. Still under development
//
//
 
`include "pci_testbench_defines.v"
`include "timescale.v"
`include "pci_constants.v"
module WB_SLAVE_BEHAVIORAL
(
        CLK_I,
        RST_I,
        ACK_O,
        ADR_I,
        CYC_I,
        DAT_O,
        DAT_I,
        ERR_O,
        RTY_O,
        SEL_I,
        STB_I,
        WE_I,
        CAB_I
);
 
/*----------------------------------------------------------------------------------------------------------------------
WISHBONE signals
----------------------------------------------------------------------------------------------------------------------*/
input                                   CLK_I ;
input                                   RST_I ;
output                                  ACK_O ;
input   `WB_ADDR_TYPE   ADR_I ;
input                                   CYC_I ;
output  `WB_DATA_TYPE   DAT_O ;
input   `WB_DATA_TYPE   DAT_I ;
output                                  ERR_O ;
output                                  RTY_O ;
input   `WB_SEL_TYPE    SEL_I ;
input                                   STB_I ;
input                                   WE_I ;
input                                   CAB_I ;
 
//reg                           ACK_O ;
//reg                           ERR_O ;
//reg                           RTY_O ;
reg             [31:0]   DAT_O ;
 
/*----------------------------------------------------------------------------------------------------------------------
Asynchronous dual-port RAM signals for storing and fetching the data
----------------------------------------------------------------------------------------------------------------------*/
reg     [31:0]   wb_memory [0:1023] ; // data for WB memory - 16 LSB addresses are connected
reg             [31:0]   mem_wr_data_out ;
reg             [31:0]   mem_rd_data_in ;
 
/*----------------------------------------------------------------------------------------------------------------------
Maximum values for WAIT and RETRY counters and which response !!!
----------------------------------------------------------------------------------------------------------------------*/
reg             [2:0]    a_e_r_resp ;            // tells with which cycle_termination_signal must wb_slave respond !
reg                             wait_cyc ;
reg             [7:0]    max_retry ;
 
// assign registers to default state while in reset
always@(RST_I)
begin
    if (RST_I)
    begin
        a_e_r_resp      <= 3'b000 ; // do not respond
        wait_cyc        <= 1'b0 ;       // no wait cycles
        max_retry       <= 8'h0 ;       // no retries
    end
end //reset
 
task cycle_response ;
        input [2:0]              ack_err_rty_resp ;      // acknowledge, error or retry response input flags
        input                   wait_cycles ;           // if wait cycles before each data termination cycle (ack, err or rty)
        input [7:0]              retry_cycles ;          // noumber of retry cycles before acknowledge cycle
begin
    // assign values
    a_e_r_resp  <= #1 ack_err_rty_resp ;
        wait_cyc        <= #1 wait_cycles ;
    max_retry   <= #1 retry_cycles ;
end
endtask // cycle_response
 
/*----------------------------------------------------------------------------------------------------------------------
Internal signals and logic
----------------------------------------------------------------------------------------------------------------------*/
reg                             calc_ack ;
reg                             calc_err ;
reg                             calc_rty ;
 
reg             [7:0]    retry_cnt ;
reg             [7:0]    retry_num ;
reg                             retry_expired ;
reg                             retry_rst ;
 
// RESET retry counter
always@(posedge RST_I or posedge CLK_I)
begin
        if (RST_I)
                retry_rst <= 1'b1 ;
        else
                retry_rst <= calc_ack || calc_err ;
end
 
// Retry counter
always@(posedge retry_rst or negedge calc_rty)
begin
        if (retry_rst)
                retry_cnt <= #`FF_DELAY 8'h00 ;
        else
                retry_cnt <= #`FF_DELAY retry_num ;
end
always@(retry_cnt or max_retry)
begin
        if (retry_cnt < max_retry)
        begin
                retry_num = retry_cnt + 1'b1 ;
                retry_expired = #10 1'b0 ;
        end
        else
        begin
                retry_num = retry_cnt ;
                retry_expired = #10 1'b1 ;
        end
end
 
reg             [1:0]    wait_cnt ;
reg             [1:0]    wait_num ;
reg                             wait_expired ;
reg                             reset_wait ;
 
always@(posedge RST_I or posedge CLK_I)
begin
        if (RST_I)
                reset_wait <= #`FF_DELAY 1'b1 ;
        else
                reset_wait <= #`FF_DELAY (wait_expired || ~STB_I) ;
end
 
// Wait counter
always@(posedge reset_wait or posedge CLK_I)
begin
        if (reset_wait)
                wait_cnt <= #`FF_DELAY 4'h0 ;
        else
                wait_cnt <= #`FF_DELAY wait_num ;
end
always@(wait_cnt or wait_cyc or STB_I or a_e_r_resp or retry_expired)
begin
        if ((wait_cyc) && (STB_I))
        begin
                if (wait_cnt < 2'h2)
                begin
                        wait_num = wait_cnt + 1'b1 ;
                        wait_expired = 1'b0 ;
                        calc_ack = 1'b0 ;
                        calc_err = 1'b0 ;
                        calc_rty = 1'b0 ;
                end
                else
                begin
                        wait_num = wait_cnt ;
                        wait_expired = 1'b1 ;
                        if (a_e_r_resp == 3'b100)
                        begin
                                calc_ack = 1'b1 ;
                                calc_err = 1'b0 ;
                                calc_rty = 1'b0 ;
                        end
                        else
                        if (a_e_r_resp == 3'b010)
                        begin
                                calc_ack = 1'b0 ;
                                calc_err = 1'b1 ;
                                calc_rty = 1'b0 ;
                        end
                        else
                        if (a_e_r_resp == 3'b001)
                        begin
                                calc_err = 1'b0 ;
                                if (retry_expired)
                                begin
                                        calc_ack = 1'b1 ;
                                        calc_rty = 1'b0 ;
                                end
                                else
                                begin
                                        calc_ack = 1'b0 ;
                                        calc_rty = 1'b1 ;
                                end
                        end
                        else
                        begin
                                calc_ack = 1'b0 ;
                                calc_err = 1'b0 ;
                                calc_rty = 1'b0 ;
                        end
                end
        end
        else
        if ((~wait_cyc) && (STB_I))
        begin
                wait_num = 2'h0 ;
                wait_expired = 1'b1 ;
                if (a_e_r_resp == 3'b100)
                begin
                        calc_ack = 1'b1 ;
                        calc_err = 1'b0 ;
                        calc_rty = 1'b0 ;
                end
                else
                if (a_e_r_resp == 3'b010)
                begin
                        calc_ack = 1'b0 ;
                        calc_err = 1'b1 ;
                        calc_rty = 1'b0 ;
                end
                else
                if (a_e_r_resp == 3'b001)
                begin
                        calc_err = 1'b0 ;
                        if (retry_expired)
                        begin
                                calc_ack = 1'b1 ;
                                calc_rty = 1'b0 ;
                        end
                        else
                        begin
                                calc_ack = 1'b0 ;
                                calc_rty = 1'b1 ;
                        end
                end
                else
                begin
                        calc_ack = 1'b0 ;
                        calc_err = 1'b0 ;
                        calc_rty = 1'b0 ;
                end
        end
        else
        begin
                wait_num = 2'h0 ;
                wait_expired = 1'b0 ;
                calc_ack = 1'b0 ;
                calc_err = 1'b0 ;
                calc_rty = 1'b0 ;
        end
end
 
wire    rd_sel = (CYC_I && STB_I && ~WE_I) ;
wire    wr_sel = (CYC_I && STB_I && WE_I) ;
 
// Generate cycle termination signals
assign  ACK_O = calc_ack && STB_I ;
assign  ERR_O = calc_err && STB_I ;
assign  RTY_O = calc_rty && STB_I ;
 
// Assign address to asynchronous memory
always@(ADR_I or RST_I)
begin
        if (RST_I) // this is added because at start of test bench we need address change in order to get data!
                mem_rd_data_in = 32'hxxxx_xxxx ;
        else
                mem_rd_data_in = wb_memory[ADR_I[11:2]] ;
end
 
// assign outputs to unknown state while in reset
always@(RST_I)
begin
    if (RST_I)
    begin
                DAT_O <= 32'hxxxx_xxxx ;
    end
end //reset
 
// Data input/output interface
always@(rd_sel or wr_sel or mem_rd_data_in or DAT_I or SEL_I or mem_wr_data_out)
begin
        if (rd_sel)
        begin
                DAT_O = mem_rd_data_in ;
        end
end
always@(posedge CLK_I)
begin
    if (wr_sel)
    begin
        mem_wr_data_out         = wb_memory[ADR_I[11:2]] ;
 
        if ( SEL_I[3] )
            mem_wr_data_out[31:24] = DAT_I[31:24] ;
 
        if ( SEL_I[2] )
            mem_wr_data_out[23:16] = DAT_I[23:16] ;
 
        if ( SEL_I[1] )
            mem_wr_data_out[15: 8] = DAT_I[15: 8] ;
 
        if ( SEL_I[0] )
            mem_wr_data_out[ 7: 0] = DAT_I[ 7: 0] ;
 
        wb_memory[ADR_I[11:2]] <= mem_wr_data_out ;
    end
end
 
endmodule

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[/] [pci/] [tags/] [rel_7/] [bench/] [verilog/] [wb_slave_behavioral.v] - Blame information for rev 34

Line No.	Rev	Author	Line
1	15	mihad	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// File name: wb_slave_behavioral.v ////`
4			`//// ////`
5			`//// This file is part of the "PCI bridge" project ////`
6			`//// http://www.opencores.org/cores/pci/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Tadej Markovic, tadej@opencores.org ////`
10			`//// ////`
11			`//// All additional information is avaliable in the README.txt ////`
12			`//// file. ////`
13			`//// ////`
14			`//// ////`
15			`//////////////////////////////////////////////////////////////////////`
16			`//// ////`
17			`//// Copyright (C) 2000 Tadej Markovic, tadej@opencores.org ////`
18			`//// ////`
19			`//// This source file may be used and distributed without ////`
20			`//// restriction provided that this copyright statement is not ////`
21			`//// removed from the file and that any derivative work contains ////`
22			`//// the original copyright notice and the associated disclaimer. ////`
23			`//// ////`
24			`//// This source file is free software; you can redistribute it ////`
25			`//// and/or modify it under the terms of the GNU Lesser General ////`
26			`//// Public License as published by the Free Software Foundation; ////`
27			`//// either version 2.1 of the License, or (at your option) any ////`
28			`//// later version. ////`
29			`//// ////`
30			`//// This source is distributed in the hope that it will be ////`
31			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
32			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
33			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
34			`//// details. ////`
35			`//// ////`
36			`//// You should have received a copy of the GNU Lesser General ////`
37			`//// Public License along with this source; if not, download it ////`
38			`//// from http://www.opencores.org/lgpl.shtml ////`
39			`//// ////`
40			`//////////////////////////////////////////////////////////////////////`
41			`//`
42			`// CVS Revision History`
43			`//`
44			`// $Log: not supported by cvs2svn $`
45	34	mihad	`// Revision 1.1 2002/02/01 13:39:43 mihad`
46			`// Initial testbench import. Still under development`
47	15	mihad	`//`
48	34	mihad	`//`
49	15	mihad
50			`include "pci_testbench_defines.v"
51			`include "timescale.v"
52	34	mihad	`include "pci_constants.v"
53	15	mihad	`module WB_SLAVE_BEHAVIORAL`
54			`(`
55			`CLK_I,`
56			`RST_I,`
57			`ACK_O,`
58			`ADR_I,`
59			`CYC_I,`
60			`DAT_O,`
61			`DAT_I,`
62			`ERR_O,`
63			`RTY_O,`
64			`SEL_I,`
65			`STB_I,`
66			`WE_I,`
67			`CAB_I`
68			`);`
69
70			`/*----------------------------------------------------------------------------------------------------------------------`
71			`WISHBONE signals`
72			`----------------------------------------------------------------------------------------------------------------------*/`
73			`input CLK_I ;`
74			`input RST_I ;`
75			`output ACK_O ;`
76			input `WB_ADDR_TYPE ADR_I ;
77			`input CYC_I ;`
78			output `WB_DATA_TYPE DAT_O ;
79			input `WB_DATA_TYPE DAT_I ;
80			`output ERR_O ;`
81			`output RTY_O ;`
82			input `WB_SEL_TYPE SEL_I ;
83			`input STB_I ;`
84			`input WE_I ;`
85			`input CAB_I ;`
86
87			`//reg ACK_O ;`
88			`//reg ERR_O ;`
89			`//reg RTY_O ;`
90			`reg [31:0] DAT_O ;`
91
92			`/*----------------------------------------------------------------------------------------------------------------------`
93			`Asynchronous dual-port RAM signals for storing and fetching the data`
94			`----------------------------------------------------------------------------------------------------------------------*/`
95			`reg [31:0] wb_memory [0:1023] ; // data for WB memory - 16 LSB addresses are connected`
96			`reg [31:0] mem_wr_data_out ;`
97			`reg [31:0] mem_rd_data_in ;`
98
99			`/*----------------------------------------------------------------------------------------------------------------------`
100			`Maximum values for WAIT and RETRY counters and which response !!!`
101			`----------------------------------------------------------------------------------------------------------------------*/`
102			`reg [2:0] a_e_r_resp ; // tells with which cycle_termination_signal must wb_slave respond !`
103			`reg wait_cyc ;`
104			`reg [7:0] max_retry ;`
105
106			`// assign registers to default state while in reset`
107			`always@(RST_I)`
108			`begin`
109			`if (RST_I)`
110			`begin`
111			`a_e_r_resp <= 3'b000 ; // do not respond`
112			`wait_cyc <= 1'b0 ; // no wait cycles`
113			`max_retry <= 8'h0 ; // no retries`
114			`end`
115			`end //reset`
116
117			`task cycle_response ;`
118			`input [2:0] ack_err_rty_resp ; // acknowledge, error or retry response input flags`
119			`input wait_cycles ; // if wait cycles before each data termination cycle (ack, err or rty)`
120			`input [7:0] retry_cycles ; // noumber of retry cycles before acknowledge cycle`
121			`begin`
122			`// assign values`
123			`a_e_r_resp <= #1 ack_err_rty_resp ;`
124			`wait_cyc <= #1 wait_cycles ;`
125			`max_retry <= #1 retry_cycles ;`
126			`end`
127			`endtask // cycle_response`
128
129			`/*----------------------------------------------------------------------------------------------------------------------`
130			`Internal signals and logic`
131			`----------------------------------------------------------------------------------------------------------------------*/`
132			`reg calc_ack ;`
133			`reg calc_err ;`
134			`reg calc_rty ;`
135
136			`reg [7:0] retry_cnt ;`
137			`reg [7:0] retry_num ;`
138			`reg retry_expired ;`
139			`reg retry_rst ;`
140
141			`// RESET retry counter`
142			`always@(posedge RST_I or posedge CLK_I)`
143			`begin`
144			`if (RST_I)`
145			`retry_rst <= 1'b1 ;`
146			`else`
147			`retry_rst <= calc_ack \|\| calc_err ;`
148			`end`
149
150			`// Retry counter`
151			`always@(posedge retry_rst or negedge calc_rty)`
152			`begin`
153			`if (retry_rst)`
154			retry_cnt <= #`FF_DELAY 8'h00 ;
155			`else`
156			retry_cnt <= #`FF_DELAY retry_num ;
157			`end`
158			`always@(retry_cnt or max_retry)`
159			`begin`
160			`if (retry_cnt < max_retry)`
161			`begin`
162			`retry_num = retry_cnt + 1'b1 ;`
163			`retry_expired = #10 1'b0 ;`
164			`end`
165			`else`
166			`begin`
167			`retry_num = retry_cnt ;`
168			`retry_expired = #10 1'b1 ;`
169			`end`
170			`end`
171
172			`reg [1:0] wait_cnt ;`
173			`reg [1:0] wait_num ;`
174			`reg wait_expired ;`
175			`reg reset_wait ;`
176
177			`always@(posedge RST_I or posedge CLK_I)`
178			`begin`
179			`if (RST_I)`
180			reset_wait <= #`FF_DELAY 1'b1 ;
181			`else`
182			reset_wait <= #`FF_DELAY (wait_expired \|\| ~STB_I) ;
183			`end`
184
185			`// Wait counter`
186			`always@(posedge reset_wait or posedge CLK_I)`
187			`begin`
188			`if (reset_wait)`
189			wait_cnt <= #`FF_DELAY 4'h0 ;
190			`else`
191			wait_cnt <= #`FF_DELAY wait_num ;
192			`end`
193			`always@(wait_cnt or wait_cyc or STB_I or a_e_r_resp or retry_expired)`
194			`begin`
195			`if ((wait_cyc) && (STB_I))`
196			`begin`
197			`if (wait_cnt < 2'h2)`
198			`begin`
199			`wait_num = wait_cnt + 1'b1 ;`
200			`wait_expired = 1'b0 ;`
201			`calc_ack = 1'b0 ;`
202			`calc_err = 1'b0 ;`
203			`calc_rty = 1'b0 ;`
204			`end`
205			`else`
206			`begin`
207			`wait_num = wait_cnt ;`
208			`wait_expired = 1'b1 ;`
209			`if (a_e_r_resp == 3'b100)`
210			`begin`
211			`calc_ack = 1'b1 ;`
212			`calc_err = 1'b0 ;`
213			`calc_rty = 1'b0 ;`
214			`end`
215			`else`
216			`if (a_e_r_resp == 3'b010)`
217			`begin`
218			`calc_ack = 1'b0 ;`
219			`calc_err = 1'b1 ;`
220			`calc_rty = 1'b0 ;`
221			`end`
222			`else`
223			`if (a_e_r_resp == 3'b001)`
224			`begin`
225			`calc_err = 1'b0 ;`
226			`if (retry_expired)`
227			`begin`
228			`calc_ack = 1'b1 ;`
229			`calc_rty = 1'b0 ;`
230			`end`
231			`else`
232			`begin`
233			`calc_ack = 1'b0 ;`
234			`calc_rty = 1'b1 ;`
235			`end`
236			`end`
237			`else`
238			`begin`
239			`calc_ack = 1'b0 ;`
240			`calc_err = 1'b0 ;`
241			`calc_rty = 1'b0 ;`
242			`end`
243			`end`
244			`end`
245			`else`
246			`if ((~wait_cyc) && (STB_I))`
247			`begin`
248			`wait_num = 2'h0 ;`
249			`wait_expired = 1'b1 ;`
250			`if (a_e_r_resp == 3'b100)`
251			`begin`
252			`calc_ack = 1'b1 ;`
253			`calc_err = 1'b0 ;`
254			`calc_rty = 1'b0 ;`
255			`end`
256			`else`
257			`if (a_e_r_resp == 3'b010)`
258			`begin`
259			`calc_ack = 1'b0 ;`
260			`calc_err = 1'b1 ;`
261			`calc_rty = 1'b0 ;`
262			`end`
263			`else`
264			`if (a_e_r_resp == 3'b001)`
265			`begin`
266			`calc_err = 1'b0 ;`
267			`if (retry_expired)`
268			`begin`
269			`calc_ack = 1'b1 ;`
270			`calc_rty = 1'b0 ;`
271			`end`
272			`else`
273			`begin`
274			`calc_ack = 1'b0 ;`
275			`calc_rty = 1'b1 ;`
276			`end`
277			`end`
278			`else`
279			`begin`
280			`calc_ack = 1'b0 ;`
281			`calc_err = 1'b0 ;`
282			`calc_rty = 1'b0 ;`
283			`end`
284			`end`
285			`else`
286			`begin`
287			`wait_num = 2'h0 ;`
288			`wait_expired = 1'b0 ;`
289			`calc_ack = 1'b0 ;`
290			`calc_err = 1'b0 ;`
291			`calc_rty = 1'b0 ;`
292			`end`
293			`end`
294
295			`wire rd_sel = (CYC_I && STB_I && ~WE_I) ;`
296			`wire wr_sel = (CYC_I && STB_I && WE_I) ;`
297
298			`// Generate cycle termination signals`
299			`assign ACK_O = calc_ack && STB_I ;`
300			`assign ERR_O = calc_err && STB_I ;`
301			`assign RTY_O = calc_rty && STB_I ;`
302
303			`// Assign address to asynchronous memory`
304			`always@(ADR_I or RST_I)`
305			`begin`
306			`if (RST_I) // this is added because at start of test bench we need address change in order to get data!`
307			`mem_rd_data_in = 32'hxxxx_xxxx ;`
308			`else`
309			`mem_rd_data_in = wb_memory[ADR_I[11:2]] ;`
310			`end`
311
312			`// assign outputs to unknown state while in reset`
313			`always@(RST_I)`
314			`begin`
315			`if (RST_I)`
316			`begin`
317			`DAT_O <= 32'hxxxx_xxxx ;`
318			`end`
319			`end //reset`
320
321			`// Data input/output interface`
322			`always@(rd_sel or wr_sel or mem_rd_data_in or DAT_I or SEL_I or mem_wr_data_out)`
323			`begin`
324			`if (rd_sel)`
325			`begin`
326			`DAT_O = mem_rd_data_in ;`
327			`end`
328			`end`
329			`always@(posedge CLK_I)`
330			`begin`
331			`if (wr_sel)`
332			`begin`
333			`mem_wr_data_out = wb_memory[ADR_I[11:2]] ;`
334
335			`if ( SEL_I[3] )`
336			`mem_wr_data_out[31:24] = DAT_I[31:24] ;`
337
338			`if ( SEL_I[2] )`
339			`mem_wr_data_out[23:16] = DAT_I[23:16] ;`
340
341			`if ( SEL_I[1] )`
342			`mem_wr_data_out[15: 8] = DAT_I[15: 8] ;`
343
344			`if ( SEL_I[0] )`
345			`mem_wr_data_out[ 7: 0] = DAT_I[ 7: 0] ;`
346
347			`wb_memory[ADR_I[11:2]] <= mem_wr_data_out ;`
348			`end`
349			`end`
350
351			`endmodule`