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//////////////////////////////////////////////////////////////////////

////                                                              ////

////  File name "pci_bridge32.v"                                  ////

////                                                              ////

////  This file is part of the "PCI bridge" project               ////

////  http://www.opencores.org/cores/pci/                         ////

////                                                              ////

////  Author(s):                                                  ////

////      - Miha Dolenc (mihad@opencores.org)                     ////

////      - Tadej Markovic (tadej@opencores.org)                  ////

////                                                              ////

////  All additional information is avaliable in the README       ////

////  file.                                                       ////

////                                                              ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

////                                                              ////

//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org          ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

//

// CVS Revision History

//

// $Log: not supported by cvs2svn $

// Revision 1.9  2003/01/27 16:49:31  mihad

// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.

//

// Revision 1.8  2002/10/21 13:04:33  mihad

// Changed BIST signal names etc..

//

// Revision 1.7  2002/10/18 03:36:37  tadejm

// Changed wrong signal name scanb_sen into scanb_en.

//

// Revision 1.6  2002/10/17 22:51:50  tadejm

// Changed BIST signals for RAMs.

//

// Revision 1.5  2002/10/11 10:09:01  mihad

// Added additional testcase and changed rst name in BIST to trst

//

// Revision 1.4  2002/10/08 17:17:05  mihad

// Added BIST signals for RAMs.

//

// Revision 1.3  2002/02/01 15:25:12  mihad

// Repaired a few bugs, updated specification, added test bench files and design document

//

// Revision 1.2  2001/10/05 08:14:28  mihad

// Updated all files with inclusion of timescale file for simulation purposes.

//

// Revision 1.1.1.1  2001/10/02 15:33:46  mihad

// New project directory structure

//

//

`include "pci_constants.v"

// synopsys translate_off

`include "timescale.v"

// synopsys translate_on

// this is top level module of pci bridge core

// it instantiates and connects other lower level modules

// check polarity of PCI output enables in file out_reg.v and change it according to IO interface specification

module pci_bridge32

(

    // WISHBONE system signals

    wb_clk_i,

    wb_rst_i,

    wb_rst_o,

    wb_int_i,

    wb_int_o,

    // WISHBONE slave interface

    wbs_adr_i,

    wbs_dat_i,

    wbs_dat_o,

    wbs_sel_i,

    wbs_cyc_i,

    wbs_stb_i,

    wbs_we_i,

`ifdef PCI_WB_REV_B3

    wbs_cti_i,

    wbs_bte_i,

`else

    wbs_cab_i,

`endif

    wbs_ack_o,

    wbs_rty_o,

    wbs_err_o,

    // WISHBONE master interface

    wbm_adr_o,

    wbm_dat_i,

    wbm_dat_o,

    wbm_sel_o,

    wbm_cyc_o,

    wbm_stb_o,

    wbm_we_o,

    wbm_cab_o,

    wbm_ack_i,

    wbm_rty_i,

    wbm_err_i,

    // pci interface - system pins

    pci_clk_i,

    pci_rst_i,

    pci_rst_o,

    pci_inta_i,

    pci_inta_o,

    pci_rst_oe_o,

    pci_inta_oe_o,

    // arbitration pins

    pci_req_o,

    pci_req_oe_o,

    pci_gnt_i,

    // protocol pins

    pci_frame_i,

    pci_frame_o,

    pci_frame_oe_o,

    pci_irdy_oe_o,

    pci_devsel_oe_o,

    pci_trdy_oe_o,

    pci_stop_oe_o,

    pci_ad_oe_o,

    pci_cbe_oe_o,

    pci_irdy_i,

    pci_irdy_o,

    pci_idsel_i,

    pci_devsel_i,

    pci_devsel_o,

    pci_trdy_i,

    pci_trdy_o,

    pci_stop_i,

    pci_stop_o          ,

    // data transfer pins

    pci_ad_i,

    pci_ad_o,

    pci_cbe_i,

    pci_cbe_o,

    // parity generation and checking pins

    pci_par_i,

    pci_par_o,

    pci_par_oe_o,

    pci_perr_i,

    pci_perr_o,

    pci_perr_oe_o,

    // system error pin

    pci_serr_o,

    pci_serr_oe_o

`ifdef PCI_BIST

    ,

    // debug chain signals

    scanb_rst,      // bist scan reset

    scanb_clk,      // bist scan clock

    scanb_si,       // bist scan serial in

    scanb_so,       // bist scan serial out

    scanb_en        // bist scan shift enable

`endif

);

// WISHBONE system signals

input   wb_clk_i ;

input   wb_rst_i ;

output  wb_rst_o ;

input   wb_int_i ;

output  wb_int_o ;

// WISHBONE slave interface

input   [31:0]  wbs_adr_i ;

input   [31:0]  wbs_dat_i ;

output  [31:0]  wbs_dat_o ;

input   [3:0]   wbs_sel_i ;

input           wbs_cyc_i ;

input           wbs_stb_i ;

input           wbs_we_i ;

`ifdef PCI_WB_REV_B3

input [2:0] wbs_cti_i ;

input [1:0] wbs_bte_i ;

`else

input wbs_cab_i ;

`endif

output          wbs_ack_o ;

output          wbs_rty_o ;

output          wbs_err_o ;

// WISHBONE master interface

output  [31:0]  wbm_adr_o ;

input   [31:0]  wbm_dat_i ;

output  [31:0]  wbm_dat_o ;

output  [3:0]   wbm_sel_o ;

output          wbm_cyc_o ;

output          wbm_stb_o ;

output          wbm_we_o ;

output          wbm_cab_o ;

input           wbm_ack_i ;

input           wbm_rty_i ;

input           wbm_err_i ;

// pci interface - system pins

input   pci_clk_i ;

input   pci_rst_i ;

output  pci_rst_o ;

output  pci_rst_oe_o ;

input   pci_inta_i ;

output  pci_inta_o ;

output  pci_inta_oe_o ;

// arbitration pins

output  pci_req_o ;

output  pci_req_oe_o ;

input   pci_gnt_i ;

// protocol pins

input   pci_frame_i ;

output  pci_frame_o ;

output  pci_frame_oe_o ;

output  pci_irdy_oe_o ;

output  pci_devsel_oe_o ;

output  pci_trdy_oe_o ;

output  pci_stop_oe_o ;

output  [31:0] pci_ad_oe_o ;

output  [3:0]  pci_cbe_oe_o ;

input   pci_irdy_i ;

output  pci_irdy_o ;

input   pci_idsel_i ;

input   pci_devsel_i ;

output  pci_devsel_o ;

input   pci_trdy_i ;

output  pci_trdy_o ;

input   pci_stop_i ;

output  pci_stop_o ;

// data transfer pins

input   [31:0]  pci_ad_i ;

output  [31:0]  pci_ad_o ;

input   [3:0]   pci_cbe_i ;

output  [3:0]   pci_cbe_o ;

// parity generation and checking pins

input   pci_par_i ;

output  pci_par_o ;

output  pci_par_oe_o ;

input   pci_perr_i ;

output  pci_perr_o ;

output  pci_perr_oe_o ;

// system error pin

output  pci_serr_o ;

output  pci_serr_oe_o ;

`ifdef PCI_BIST

/*-----------------------------------------------------

BIST debug chain port signals

-----------------------------------------------------*/

input   scanb_rst;      // bist scan reset

input   scanb_clk;      // bist scan clock

input   scanb_si;       // bist scan serial in

output  scanb_so;       // bist scan serial out

input   scanb_en;       // bist scan shift enable

// internal wires for serial chain connection

wire SO_internal ;

wire SI_internal = SO_internal ;

`endif

// declare clock and reset wires

wire pci_clk = pci_clk_i ;

wire wb_clk  = wb_clk_i ;

wire reset ; // assigned at pci bridge reset and interrupt logic

/*=========================================================================================================

First comes definition of all modules' outputs, so they can be assigned to any other module's input later

  in the file, when module is instantiated

=========================================================================================================*/

// PCI BRIDGE RESET AND INTERRUPT LOGIC OUTPUTS

wire    pci_reso_reset ;

wire    pci_reso_pci_rstn_out ;

wire    pci_reso_pci_rstn_en_out ;

wire    pci_reso_rst_o ;

wire    pci_into_pci_intan_out ;

wire    pci_into_pci_intan_en_out ;

wire    pci_into_int_o ;

wire    pci_into_conf_isr_int_prop_out ;

// assign pci bridge reset interrupt logic outputs to top outputs where possible

assign reset            = pci_reso_reset ;

assign pci_rst_o     = pci_reso_pci_rstn_out ;

assign pci_rst_oe_o  = pci_reso_pci_rstn_en_out ;

assign wb_rst_o         = pci_reso_rst_o ;

assign pci_inta_o    = pci_into_pci_intan_out ;

assign pci_inta_oe_o = pci_into_pci_intan_en_out ;

assign wb_int_o         = pci_into_int_o ;

// WISHBONE SLAVE UNIT OUTPUTS

wire    [31:0]  wbu_sdata_out ;

wire            wbu_ack_out ;

wire            wbu_rty_out ;

wire            wbu_err_out ;

wire            wbu_pciif_req_out ;

wire            wbu_pciif_frame_out ;

wire            wbu_pciif_frame_en_out ;

wire            wbu_pciif_irdy_out ;

wire            wbu_pciif_irdy_en_out ;

wire    [31:0]  wbu_pciif_ad_out ;

wire            wbu_pciif_ad_en_out ;

wire    [3:0]   wbu_pciif_cbe_out ;

wire            wbu_pciif_cbe_en_out ;

wire    [31:0]  wbu_err_addr_out ;

wire    [3:0]   wbu_err_bc_out ;

wire            wbu_err_signal_out ;

wire            wbu_err_source_out ;

wire            wbu_err_rty_exp_out ;

wire            wbu_tabort_rec_out ;

wire            wbu_mabort_rec_out ;

wire    [11:0]  wbu_conf_offset_out ;

wire            wbu_conf_renable_out ;

wire            wbu_conf_wenable_out ;

wire    [3:0]   wbu_conf_be_out ;

wire    [31:0]  wbu_conf_data_out ;

wire            wbu_del_read_comp_pending_out ;

wire            wbu_wbw_fifo_empty_out ;

wire            wbu_ad_load_out ;

wire            wbu_ad_load_on_transfer_out ;

wire            wbu_pciif_frame_load_out ;

// PCI TARGET UNIT OUTPUTS

wire    [31:0]  pciu_adr_out ;

wire    [31:0]  pciu_mdata_out ;

wire            pciu_cyc_out ;

wire            pciu_stb_out ;

wire            pciu_we_out ;

wire    [3:0]   pciu_sel_out ;

wire            pciu_cab_out ;

wire            pciu_pciif_trdy_out ;

wire            pciu_pciif_stop_out ;

wire            pciu_pciif_devsel_out ;

wire            pciu_pciif_trdy_en_out ;

wire            pciu_pciif_stop_en_out ;

wire            pciu_pciif_devsel_en_out ;

wire            pciu_ad_load_out ;

wire            pciu_ad_load_on_transfer_out ;

wire   [31:0]   pciu_pciif_ad_out ;

wire            pciu_pciif_ad_en_out ;

wire            pciu_pciif_tabort_set_out ;

wire    [31:0]  pciu_err_addr_out ;

wire    [3:0]   pciu_err_bc_out ;

wire    [31:0]  pciu_err_data_out ;

wire    [3:0]   pciu_err_be_out ;

wire            pciu_err_signal_out ;

wire            pciu_err_source_out ;

wire            pciu_err_rty_exp_out ;

wire            pciu_conf_select_out ;

wire    [11:0]  pciu_conf_offset_out ;

wire            pciu_conf_renable_out ;

wire            pciu_conf_wenable_out ;

wire    [3:0]   pciu_conf_be_out ;

wire    [31:0]  pciu_conf_data_out ;

wire            pciu_pci_drcomp_pending_out ;

wire            pciu_pciw_fifo_empty_out ;

// assign pci target unit's outputs to top outputs where possible

assign wbm_adr_o    =   pciu_adr_out ;

assign wbm_dat_o   =   pciu_mdata_out ;

assign wbm_cyc_o    =   pciu_cyc_out ;

assign wbm_stb_o    =   pciu_stb_out ;

assign wbm_we_o     =   pciu_we_out ;

assign wbm_sel_o    =   pciu_sel_out ;

assign wbm_cab_o    =   pciu_cab_out ;

// CONFIGURATION SPACE OUTPUTS

wire    [31:0]  conf_w_data_out ;

wire    [31:0]  conf_r_data_out ;

wire            conf_serr_enable_out ;

wire            conf_perr_response_out ;

wire            conf_pci_master_enable_out ;

wire            conf_mem_space_enable_out ;

wire            conf_io_space_enable_out ;

wire    [7:0]   conf_cache_line_size_to_pci_out ;

wire    [7:0]   conf_cache_line_size_to_wb_out ;

wire            conf_cache_lsize_not_zero_to_wb_out ;

wire    [7:0]   conf_latency_tim_out ;

wire   [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)]   conf_pci_ba0_out ;

wire   [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)]   conf_pci_ba1_out ;

wire   [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)]   conf_pci_ba2_out ;

wire   [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)]   conf_pci_ba3_out ;

wire   [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)]   conf_pci_ba4_out ;

wire   [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)]   conf_pci_ba5_out ;

wire   [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)]   conf_pci_ta0_out ;

wire   [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)]   conf_pci_ta1_out ;

wire   [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)]   conf_pci_ta2_out ;

wire   [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)]   conf_pci_ta3_out ;

wire   [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)]   conf_pci_ta4_out ;

wire   [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)]   conf_pci_ta5_out ;

wire   [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)]   conf_pci_am0_out ;

wire   [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)]   conf_pci_am1_out ;

wire   [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)]   conf_pci_am2_out ;

wire   [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)]   conf_pci_am3_out ;

wire   [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)]   conf_pci_am4_out ;

wire   [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)]   conf_pci_am5_out ;

wire            conf_pci_mem_io0_out ;

wire            conf_pci_mem_io1_out ;

wire            conf_pci_mem_io2_out ;

wire            conf_pci_mem_io3_out ;

wire            conf_pci_mem_io4_out ;

wire            conf_pci_mem_io5_out ;

wire    [1:0]   conf_pci_img_ctrl0_out ;

wire    [1:0]   conf_pci_img_ctrl1_out ;

wire    [1:0]   conf_pci_img_ctrl2_out ;

wire    [1:0]   conf_pci_img_ctrl3_out ;

wire    [1:0]   conf_pci_img_ctrl4_out ;

wire    [1:0]   conf_pci_img_ctrl5_out ;

wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_ba0_out ;

wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_ba1_out ;

wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_ba2_out ;

wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_ba3_out ;

wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_ba4_out ;

wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_ba5_out ;

wire            conf_wb_mem_io0_out ;

wire            conf_wb_mem_io1_out ;

wire            conf_wb_mem_io2_out ;

wire            conf_wb_mem_io3_out ;

wire            conf_wb_mem_io4_out ;

wire            conf_wb_mem_io5_out ;

wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_am0_out ;

wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_am1_out ;

wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_am2_out ;

wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_am3_out ;

wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_am4_out ;

wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_am5_out ;

wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_ta0_out ;

wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_ta1_out ;

wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_ta2_out ;

wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_ta3_out ;

wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_ta4_out ;

wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_ta5_out ;

wire    [2:0]   conf_wb_img_ctrl0_out ;

wire    [2:0]   conf_wb_img_ctrl1_out ;

wire    [2:0]   conf_wb_img_ctrl2_out ;

wire    [2:0]   conf_wb_img_ctrl3_out ;

wire    [2:0]   conf_wb_img_ctrl4_out ;

wire    [2:0]   conf_wb_img_ctrl5_out ;

wire    [23:0]  conf_ccyc_addr_out ;

wire            conf_soft_res_out ;

wire            conf_int_out ;

// PCI IO MUX OUTPUTS

wire        pci_mux_frame_out ;

wire        pci_mux_irdy_out ;

wire        pci_mux_devsel_out ;

wire        pci_mux_trdy_out ;

wire        pci_mux_stop_out ;

wire [3:0]  pci_mux_cbe_out ;

wire [31:0] pci_mux_ad_out ;

wire        pci_mux_ad_load_out ;

wire [31:0] pci_mux_ad_en_out ;

wire        pci_mux_ad_en_unregistered_out ;

wire        pci_mux_frame_en_out ;

wire        pci_mux_irdy_en_out ;

wire        pci_mux_devsel_en_out ;

wire        pci_mux_trdy_en_out ;

wire        pci_mux_stop_en_out ;

wire [3:0]  pci_mux_cbe_en_out ;

wire        pci_mux_par_out ;

wire        pci_mux_par_en_out ;

wire        pci_mux_perr_out ;

wire        pci_mux_perr_en_out ;

wire        pci_mux_serr_out ;

wire        pci_mux_serr_en_out ;

wire        pci_mux_req_out ;

wire        pci_mux_req_en_out ;

// assign outputs to top level outputs

assign pci_ad_oe_o       = pci_mux_ad_en_out ;

assign pci_frame_oe_o   = pci_mux_frame_en_out ;

assign pci_irdy_oe_o    = pci_mux_irdy_en_out ;

assign pci_cbe_oe_o     = pci_mux_cbe_en_out ;

assign pci_par_o         =   pci_mux_par_out ;

assign pci_par_oe_o      =   pci_mux_par_en_out ;

assign pci_perr_o       =   pci_mux_perr_out ;

assign pci_perr_oe_o    =   pci_mux_perr_en_out ;

assign pci_serr_o       =   pci_mux_serr_out ;

assign pci_serr_oe_o    =   pci_mux_serr_en_out ;

assign pci_req_o        =   pci_mux_req_out ;

assign pci_req_oe_o     =   pci_mux_req_en_out ;

assign pci_trdy_oe_o    = pci_mux_trdy_en_out ;

assign pci_devsel_oe_o  = pci_mux_devsel_en_out ;

assign pci_stop_oe_o    = pci_mux_stop_en_out ;

assign pci_trdy_o       =  pci_mux_trdy_out ;

assign pci_devsel_o     = pci_mux_devsel_out ;

assign pci_stop_o       = pci_mux_stop_out ;

assign pci_ad_o          = pci_mux_ad_out ;

assign pci_frame_o      = pci_mux_frame_out ;

assign pci_irdy_o       = pci_mux_irdy_out ;

assign pci_cbe_o        = pci_mux_cbe_out ;

// duplicate output register's outputs

wire            out_bckp_frame_out ;

wire            out_bckp_irdy_out ;

wire            out_bckp_devsel_out ;

wire            out_bckp_trdy_out ;

wire            out_bckp_stop_out ;

wire    [3:0]   out_bckp_cbe_out ;

wire            out_bckp_cbe_en_out ;

wire    [31:0]  out_bckp_ad_out ;

wire            out_bckp_ad_en_out ;

wire            out_bckp_irdy_en_out ;

wire            out_bckp_frame_en_out ;

wire            out_bckp_tar_ad_en_out ;

wire            out_bckp_mas_ad_en_out ;

wire            out_bckp_trdy_en_out ;

wire            out_bckp_par_out ;

wire            out_bckp_par_en_out ;

wire            out_bckp_perr_out ;

wire            out_bckp_perr_en_out ;

wire            out_bckp_serr_out ;

wire            out_bckp_serr_en_out ;

// PARITY CHECKER OUTPUTS

wire    parchk_pci_par_out ;

wire    parchk_pci_par_en_out ;

wire    parchk_pci_perr_out ;

wire    parchk_pci_perr_en_out ;

wire    parchk_pci_serr_out ;

wire    parchk_pci_serr_en_out ;

wire    parchk_par_err_detect_out ;

wire    parchk_perr_mas_detect_out ;

wire    parchk_sig_serr_out ;

// input register outputs

wire            in_reg_gnt_out ;

wire            in_reg_frame_out ;

wire            in_reg_irdy_out ;

wire            in_reg_trdy_out ;

wire            in_reg_stop_out ;

wire            in_reg_devsel_out ;

wire            in_reg_idsel_out ;

wire    [31:0]  in_reg_ad_out ;

wire    [3:0]   in_reg_cbe_out ;

/*=========================================================================================================

Now comes definition of all modules' and their appropriate inputs

=========================================================================================================*/

// PCI BRIDGE RESET AND INTERRUPT LOGIC INPUTS

wire    pci_resi_rst_i                  = wb_rst_i ;

wire    pci_resi_pci_rstn_in            = pci_rst_i ;

wire    pci_resi_conf_soft_res_in       = conf_soft_res_out ;

wire    pci_inti_pci_intan_in           = pci_inta_i ;

wire    pci_inti_conf_int_in            = conf_int_out ;

wire    pci_inti_int_i                  = wb_int_i ;

wire    pci_inti_out_bckp_perr_en_in    = out_bckp_perr_en_out ;

wire    pci_inti_out_bckp_serr_en_in    = out_bckp_serr_en_out ;

pci_rst_int pci_resets_and_interrupts

(

    .clk_in                 (pci_clk),

    .rst_i                  (pci_resi_rst_i),

    .pci_rstn_in            (pci_resi_pci_rstn_in),

    .conf_soft_res_in       (pci_resi_conf_soft_res_in),

    .reset                  (pci_reso_reset),

    .pci_rstn_out           (pci_reso_pci_rstn_out),

    .pci_rstn_en_out        (pci_reso_pci_rstn_en_out),

    .rst_o                  (pci_reso_rst_o),

    .pci_intan_in           (pci_inti_pci_intan_in),

    .conf_int_in            (pci_inti_conf_int_in),

    .int_i                  (pci_inti_int_i),

    .out_bckp_perr_en_in    (pci_inti_out_bckp_perr_en_in),

    .out_bckp_serr_en_in    (pci_inti_out_bckp_serr_en_in),

    .pci_intan_out          (pci_into_pci_intan_out),

    .pci_intan_en_out       (pci_into_pci_intan_en_out),

    .int_o                  (pci_into_int_o),

    .conf_isr_int_prop_out  (pci_into_conf_isr_int_prop_out)

);

`ifdef PCI_WB_REV_B3

wire            wbs_wbb3_2_wbb2_cyc_o   ;

wire            wbs_wbb3_2_wbb2_stb_o   ;

wire    [31:0]  wbs_wbb3_2_wbb2_adr_o   ;

wire    [31:0]  wbs_wbb3_2_wbb2_dat_i_o ;

wire    [31:0]  wbs_wbb3_2_wbb2_dat_o_o ;

wire            wbs_wbb3_2_wbb2_we_o    ;

wire    [ 3:0]  wbs_wbb3_2_wbb2_sel_o   ;

wire            wbs_wbb3_2_wbb2_ack_o   ;

wire            wbs_wbb3_2_wbb2_err_o   ;

wire            wbs_wbb3_2_wbb2_rty_o   ;

wire            wbs_wbb3_2_wbb2_cab_o   ;

// assign wishbone slave unit's outputs to top outputs where possible

assign wbs_dat_o    =   wbs_wbb3_2_wbb2_dat_o_o ;

assign wbs_ack_o    =   wbs_wbb3_2_wbb2_ack_o   ;

assign wbs_rty_o    =   wbs_wbb3_2_wbb2_rty_o   ;

assign wbs_err_o    =   wbs_wbb3_2_wbb2_err_o       ;

wire            wbs_wbb3_2_wbb2_cyc_i   =   wbs_cyc_i       ;

wire            wbs_wbb3_2_wbb2_stb_i   =   wbs_stb_i       ;

wire            wbs_wbb3_2_wbb2_we_i    =   wbs_we_i        ;

wire            wbs_wbb3_2_wbb2_ack_i   =   wbu_ack_out     ;

wire            wbs_wbb3_2_wbb2_err_i   =   wbu_err_out     ;

wire            wbs_wbb3_2_wbb2_rty_i   =   wbu_rty_out     ;

wire    [31:0]  wbs_wbb3_2_wbb2_adr_i   =   wbs_adr_i       ;

wire    [ 3:0]  wbs_wbb3_2_wbb2_sel_i   =   wbs_sel_i       ;

wire    [31:0]  wbs_wbb3_2_wbb2_dat_i_i =   wbs_dat_i       ;

wire    [31:0]  wbs_wbb3_2_wbb2_dat_o_i =   wbu_sdata_out   ;