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//////////////////////////////////////////////////////////////////////
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//// ////
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//// File name: pci_target32_interface.v ////
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//// ////
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//// This file is part of the "PCI bridge" project ////
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//// http://www.opencores.org/cores/pci/ ////
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//// ////
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//// Author(s): ////
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//// - Tadej Markovic, tadej@opencores.org ////
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//// ////
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//// All additional information is avaliable in the README.txt ////
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//// file. ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 Tadej Markovic, tadej@opencores.org ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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tadejm |
// Revision 1.7 2003/01/27 16:49:31 mihad
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// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
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//
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mihad |
// Revision 1.6 2003/01/21 16:06:56 mihad
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// Bug fixes, testcases added.
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//
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mihad |
// Revision 1.5 2002/08/22 13:28:04 mihad
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// Updated for synthesis purposes. Gate level simulation was failing in some configurations
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//
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mihad |
// Revision 1.4 2002/02/19 16:32:37 mihad
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// Modified testbench and fixed some bugs
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//
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mihad |
// Revision 1.3 2002/02/01 15:25:12 mihad
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// Repaired a few bugs, updated specification, added test bench files and design document
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//
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mihad |
// Revision 1.2 2001/10/05 08:14:30 mihad
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// Updated all files with inclusion of timescale file for simulation purposes.
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//
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// Revision 1.1.1.1 2001/10/02 15:33:47 mihad
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// New project directory structure
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//
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//
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`include "bus_commands.v"
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`include "pci_constants.v"
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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module pci_target32_interface
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(
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// system inputs
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clk_in,
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reset_in,
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// PCI Target side of INTERFACE
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address_in,
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addr_claim_out,
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bc_in,
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bc0_in,
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data_in,
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data_out,
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be_in,
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next_be_in,
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req_in,
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rdy_in,
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addr_phase_in,
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bckp_devsel_in,
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bckp_trdy_in,
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bckp_stop_in,
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last_reg_in,
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frame_reg_in,
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fetch_pcir_fifo_in,
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load_medium_reg_in,
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sel_fifo_mreg_in,
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sel_conf_fifo_in,
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fetch_conf_in,
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load_to_pciw_fifo_in,
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load_to_conf_in,
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same_read_out,
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norm_access_to_config_out,
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read_completed_out,
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read_processing_out,
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target_abort_out,
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disconect_wo_data_out,
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disconect_w_data_out,
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pciw_fifo_full_out,
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pcir_fifo_data_err_out,
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wbw_fifo_empty_out,
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wbu_del_read_comp_pending_out,
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// Delayed synchronizacion module signals
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req_out,
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done_out,
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in_progress_out,
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req_req_pending_in,
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req_comp_pending_in,
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addr_out,
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be_out,
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we_out,
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bc_out,
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burst_ok_out,
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strd_addr_in,
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strd_bc_in,
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status_in,
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comp_flush_in,
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// FIFO signals
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pcir_fifo_renable_out,
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pcir_fifo_data_in,
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pcir_fifo_be_in,
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pcir_fifo_control_in,
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pcir_fifo_flush_out,
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pcir_fifo_almost_empty_in,
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pcir_fifo_empty_in,
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pciw_fifo_wenable_out,
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pciw_fifo_addr_data_out,
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pciw_fifo_cbe_out,
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pciw_fifo_control_out,
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pciw_fifo_three_left_in,
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pciw_fifo_two_left_in,
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pciw_fifo_almost_full_in,
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pciw_fifo_full_in,
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wbw_fifo_empty_in,
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wbu_del_read_comp_pending_in,
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// Configuration space signals
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conf_hit_out,
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conf_addr_out,
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conf_data_out,
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conf_data_in,
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conf_be_out,
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conf_we_out,
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conf_re_out,
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mem_enable_in,
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io_enable_in,
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mem_io_addr_space0_in,
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mem_io_addr_space1_in,
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mem_io_addr_space2_in,
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mem_io_addr_space3_in,
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mem_io_addr_space4_in,
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mem_io_addr_space5_in,
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pre_fetch_en0_in,
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pre_fetch_en1_in,
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pre_fetch_en2_in,
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pre_fetch_en3_in,
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pre_fetch_en4_in,
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pre_fetch_en5_in,
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pci_base_addr0_in,
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pci_base_addr1_in,
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pci_base_addr2_in,
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pci_base_addr3_in,
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pci_base_addr4_in,
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pci_base_addr5_in,
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pci_addr_mask0_in,
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pci_addr_mask1_in,
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pci_addr_mask2_in,
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pci_addr_mask3_in,
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pci_addr_mask4_in,
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pci_addr_mask5_in,
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pci_tran_addr0_in,
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pci_tran_addr1_in,
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pci_tran_addr2_in,
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pci_tran_addr3_in,
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pci_tran_addr4_in,
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pci_tran_addr5_in,
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addr_tran_en0_in,
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addr_tran_en1_in,
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addr_tran_en2_in,
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addr_tran_en3_in,
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addr_tran_en4_in,
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addr_tran_en5_in
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) ;
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/*==================================================================================================================
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System inputs.
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==================================================================================================================*/
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// PCI side clock and reset
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input clk_in,
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reset_in ;
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/*==================================================================================================================
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Side of the PCI Target state machine
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==================================================================================================================*/
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// Data, byte enables, bus commands and address ports
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input [31:0] address_in ; // current request address input - registered
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output addr_claim_out ; // current request address claim output
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input [3:0] bc_in ; // current request bus command input - registered
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input bc0_in ; // current cycle RW signal
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output [31:0] data_out ; // for read operations - current dataphase data output
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input [31:0] data_in ; // for write operations - current request data input - registered
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input [3:0] be_in ; // current dataphase byte enable inputs - registered
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tadejm |
input [3:0] next_be_in ; // next dataphase byte enable inputs - NOT registered
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// Port connection control signals from PCI FSM
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input req_in ; // Read is requested to WB master from PCI side
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input rdy_in ; // DATA / ADDRESS selection from PCI side when read or write - registered
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input addr_phase_in ; // Indicates address phase and also fast-back-to-back address phase - registered
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input bckp_devsel_in ; // DEVSEL input (which is registered) equivalent
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input bckp_trdy_in ; // TRDY input (which is registered) equivalent
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input bckp_stop_in ; // STOP input (which is registered) equivalent
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input last_reg_in ; // Indicates last data phase - registered
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input frame_reg_in ; // FRAME input signal - registered
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input fetch_pcir_fifo_in ;// Read enable for PCIR_FIFO when when read is finishen on WB side
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input load_medium_reg_in ;// Load data from PCIR_FIFO to medium register (first data must be prepared on time)
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input sel_fifo_mreg_in ; // Read data selection between PCIR_FIFO and medium register
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input sel_conf_fifo_in ; // Read data selection between Configuration registers and "FIFO"
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input fetch_conf_in ; // Read enable for configuration space registers
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input load_to_pciw_fifo_in ;// Write enable to PCIW_FIFO
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input load_to_conf_in ; // Write enable to Configuration space registers
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/*==================================================================================================================
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Status outputs to PCI side (FSM)
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==================================================================================================================*/
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output same_read_out ; // Indicates the same read request (important when read is finished on WB side)
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output norm_access_to_config_out ; // Indicates the access to Configuration space with MEMORY commands
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output read_completed_out ; // Indicates that read request is completed on WB side
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output read_processing_out ; // Indicates that read request is processing on WB side
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output target_abort_out ; // Indicates target abort termination
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output disconect_wo_data_out ; // Indicates disconnect without data termination
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output disconect_w_data_out ; // Indicates disconnect with data termination
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output pciw_fifo_full_out ; // Indicates that write PCIW_FIFO is full
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output pcir_fifo_data_err_out ; // Indicates data error on current data read from PCIR_FIFO
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output wbw_fifo_empty_out ; // Indicates that WB SLAVE has no data to be written to PCI bus
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output wbu_del_read_comp_pending_out ; // Indicates that WB Unit has a delayed read poending!
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2 |
mihad |
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/*==================================================================================================================
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Read request interface through Delayed sinchronization module to WB Master
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==================================================================================================================*/
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// request, completion, done and progress indicator outputs for delayed_sync module where they are synchronized
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output req_out, // request qualifier - when 1 it indicates that valid data is provided on outputs
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done_out, // done output - when 1 indicates that PCI Target has completed a cycle on its bus
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in_progress_out ; // out progress indicator - indicates that current completion is in progress on
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// PCI Target side
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// pending indication inputs - PCI Target side must know about requests and completions
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input req_req_pending_in ; // request pending input for PCI Target side
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input req_comp_pending_in ; // completion pending input for PCI Target side - it indicates when completion
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// is ready for completing on PCI Target bus
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// various data outputs - PCI Target sets address, bus command, byte enables, write enable and burst
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output [31:0] addr_out ; // address bus output
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output [3:0] be_out ; // byte enable output
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output we_out ; // write enable output - read/write request indication 1 = write request / 0 = read request
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output [3:0] bc_out ; // bus command output
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21 |
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output burst_ok_out ; // pre-fetch enable & burst read - qualifies pre-fetch for access to current image space
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2 |
mihad |
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// completion side signals encoded termination status - 0 = normal completion / 1 = error terminated completion
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input [31:0] strd_addr_in ; // Stored requested read access address
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input [3:0] strd_bc_in ; // Stored requested read access bus command
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input status_in ; // Error status reported - NOT USED because FIFO control bits determin data error status
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input comp_flush_in ; // If completition counter (2^16 clk periods) has expired, PCIR_FIFO must flush data
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/*==================================================================================================================
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PCIR_PCIW_FIFO signals from pci side
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282 |
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==================================================================================================================*/
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21 |
mihad |
// PCIR_FIFO control signals used for fetching data from PCIR_FIFO
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2 |
mihad |
output pcir_fifo_renable_out ; // read enable output to PCIR_FIFO
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input [31:0] pcir_fifo_data_in ; // data input from PCIR_FIFO
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input [3:0] pcir_fifo_be_in ; // byte enable input from PCIR_FIFO
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287 |
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input [3:0] pcir_fifo_control_in ; // control signals input from PCIR_FIFO
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288 |
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output pcir_fifo_flush_out ; // flush PCIR_FIFO
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input pcir_fifo_almost_empty_in ; // almost empty indicator from PCIR_FIFO
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input pcir_fifo_empty_in ; // empty indicator
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// PCIW_FIFO control signals used for sinking data into PCIW_FIFO and status monitoring
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output pciw_fifo_wenable_out ; // write enable output to PCIW_FIFO
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108 |
tadejm |
wire pciw_fifo_wenable ; // not registered we
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2 |
mihad |
output [31:0] pciw_fifo_addr_data_out ; // address / data output signals to PCIW_FIFO
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output [3:0] pciw_fifo_cbe_out ; // command / byte enable signals to PCIW_FIFO
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output [3:0] pciw_fifo_control_out ; // control signals to PCIW_FIFO
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298 |
108 |
tadejm |
input pciw_fifo_three_left_in ; // three data spaces left in PCIW_FIFO
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input pciw_fifo_two_left_in ; // two data spaces left in PCIW_FIFO
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2 |
mihad |
input pciw_fifo_almost_full_in ; // almost full indicator from PCIW_FIFO
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input pciw_fifo_full_in ; // full indicator from PCIW_FIFO
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// WBW_FIFO empy control signal used when delayed read is complete in PCIR_FIFO
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input wbw_fifo_empty_in ; // empty indicator from WBW_FIFO
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21 |
mihad |
input wbu_del_read_comp_pending_in ; // delayed read pending indicator from WB Unit
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306 |
2 |
mihad |
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307 |
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308 |
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/*==================================================================================================================
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309 |
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Configuration space signals - from and to registers
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310 |
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==================================================================================================================*/
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311 |
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// BUS for reading and writing to configuration space registers
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312 |
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output conf_hit_out ; // like "chip select" for configuration space
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313 |
|
|
output [11:0] conf_addr_out ; // address to configuration space when there is access to it
|
314 |
|
|
output [31:0] conf_data_out ; // data to configuration space - for writing to registers
|
315 |
|
|
input [31:0] conf_data_in ; // data from configuration space - for reading from registers
|
316 |
|
|
output [3:0] conf_be_out ; // byte enables used for correct writing to configuration space
|
317 |
|
|
output conf_we_out ; // write enable control signal - 1 for writing / 0 for nothing
|
318 |
|
|
output conf_re_out ; // read enable control signal - 1 for reading / 0 for nothing
|
319 |
|
|
|
320 |
|
|
// Inputs for image control registers
|
321 |
|
|
input mem_enable_in ; // allowed access to memory mapped image
|
322 |
|
|
input io_enable_in ; // allowed access to io mapped image
|
323 |
|
|
|
324 |
|
|
// Inputs needed for determining if image is assigned to memory or io space with pre-fetch and address translation
|
325 |
21 |
mihad |
input mem_io_addr_space0_in ; // bit-0 in pci_base_addr0 register
|
326 |
|
|
input mem_io_addr_space1_in ; // bit-0 in pci_base_addr1 register
|
327 |
|
|
input mem_io_addr_space2_in ; // bit-0 in pci_base_addr2 register
|
328 |
|
|
input mem_io_addr_space3_in ; // bit-0 in pci_base_addr3 register
|
329 |
|
|
input mem_io_addr_space4_in ; // bit-0 in pci_base_addr4 register
|
330 |
2 |
mihad |
input mem_io_addr_space5_in ; // bit-0 in pci_base_addr5 register
|
331 |
|
|
input pre_fetch_en0_in ; // bit-1 in pci_image_ctr0 register
|
332 |
|
|
input pre_fetch_en1_in ; // bit-1 in pci_image_ctr1 register
|
333 |
|
|
input pre_fetch_en2_in ; // bit-1 in pci_image_ctr2 register
|
334 |
|
|
input pre_fetch_en3_in ; // bit-1 in pci_image_ctr3 register
|
335 |
|
|
input pre_fetch_en4_in ; // bit-1 in pci_image_ctr4 register
|
336 |
|
|
input pre_fetch_en5_in ; // bit-1 in pci_image_ctr5 register
|
337 |
|
|
|
338 |
|
|
// Input from image registers - register values needed for decoder to work properly
|
339 |
|
|
input [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_base_addr0_in ; // base address from base address register
|
340 |
|
|
input [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_base_addr1_in ; // base address from base address register
|
341 |
|
|
input [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_base_addr2_in ; // base address from base address register
|
342 |
|
|
input [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_base_addr3_in ; // base address from base address register
|
343 |
|
|
input [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_base_addr4_in ; // base address from base address register
|
344 |
|
|
input [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_base_addr5_in ; // base address from base address register
|
345 |
|
|
input [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_addr_mask0_in ; // masking of base address from address mask register
|
346 |
|
|
input [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_addr_mask1_in ; // masking of base address from address mask register
|
347 |
|
|
input [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_addr_mask2_in ; // masking of base address from address mask register
|
348 |
|
|
input [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_addr_mask3_in ; // masking of base address from address mask register
|
349 |
|
|
input [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_addr_mask4_in ; // masking of base address from address mask register
|
350 |
|
|
input [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_addr_mask5_in ; // masking of base address from address mask register
|
351 |
|
|
input [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_tran_addr0_in ; // translation address from address translation register
|
352 |
|
|
input [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_tran_addr1_in ; // translation address from address translation register
|
353 |
|
|
input [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_tran_addr2_in ; // translation address from address translation register
|
354 |
|
|
input [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_tran_addr3_in ; // translation address from address translation register
|
355 |
|
|
input [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_tran_addr4_in ; // translation address from address translation register
|
356 |
|
|
input [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_tran_addr5_in ; // translation address from address translation register
|
357 |
|
|
|
358 |
|
|
input addr_tran_en0_in ; // address translation enable bit
|
359 |
|
|
input addr_tran_en1_in ; // address translation enable bit
|
360 |
|
|
input addr_tran_en2_in ; // address translation enable bit
|
361 |
|
|
input addr_tran_en3_in ; // address translation enable bit
|
362 |
|
|
input addr_tran_en4_in ; // address translation enable bit
|
363 |
|
|
input addr_tran_en5_in ; // address translation enable bit
|
364 |
|
|
|
365 |
|
|
/*==================================================================================================================
|
366 |
|
|
END of input / output PORT DEFINITONS !!!
|
367 |
|
|
==================================================================================================================*/
|
368 |
|
|
|
369 |
|
|
// address output from address multiplexer
|
370 |
|
|
reg [31:0] address ;
|
371 |
|
|
// prefetch enable for access to selected image space
|
372 |
|
|
reg pre_fetch_en ;
|
373 |
|
|
|
374 |
|
|
// Input addresses and image hits from address decoders - addresses are multiplexed to address
|
375 |
21 |
mihad |
`ifdef HOST
|
376 |
|
|
`ifdef NO_CNF_IMAGE
|
377 |
|
|
`ifdef PCI_IMAGE0 // if PCI bridge is HOST and IMAGE0 is assigned as general image space
|
378 |
2 |
mihad |
wire hit0_in ;
|
379 |
|
|
wire [31:0] address0_in ;
|
380 |
21 |
mihad |
wire pre_fetch_en0 = pre_fetch_en0_in ;
|
381 |
|
|
`else
|
382 |
|
|
wire hit0_in = 1'b0 ;
|
383 |
|
|
wire [31:0] address0_in = 32'h0 ;
|
384 |
|
|
wire pre_fetch_en0 = 1'b0 ;
|
385 |
|
|
`endif
|
386 |
|
|
`else
|
387 |
|
|
wire hit0_in ;
|
388 |
|
|
wire [31:0] address0_in ;
|
389 |
|
|
wire pre_fetch_en0 = pre_fetch_en0_in ;
|
390 |
|
|
`endif
|
391 |
|
|
`else // GUEST
|
392 |
|
|
wire hit0_in ;
|
393 |
|
|
wire [31:0] address0_in ;
|
394 |
|
|
wire pre_fetch_en0 = pre_fetch_en0_in ;
|
395 |
|
|
`endif
|
396 |
|
|
|
397 |
2 |
mihad |
wire hit1_in ;
|
398 |
|
|
wire [31:0] address1_in ;
|
399 |
21 |
mihad |
wire pre_fetch_en1 = pre_fetch_en1_in ;
|
400 |
|
|
|
401 |
|
|
`ifdef PCI_IMAGE2
|
402 |
2 |
mihad |
wire hit2_in ;
|
403 |
|
|
wire [31:0] address2_in ;
|
404 |
21 |
mihad |
wire pre_fetch_en2 = pre_fetch_en2_in ;
|
405 |
|
|
`else
|
406 |
|
|
wire hit2_in = 1'b0 ;
|
407 |
|
|
wire [31:0] address2_in = 32'h0 ;
|
408 |
|
|
wire pre_fetch_en2 = 1'b0 ;
|
409 |
2 |
mihad |
`endif
|
410 |
21 |
mihad |
|
411 |
2 |
mihad |
`ifdef PCI_IMAGE3
|
412 |
|
|
wire hit3_in ;
|
413 |
|
|
wire [31:0] address3_in ;
|
414 |
21 |
mihad |
wire pre_fetch_en3 = pre_fetch_en3_in ;
|
415 |
|
|
`else
|
416 |
|
|
wire hit3_in = 1'b0 ;
|
417 |
|
|
wire [31:0] address3_in = 32'h0 ;
|
418 |
|
|
wire pre_fetch_en3 = 1'b0 ;
|
419 |
2 |
mihad |
`endif
|
420 |
21 |
mihad |
|
421 |
2 |
mihad |
`ifdef PCI_IMAGE4
|
422 |
|
|
wire hit4_in ;
|
423 |
|
|
wire [31:0] address4_in ;
|
424 |
21 |
mihad |
wire pre_fetch_en4 = pre_fetch_en4_in ;
|
425 |
|
|
`else
|
426 |
|
|
wire hit4_in = 1'b0 ;
|
427 |
|
|
wire [31:0] address4_in = 32'h0 ;
|
428 |
|
|
wire pre_fetch_en4 = 1'b0 ;
|
429 |
2 |
mihad |
`endif
|
430 |
21 |
mihad |
|
431 |
2 |
mihad |
`ifdef PCI_IMAGE5
|
432 |
|
|
wire hit5_in ;
|
433 |
|
|
wire [31:0] address5_in ;
|
434 |
21 |
mihad |
wire pre_fetch_en5 = pre_fetch_en5_in ;
|
435 |
|
|
`else
|
436 |
|
|
wire hit5_in = 1'b0 ;
|
437 |
|
|
wire [31:0] address5_in = 32'h0 ;
|
438 |
|
|
wire pre_fetch_en5 = 1'b0 ;
|
439 |
2 |
mihad |
`endif
|
440 |
|
|
|
441 |
|
|
// Include address decoders
|
442 |
21 |
mihad |
`ifdef HOST
|
443 |
|
|
`ifdef NO_CNF_IMAGE
|
444 |
|
|
`ifdef PCI_IMAGE0 // if PCI bridge is HOST and IMAGE0 is assigned as general image space
|
445 |
77 |
mihad |
pci_pci_decoder #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder0
|
446 |
21 |
mihad |
(.hit (hit0_in),
|
447 |
|
|
.addr_out (address0_in),
|
448 |
|
|
.addr_in (address_in),
|
449 |
|
|
.bc_in (bc_in),
|
450 |
2 |
mihad |
.base_addr (pci_base_addr0_in),
|
451 |
21 |
mihad |
.mask_addr (pci_addr_mask0_in),
|
452 |
|
|
.tran_addr (pci_tran_addr0_in),
|
453 |
2 |
mihad |
.at_en (addr_tran_en0_in),
|
454 |
21 |
mihad |
.mem_io_space (mem_io_addr_space0_in),
|
455 |
|
|
.mem_en (mem_enable_in),
|
456 |
2 |
mihad |
.io_en (io_enable_in)
|
457 |
|
|
) ;
|
458 |
21 |
mihad |
`endif
|
459 |
|
|
`else
|
460 |
77 |
mihad |
pci_pci_decoder #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder0
|
461 |
21 |
mihad |
(.hit (hit0_in),
|
462 |
|
|
.addr_out (address0_in),
|
463 |
|
|
.addr_in (address_in),
|
464 |
|
|
.bc_in (bc_in),
|
465 |
|
|
.base_addr (pci_base_addr0_in),
|
466 |
|
|
.mask_addr (pci_addr_mask0_in),
|
467 |
|
|
.tran_addr (pci_tran_addr0_in),
|
468 |
|
|
.at_en (addr_tran_en0_in),
|
469 |
|
|
.mem_io_space (mem_io_addr_space0_in),
|
470 |
|
|
.mem_en (mem_enable_in),
|
471 |
|
|
.io_en (io_enable_in)
|
472 |
|
|
) ;
|
473 |
|
|
`endif
|
474 |
|
|
`else // GUEST
|
475 |
77 |
mihad |
pci_pci_decoder #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder0
|
476 |
21 |
mihad |
(.hit (hit0_in),
|
477 |
|
|
.addr_out (address0_in),
|
478 |
|
|
.addr_in (address_in),
|
479 |
|
|
.bc_in (bc_in),
|
480 |
|
|
.base_addr (pci_base_addr0_in),
|
481 |
|
|
.mask_addr (pci_addr_mask0_in),
|
482 |
|
|
.tran_addr (pci_tran_addr0_in),
|
483 |
|
|
.at_en (addr_tran_en0_in),
|
484 |
|
|
.mem_io_space (mem_io_addr_space0_in),
|
485 |
|
|
.mem_en (mem_enable_in),
|
486 |
|
|
.io_en (io_enable_in)
|
487 |
|
|
) ;
|
488 |
|
|
`endif
|
489 |
77 |
mihad |
pci_pci_decoder #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder1
|
490 |
21 |
mihad |
(.hit (hit1_in),
|
491 |
|
|
.addr_out (address1_in),
|
492 |
|
|
.addr_in (address_in),
|
493 |
|
|
.bc_in (bc_in),
|
494 |
2 |
mihad |
.base_addr (pci_base_addr1_in),
|
495 |
21 |
mihad |
.mask_addr (pci_addr_mask1_in),
|
496 |
|
|
.tran_addr (pci_tran_addr1_in),
|
497 |
|
|
.at_en (addr_tran_en1_in),
|
498 |
|
|
.mem_io_space (mem_io_addr_space1_in),
|
499 |
|
|
.mem_en (mem_enable_in),
|
500 |
2 |
mihad |
.io_en (io_enable_in)
|
501 |
|
|
) ;
|
502 |
21 |
mihad |
`ifdef PCI_IMAGE2
|
503 |
77 |
mihad |
pci_pci_decoder #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder2
|
504 |
21 |
mihad |
(.hit (hit2_in),
|
505 |
|
|
.addr_out (address2_in),
|
506 |
|
|
.addr_in (address_in),
|
507 |
|
|
.bc_in (bc_in),
|
508 |
2 |
mihad |
.base_addr (pci_base_addr2_in),
|
509 |
21 |
mihad |
.mask_addr (pci_addr_mask2_in),
|
510 |
|
|
.tran_addr (pci_tran_addr2_in),
|
511 |
|
|
.at_en (addr_tran_en2_in),
|
512 |
|
|
.mem_io_space (mem_io_addr_space2_in),
|
513 |
|
|
.mem_en (mem_enable_in),
|
514 |
2 |
mihad |
.io_en (io_enable_in)
|
515 |
|
|
) ;
|
516 |
|
|
`endif
|
517 |
|
|
`ifdef PCI_IMAGE3
|
518 |
77 |
mihad |
pci_pci_decoder #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder3
|
519 |
21 |
mihad |
(.hit (hit3_in),
|
520 |
|
|
.addr_out (address3_in),
|
521 |
|
|
.addr_in (address_in),
|
522 |
|
|
.bc_in (bc_in),
|
523 |
2 |
mihad |
.base_addr (pci_base_addr3_in),
|
524 |
21 |
mihad |
.mask_addr (pci_addr_mask3_in),
|
525 |
|
|
.tran_addr (pci_tran_addr3_in),
|
526 |
|
|
.at_en (addr_tran_en3_in),
|
527 |
|
|
.mem_io_space (mem_io_addr_space3_in),
|
528 |
|
|
.mem_en (mem_enable_in),
|
529 |
2 |
mihad |
.io_en (io_enable_in)
|
530 |
|
|
) ;
|
531 |
|
|
`endif
|
532 |
|
|
`ifdef PCI_IMAGE4
|
533 |
77 |
mihad |
pci_pci_decoder #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder4
|
534 |
21 |
mihad |
(.hit (hit4_in),
|
535 |
|
|
.addr_out (address4_in),
|
536 |
|
|
.addr_in (address_in),
|
537 |
|
|
.bc_in (bc_in),
|
538 |
2 |
mihad |
.base_addr (pci_base_addr4_in),
|
539 |
21 |
mihad |
.mask_addr (pci_addr_mask4_in),
|
540 |
|
|
.tran_addr (pci_tran_addr4_in),
|
541 |
|
|
.at_en (addr_tran_en4_in),
|
542 |
|
|
.mem_io_space (mem_io_addr_space4_in),
|
543 |
|
|
.mem_en (mem_enable_in),
|
544 |
2 |
mihad |
.io_en (io_enable_in)
|
545 |
|
|
) ;
|
546 |
|
|
`endif
|
547 |
|
|
`ifdef PCI_IMAGE5
|
548 |
77 |
mihad |
pci_pci_decoder #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder5
|
549 |
21 |
mihad |
(.hit (hit5_in),
|
550 |
|
|
.addr_out (address5_in),
|
551 |
|
|
.addr_in (address_in),
|
552 |
|
|
.bc_in (bc_in),
|
553 |
2 |
mihad |
.base_addr (pci_base_addr5_in),
|
554 |
21 |
mihad |
.mask_addr (pci_addr_mask5_in),
|
555 |
|
|
.tran_addr (pci_tran_addr5_in),
|
556 |
|
|
.at_en (addr_tran_en5_in),
|
557 |
|
|
.mem_io_space (mem_io_addr_space5_in),
|
558 |
|
|
.mem_en (mem_enable_in),
|
559 |
2 |
mihad |
.io_en (io_enable_in)
|
560 |
|
|
) ;
|
561 |
|
|
`endif
|
562 |
|
|
|
563 |
|
|
// Internal signals for image hit determination
|
564 |
|
|
reg addr_claim ;// address claim signal is asinchronous set for addr_claim_out signal to PCI Target SM
|
565 |
|
|
|
566 |
|
|
// Determining if image 0 is assigned to configuration space or as normal pci to wb access!
|
567 |
|
|
// if normal access is allowed to configuration space, then hit0 is hit0_conf
|
568 |
|
|
`ifdef HOST
|
569 |
21 |
mihad |
`ifdef NO_CNF_IMAGE
|
570 |
|
|
parameter hit0_conf = 1'b0 ;
|
571 |
2 |
mihad |
`else
|
572 |
21 |
mihad |
parameter hit0_conf = 1'b1 ; // if normal access is allowed to configuration space, then hit0 is hit0_conf
|
573 |
2 |
mihad |
`endif
|
574 |
21 |
mihad |
`else // GUEST
|
575 |
|
|
parameter hit0_conf = 1'b1 ; // if normal access is allowed to configuration space, then hit0 is hit0_conf
|
576 |
2 |
mihad |
`endif
|
577 |
|
|
|
578 |
|
|
// Logic with address mux, determining if address is still in the same image space and if it is prefetced or not
|
579 |
21 |
mihad |
always@(hit5_in or hit4_in or hit3_in or hit2_in or hit1_in or hit0_in or
|
580 |
|
|
address5_in or address4_in or address3_in or address2_in or address1_in or address0_in or
|
581 |
|
|
pre_fetch_en5 or
|
582 |
|
|
pre_fetch_en4 or
|
583 |
|
|
pre_fetch_en3 or
|
584 |
|
|
pre_fetch_en2 or
|
585 |
|
|
pre_fetch_en1 or
|
586 |
|
|
pre_fetch_en0
|
587 |
|
|
)
|
588 |
|
|
begin
|
589 |
|
|
addr_claim <= (hit5_in || hit4_in) || (hit3_in || hit2_in || hit1_in || hit0_in) ;
|
590 |
|
|
case ({hit5_in, hit4_in, hit3_in, hit2_in, hit0_in})
|
591 |
|
|
5'b10000 :
|
592 |
2 |
mihad |
begin
|
593 |
21 |
mihad |
address <= address5_in ;
|
594 |
|
|
pre_fetch_en <= pre_fetch_en5 ;
|
595 |
2 |
mihad |
end
|
596 |
21 |
mihad |
5'b01000 :
|
597 |
|
|
begin
|
598 |
|
|
address <= address4_in ;
|
599 |
|
|
pre_fetch_en <= pre_fetch_en4 ;
|
600 |
|
|
end
|
601 |
|
|
5'b00100 :
|
602 |
|
|
begin
|
603 |
|
|
address <= address3_in ;
|
604 |
|
|
pre_fetch_en <= pre_fetch_en3 ;
|
605 |
|
|
end
|
606 |
|
|
5'b00010 :
|
607 |
|
|
begin
|
608 |
|
|
address <= address2_in ;
|
609 |
|
|
pre_fetch_en <= pre_fetch_en2 ;
|
610 |
|
|
end
|
611 |
|
|
5'b00001 :
|
612 |
|
|
begin
|
613 |
|
|
address <= address0_in ;
|
614 |
|
|
pre_fetch_en <= pre_fetch_en0 ;
|
615 |
|
|
end
|
616 |
|
|
default : // IMAGE 1 is always included into PCI bridge
|
617 |
|
|
begin
|
618 |
|
|
address <= address1_in ;
|
619 |
|
|
pre_fetch_en <= pre_fetch_en1 ;
|
620 |
|
|
end
|
621 |
|
|
endcase
|
622 |
|
|
end
|
623 |
2 |
mihad |
|
624 |
|
|
// Address claim output to PCI Target SM
|
625 |
|
|
assign addr_claim_out = addr_claim ;
|
626 |
|
|
|
627 |
|
|
reg [31:0] norm_address ; // stored normal address (decoded and translated) for access to WB
|
628 |
|
|
reg norm_prf_en ; // stored pre-fetch enable
|
629 |
|
|
reg [3:0] norm_bc ; // stored bus-command
|
630 |
|
|
reg same_read_reg ; // stored SAME_READ information
|
631 |
21 |
mihad |
reg target_rd ; // delayed registered TRDY output equivalent signal
|
632 |
2 |
mihad |
|
633 |
|
|
always@(posedge clk_in or posedge reset_in)
|
634 |
|
|
begin
|
635 |
21 |
mihad |
if (reset_in)
|
636 |
2 |
mihad |
begin
|
637 |
21 |
mihad |
norm_address <= #`FF_DELAY 32'h0000_0000 ;
|
638 |
|
|
norm_prf_en <= #`FF_DELAY 1'b0 ;
|
639 |
|
|
norm_bc <= #`FF_DELAY 4'h0 ;
|
640 |
|
|
same_read_reg <= #`FF_DELAY 1'b0 ;
|
641 |
2 |
mihad |
end
|
642 |
|
|
else
|
643 |
|
|
begin
|
644 |
|
|
if (addr_phase_in)
|
645 |
|
|
begin
|
646 |
21 |
mihad |
norm_address <= #`FF_DELAY address ;
|
647 |
|
|
norm_prf_en <= #`FF_DELAY pre_fetch_en ;
|
648 |
|
|
norm_bc <= #`FF_DELAY bc_in ;
|
649 |
|
|
same_read_reg <= #`FF_DELAY same_read_out ;
|
650 |
2 |
mihad |
end
|
651 |
|
|
end
|
652 |
|
|
end
|
653 |
21 |
mihad |
|
654 |
|
|
`ifdef HOST
|
655 |
|
|
`ifdef NO_CNF_IMAGE
|
656 |
|
|
reg [1:0] strd_address ; // stored INPUT address for accessing Configuration space registers
|
657 |
|
|
`else
|
658 |
|
|
reg [11:0] strd_address ; // stored INPUT address for accessing Configuration space registers
|
659 |
|
|
`endif
|
660 |
|
|
`else
|
661 |
|
|
reg [11:0] strd_address ; // stored INPUT address for accessing Configuration space registers
|
662 |
|
|
`endif
|
663 |
2 |
mihad |
always@(posedge clk_in or posedge reset_in)
|
664 |
|
|
begin
|
665 |
21 |
mihad |
if (reset_in)
|
666 |
2 |
mihad |
begin
|
667 |
21 |
mihad |
strd_address <= #`FF_DELAY 0 ;
|
668 |
2 |
mihad |
end
|
669 |
|
|
else
|
670 |
|
|
begin
|
671 |
21 |
mihad |
if (addr_phase_in)
|
672 |
|
|
begin
|
673 |
|
|
`ifdef HOST
|
674 |
|
|
`ifdef NO_CNF_IMAGE
|
675 |
|
|
strd_address <= #`FF_DELAY address_in[1:0] ;
|
676 |
|
|
`else
|
677 |
|
|
strd_address <= #`FF_DELAY address_in[11:0] ;
|
678 |
|
|
`endif
|
679 |
|
|
`else
|
680 |
|
|
strd_address <= #`FF_DELAY address_in[11:0] ;
|
681 |
|
|
`endif
|
682 |
|
|
end
|
683 |
2 |
mihad |
end
|
684 |
|
|
end
|
685 |
|
|
|
686 |
21 |
mihad |
always@(posedge clk_in or posedge reset_in)
|
687 |
|
|
begin
|
688 |
|
|
if (reset_in)
|
689 |
|
|
begin
|
690 |
|
|
target_rd <= #`FF_DELAY 1'b0 ;
|
691 |
|
|
end
|
692 |
|
|
else
|
693 |
|
|
begin
|
694 |
|
|
if (same_read_reg && !bckp_trdy_in)
|
695 |
|
|
target_rd <= #`FF_DELAY 1'b1 ;// Signal indicates when target ready is deaserted on PCI bus
|
696 |
|
|
else if (same_read_reg && bckp_devsel_in && !bckp_stop_in)
|
697 |
|
|
target_rd <= #`FF_DELAY 1'b1 ;// Signal indicates when target ready is deaserted on PCI bus
|
698 |
26 |
mihad |
else if ((!same_read_reg) || (last_reg_in && target_rd))
|
699 |
21 |
mihad |
target_rd <= #`FF_DELAY 1'b0 ;// Signal indicates when target ready is deaserted on PCI bus
|
700 |
|
|
end
|
701 |
|
|
end
|
702 |
|
|
// '1' indicates asserted TRDY signal when same read operation is performed
|
703 |
|
|
wire target_rd_completed = target_rd ;
|
704 |
|
|
|
705 |
2 |
mihad |
reg same_read_request ;
|
706 |
|
|
|
707 |
21 |
mihad |
// When delayed read is completed on WB, addres and bc must be compered, if there is the same read request
|
708 |
2 |
mihad |
always@(address or strd_addr_in or bc_in or strd_bc_in)
|
709 |
|
|
begin
|
710 |
|
|
if ((address == strd_addr_in) & (bc_in == strd_bc_in))
|
711 |
|
|
same_read_request <= 1'b1 ;
|
712 |
|
|
else
|
713 |
|
|
same_read_request <= 1'b0 ;
|
714 |
|
|
end
|
715 |
|
|
|
716 |
|
|
assign same_read_out = (same_read_request) ; // && ~pcir_fifo_empty_in) ;
|
717 |
|
|
|
718 |
|
|
// Signals for byte enable checking
|
719 |
|
|
reg addr_burst_ok ;
|
720 |
|
|
reg io_be_ok ;
|
721 |
|
|
|
722 |
|
|
// Byte enable checking for IO, MEMORY and CONFIGURATION spaces - be_in is active low!
|
723 |
|
|
always@(strd_address or be_in)
|
724 |
|
|
begin
|
725 |
|
|
case (strd_address[1:0])
|
726 |
|
|
2'b11 :
|
727 |
|
|
begin
|
728 |
|
|
addr_burst_ok <= 1'b0 ;
|
729 |
|
|
io_be_ok <= (be_in[2] && be_in[1] && be_in[0]) ; // only be3 can be active
|
730 |
|
|
end
|
731 |
|
|
2'b10 :
|
732 |
|
|
begin
|
733 |
|
|
addr_burst_ok <= 1'b0 ;
|
734 |
|
|
io_be_ok <= (~be_in[2] && be_in[1] && be_in[0]) || (be_in[3] && be_in[2] && be_in[1] && be_in[0]) ;
|
735 |
|
|
end
|
736 |
|
|
2'b01 :
|
737 |
|
|
begin
|
738 |
|
|
addr_burst_ok <= 1'b0 ;
|
739 |
|
|
io_be_ok <= (~be_in[1] && be_in[0]) || (be_in[3] && be_in[2] && be_in[1] && be_in[0]) ;
|
740 |
|
|
end
|
741 |
|
|
default : // 2'b00
|
742 |
|
|
begin
|
743 |
|
|
addr_burst_ok <= 1'b1 ;
|
744 |
|
|
io_be_ok <= (~be_in[0]) || (be_in[3] && be_in[2] && be_in[1] && be_in[0]) ;
|
745 |
|
|
end
|
746 |
|
|
endcase
|
747 |
|
|
end
|
748 |
|
|
|
749 |
53 |
mihad |
wire calc_target_abort = (norm_bc[3:1] == `BC_IO_RW) ? !io_be_ok : 1'b0 ;
|
750 |
2 |
mihad |
|
751 |
21 |
mihad |
wire [3:0] pcir_fifo_control_input = pcir_fifo_empty_in ? 4'h0 : pcir_fifo_control_in ;
|
752 |
|
|
|
753 |
2 |
mihad |
// Medium registers for data and control busses from PCIR_FIFO
|
754 |
|
|
reg [31:0] pcir_fifo_data_reg ;
|
755 |
|
|
reg [3:0] pcir_fifo_ctrl_reg ;
|
756 |
|
|
|
757 |
|
|
always@(posedge clk_in or posedge reset_in)
|
758 |
|
|
begin
|
759 |
21 |
mihad |
if (reset_in)
|
760 |
2 |
mihad |
begin
|
761 |
21 |
mihad |
pcir_fifo_data_reg <= #`FF_DELAY 32'h0000_0000 ;
|
762 |
|
|
pcir_fifo_ctrl_reg <= #`FF_DELAY 4'h0 ;
|
763 |
2 |
mihad |
end
|
764 |
|
|
else
|
765 |
|
|
begin
|
766 |
|
|
if (load_medium_reg_in)
|
767 |
|
|
begin
|
768 |
21 |
mihad |
pcir_fifo_data_reg <= #`FF_DELAY pcir_fifo_data_in ;
|
769 |
|
|
pcir_fifo_ctrl_reg <= #`FF_DELAY pcir_fifo_control_input ;
|
770 |
2 |
mihad |
end
|
771 |
|
|
end
|
772 |
|
|
end
|
773 |
|
|
|
774 |
73 |
mihad |
// when disconnect is signalled, the next data written to fifo will be the last
|
775 |
|
|
// also when this happens, disconnect must stay asserted until last data is written to the fifo
|
776 |
|
|
reg next_write_to_pciw_fifo_is_last ;
|
777 |
|
|
|
778 |
2 |
mihad |
// selecting "fifo data" from medium registers or from PCIR_FIFO
|
779 |
21 |
mihad |
wire [31:0] pcir_fifo_data = (sel_fifo_mreg_in && !pcir_fifo_empty_in) ? pcir_fifo_data_in : pcir_fifo_data_reg ;
|
780 |
|
|
wire [3:0] pcir_fifo_ctrl = (sel_fifo_mreg_in && !pcir_fifo_empty_in) ? pcir_fifo_control_input : pcir_fifo_ctrl_reg ;
|
781 |
2 |
mihad |
|
782 |
|
|
// signal assignments to PCI Target FSM
|
783 |
21 |
mihad |
assign read_completed_out = req_comp_pending_in ; // completion pending input for requesting side of the bridge
|
784 |
2 |
mihad |
assign read_processing_out = req_req_pending_in ; // request pending input for requesting side
|
785 |
21 |
mihad |
// when '1', the bus command is IO command - not supported commands are checked in pci_decoder modules
|
786 |
|
|
wire io_memory_bus_command = !norm_bc[3] && !norm_bc[2] ;
|
787 |
2 |
mihad |
assign disconect_wo_data_out = (
|
788 |
21 |
mihad |
((/*pcir_fifo_ctrl[`LAST_CTRL_BIT] ||*/ pcir_fifo_empty_in || ~burst_ok_out/*addr_burst_ok*/ || io_memory_bus_command) &&
|
789 |
|
|
~bc0_in && ~frame_reg_in) ||
|
790 |
108 |
tadejm |
((pciw_fifo_full_in || pciw_fifo_almost_full_in || next_write_to_pciw_fifo_is_last || pciw_fifo_two_left_in ||
|
791 |
|
|
(pciw_fifo_three_left_in && pciw_fifo_wenable) || ~addr_burst_ok || io_memory_bus_command) &&
|
792 |
21 |
mihad |
bc0_in && ~frame_reg_in)
|
793 |
2 |
mihad |
) ;
|
794 |
21 |
mihad |
assign disconect_w_data_out = (
|
795 |
|
|
( burst_ok_out && !io_memory_bus_command && ~bc0_in ) ||
|
796 |
|
|
( addr_burst_ok && !io_memory_bus_command && bc0_in )
|
797 |
|
|
) ;
|
798 |
|
|
assign target_abort_out = ( ~addr_phase_in && calc_target_abort ) ;
|
799 |
2 |
mihad |
|
800 |
21 |
mihad |
`ifdef HOST
|
801 |
|
|
`ifdef NO_CNF_IMAGE
|
802 |
|
|
// signal assignments to PCI Target FSM
|
803 |
|
|
assign norm_access_to_config_out = 1'b0 ;
|
804 |
|
|
// control signal assignments to read request sinchronization module
|
805 |
|
|
assign done_out = (target_rd_completed && last_reg_in) ;
|
806 |
|
|
assign in_progress_out = (same_read_reg && ~bckp_trdy_in) ;
|
807 |
|
|
// signal used for PCIR_FIFO flush (with comp_flush_in signal)
|
808 |
|
|
wire pcir_fifo_flush = (target_rd_completed && last_reg_in && ~pcir_fifo_empty_in) ;
|
809 |
|
|
`else
|
810 |
|
|
// signal assignments to PCI Target FSM
|
811 |
|
|
assign norm_access_to_config_out = (hit0_in && hit0_conf) ;
|
812 |
|
|
// control signal assignments to read request sinchronization module
|
813 |
|
|
assign done_out = (~sel_conf_fifo_in && target_rd_completed && last_reg_in) ;
|
814 |
|
|
assign in_progress_out = (~sel_conf_fifo_in && same_read_reg && ~bckp_trdy_in) ;
|
815 |
|
|
// signal used for PCIR_FIFO flush (with comp_flush_in signal)
|
816 |
|
|
wire pcir_fifo_flush = (~sel_conf_fifo_in && target_rd_completed && last_reg_in && ~pcir_fifo_empty_in) ;
|
817 |
|
|
`endif
|
818 |
|
|
`else
|
819 |
|
|
// signal assignments to PCI Target FSM
|
820 |
|
|
assign norm_access_to_config_out = (hit0_in && hit0_conf) ;
|
821 |
|
|
// control signal assignments to read request sinchronization module
|
822 |
|
|
assign done_out = (~sel_conf_fifo_in && target_rd_completed && last_reg_in) ;
|
823 |
|
|
assign in_progress_out = (~sel_conf_fifo_in && same_read_reg && ~bckp_trdy_in) ;
|
824 |
|
|
// signal used for PCIR_FIFO flush (with comp_flush_in signal)
|
825 |
|
|
wire pcir_fifo_flush = (~sel_conf_fifo_in && target_rd_completed && last_reg_in && ~pcir_fifo_empty_in) ;
|
826 |
|
|
`endif
|
827 |
2 |
mihad |
|
828 |
|
|
// flush signal for PCIR_FIFO must be registered, since it asinchronously resets some status registers
|
829 |
21 |
mihad |
wire pcir_fifo_flush_reg ;
|
830 |
77 |
mihad |
pci_async_reset_flop async_reset_as_pcir_flush
|
831 |
21 |
mihad |
(
|
832 |
|
|
.data_in (comp_flush_in || pcir_fifo_flush),
|
833 |
|
|
.clk_in (clk_in),
|
834 |
|
|
.async_reset_data_out (pcir_fifo_flush_reg),
|
835 |
|
|
.reset_in (reset_in)
|
836 |
|
|
) ;
|
837 |
2 |
mihad |
|
838 |
73 |
mihad |
always@(posedge clk_in or posedge reset_in)
|
839 |
|
|
begin
|
840 |
|
|
if (reset_in)
|
841 |
|
|
next_write_to_pciw_fifo_is_last <= #1 1'b0 ;
|
842 |
108 |
tadejm |
else if (next_write_to_pciw_fifo_is_last && pciw_fifo_wenable)
|
843 |
73 |
mihad |
next_write_to_pciw_fifo_is_last <= #1 1'b0 ;
|
844 |
108 |
tadejm |
else if (pciw_fifo_wenable && disconect_wo_data_out)
|
845 |
73 |
mihad |
next_write_to_pciw_fifo_is_last <= #1 1'b1 ;
|
846 |
|
|
end
|
847 |
|
|
|
848 |
2 |
mihad |
// signal assignments from fifo to PCI Target FSM
|
849 |
|
|
assign wbw_fifo_empty_out = wbw_fifo_empty_in ;
|
850 |
21 |
mihad |
assign wbu_del_read_comp_pending_out = wbu_del_read_comp_pending_in ;
|
851 |
108 |
tadejm |
assign pciw_fifo_full_out = (pciw_fifo_full_in || pciw_fifo_almost_full_in || pciw_fifo_two_left_in || pciw_fifo_three_left_in) ;
|
852 |
21 |
mihad |
assign pcir_fifo_data_err_out = pcir_fifo_ctrl[`DATA_ERROR_CTRL_BIT] && !sel_conf_fifo_in ;
|
853 |
108 |
tadejm |
// signal assignments to PCIR FIFO fifo
|
854 |
2 |
mihad |
assign pcir_fifo_flush_out = pcir_fifo_flush_reg ;
|
855 |
21 |
mihad |
assign pcir_fifo_renable_out = fetch_pcir_fifo_in && !pcir_fifo_empty_in ;
|
856 |
2 |
mihad |
|
857 |
108 |
tadejm |
// signal assignments to PCIW FIFO
|
858 |
|
|
reg pciw_fifo_wenable_out;
|
859 |
|
|
assign pciw_fifo_wenable = load_to_pciw_fifo_in ;
|
860 |
|
|
reg [3:0] pciw_fifo_control_out;
|
861 |
|
|
reg [31:0] pciw_fifo_addr_data_out;
|
862 |
|
|
reg [3:0] pciw_fifo_cbe_out;
|
863 |
|
|
always@(posedge clk_in or posedge reset_in)
|
864 |
|
|
begin
|
865 |
|
|
if (reset_in)
|
866 |
|
|
begin
|
867 |
|
|
pciw_fifo_wenable_out = 1'b0;
|
868 |
|
|
pciw_fifo_control_out = 4'h0;
|
869 |
|
|
// data and address outputs assignments to PCIW_FIFO - correction of 2 LSBits
|
870 |
|
|
pciw_fifo_addr_data_out = 32'h0;
|
871 |
|
|
pciw_fifo_cbe_out = 4'h0;
|
872 |
|
|
end
|
873 |
|
|
else
|
874 |
|
|
begin
|
875 |
|
|
pciw_fifo_wenable_out = load_to_pciw_fifo_in ;
|
876 |
|
|
pciw_fifo_control_out[`ADDR_CTRL_BIT] = ~rdy_in ;
|
877 |
|
|
pciw_fifo_control_out[`BURST_BIT] = rdy_in ? ~frame_reg_in : 1'b0 ;
|
878 |
|
|
// if '1' then next burst BE is not equat to current one => burst will be chopped into single transfers
|
879 |
|
|
pciw_fifo_control_out[`DATA_ERROR_CTRL_BIT] = rdy_in && (next_be_in != be_in) && ~bckp_trdy_in; // valid comp.
|
880 |
|
|
pciw_fifo_control_out[`LAST_CTRL_BIT] = rdy_in && (next_write_to_pciw_fifo_is_last ||
|
881 |
|
|
last_reg_in || pciw_fifo_almost_full_in ||
|
882 |
|
|
~addr_burst_ok || io_memory_bus_command);
|
883 |
|
|
// data and address outputs assignments to PCIW_FIFO - correction of 2 LSBits
|
884 |
|
|
pciw_fifo_addr_data_out = rdy_in ? data_in : {norm_address[31:2],
|
885 |
|
|
norm_address[1] && io_memory_bus_command,
|
886 |
|
|
norm_address[0] && io_memory_bus_command} ;
|
887 |
|
|
pciw_fifo_cbe_out = rdy_in ? be_in : norm_bc ;
|
888 |
|
|
end
|
889 |
|
|
end
|
890 |
|
|
|
891 |
21 |
mihad |
`ifdef HOST
|
892 |
|
|
`ifdef NO_CNF_IMAGE
|
893 |
|
|
// data and address outputs assignments to PCI Target FSM
|
894 |
|
|
assign data_out = pcir_fifo_data ;
|
895 |
|
|
`else
|
896 |
|
|
// data and address outputs assignments to PCI Target FSM
|
897 |
|
|
assign data_out = sel_conf_fifo_in ? conf_data_in : pcir_fifo_data ;
|
898 |
|
|
`endif
|
899 |
|
|
`else
|
900 |
|
|
// data and address outputs assignments to PCI Target FSM
|
901 |
|
|
assign data_out = sel_conf_fifo_in ? conf_data_in : pcir_fifo_data ;
|
902 |
|
|
`endif
|
903 |
|
|
|
904 |
2 |
mihad |
// data and address outputs assignments to read request sinchronization module
|
905 |
|
|
assign req_out = req_in ;
|
906 |
21 |
mihad |
// this address is stored in delayed_sync module and is connected back as strd_addr_in
|
907 |
|
|
assign addr_out = norm_address[31:0] ; // correction of 2 LSBits is done in wb_master module, original address must be saved
|
908 |
2 |
mihad |
assign be_out = be_in ;
|
909 |
|
|
assign we_out = 1'b0 ;
|
910 |
|
|
assign bc_out = norm_bc ;
|
911 |
21 |
mihad |
// burst is OK for reads when there is ((MEM_READ_LN or MEM_READ_MUL) and AD[1:0]==2'b00) OR
|
912 |
|
|
// (MEM_READ and Prefetchable_IMAGE and AD[1:0]==2'b00)
|
913 |
|
|
assign burst_ok_out = (norm_bc[3] && addr_burst_ok) || (norm_bc[2] && norm_prf_en && addr_burst_ok) ;
|
914 |
2 |
mihad |
// data and address outputs assignments to Configuration space
|
915 |
21 |
mihad |
`ifdef HOST
|
916 |
|
|
`ifdef NO_CNF_IMAGE
|
917 |
|
|
assign conf_data_out = 32'h0 ;
|
918 |
|
|
assign conf_addr_out = 12'h0 ;
|
919 |
|
|
assign conf_be_out = 4'b0 ;
|
920 |
|
|
assign conf_we_out = 1'h0 ;
|
921 |
|
|
`else
|
922 |
|
|
assign conf_data_out = data_in ;
|
923 |
|
|
assign conf_addr_out = strd_address[11:0] ;
|
924 |
|
|
assign conf_be_out = be_in ;
|
925 |
|
|
assign conf_we_out = load_to_conf_in ;
|
926 |
|
|
`endif
|
927 |
|
|
`else
|
928 |
|
|
assign conf_data_out = data_in ;
|
929 |
|
|
assign conf_addr_out = strd_address[11:0] ;
|
930 |
|
|
assign conf_be_out = be_in ;
|
931 |
|
|
assign conf_we_out = load_to_conf_in ;
|
932 |
|
|
`endif
|
933 |
|
|
// NOT USED NOW, SONCE READ IS ASYNCHRONOUS
|
934 |
|
|
//assign conf_re_out = fetch_conf_in ;
|
935 |
|
|
assign conf_re_out = 1'b0 ;
|
936 |
2 |
mihad |
|
937 |
21 |
mihad |
endmodule
|