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[/] [pci/] [tags/] [rel_7/] [rtl/] [verilog/] [pci_target32_interface.v] - Blame information for rev 2

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1 2 mihad 
//////////////////////////////////////////////////////////////////////
2 
////                                                              ////
3 
////  File name: pci_target32_interface.v                         ////
4 
////                                                              ////
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////  This file is part of the "PCI bridge" project               ////
6 
////  http://www.opencores.org/cores/pci/                         ////
7 
////                                                              ////
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////  Author(s):                                                  ////
9 
////      - Tadej Markovic, tadej@opencores.org                   ////
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////                                                              ////
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////  All additional information is avaliable in the README.txt   ////
12 
////  file.                                                       ////
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////                                                              ////
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////                                                              ////
15 
//////////////////////////////////////////////////////////////////////
16 
////                                                              ////
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//// Copyright (C) 2000 Tadej Markovic, tadej@opencores.org       ////
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////                                                              ////
19 
//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
22 
//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
25 
//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
31 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
34 
//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
41 
//
42 
// CVS Revision History
43 
//
44 
// $Log: not supported by cvs2svn $
45 
//
46 
 
47 
`include "bus_commands.v"
48 
`include "constants.v"
49 
 
50 
module PCI_TARGET32_INTERFACE
51 
(
52 
    // system inputs
53 
    clk_in,
54 
    reset_in,
55 
 
56 
    // PCI Target side of INTERFACE
57 
    address_in,
58 
    addr_claim_out,
59 
    bc_in,
60 
    bc0_in,
61 
    data_in,
62 
    data_out,
63 
    be_in,
64 
    req_in,
65 
    rdy_in,
66 
    addr_phase_in,
67 
    bckp_trdy_in,
68 
    last_reg_in,
69 
    frame_reg_in,
70 
    fetch_pcir_fifo_in,
71 
    load_medium_reg_in,
72 
    sel_fifo_mreg_in,
73 
    sel_conf_fifo_in,
74 
    fetch_conf_in,
75 
    load_to_pciw_fifo_in,
76 
    load_to_conf_in,
77 
    same_read_out,
78 
 
79 
        norm_access_to_config_out,
80 
        read_completed_out,
81 
        read_processing_out,
82 
        target_abort_out,
83 
        disconect_wo_data_out,
84 
        pciw_fifo_full_out,
85 
        pcir_fifo_data_err_out,
86 
        wbw_fifo_empty_out,
87 
 
88 
        // Delayed synchronizacion module signals
89 
        req_out,
90 
    done_out,
91 
    in_progress_out,
92 
        req_req_pending_in,
93 
    req_comp_pending_in,
94 
        addr_out,
95 
    be_out,
96 
    we_out,
97 
    bc_out,
98 
    burst_out,
99 
        strd_addr_in,
100 
        strd_bc_in,
101 
    status_in,
102 
    comp_flush_in,
103 
 
104 
        // FIFO signals
105 
        pcir_fifo_renable_out,
106 
        pcir_fifo_data_in,
107 
        pcir_fifo_be_in,
108 
        pcir_fifo_control_in,
109 
        pcir_fifo_flush_out,
110 
        pcir_fifo_almost_empty_in,
111 
        pcir_fifo_empty_in,
112 
        pciw_fifo_wenable_out,
113 
        pciw_fifo_addr_data_out,
114 
        pciw_fifo_cbe_out,
115 
        pciw_fifo_control_out,
116 
        pciw_fifo_two_left_in,
117 
        pciw_fifo_almost_full_in,
118 
        pciw_fifo_full_in,
119 
        wbw_fifo_empty_in,
120 
 
121 
        // Configuration space signals
122 
        conf_hit_out,
123 
        conf_addr_out,
124 
        conf_data_out,
125 
        conf_data_in,
126 
        conf_be_out,
127 
        conf_we_out,
128 
        conf_re_out,
129 
        mem_enable_in,
130 
        io_enable_in,
131 
        mem_io_addr_space0_in,
132 
        mem_io_addr_space1_in,
133 
        mem_io_addr_space2_in,
134 
        mem_io_addr_space3_in,
135 
        mem_io_addr_space4_in,
136 
        mem_io_addr_space5_in,
137 
        pre_fetch_en0_in,
138 
        pre_fetch_en1_in,
139 
        pre_fetch_en2_in,
140 
        pre_fetch_en3_in,
141 
        pre_fetch_en4_in,
142 
        pre_fetch_en5_in,
143 
        pci_base_addr0_in,
144 
        pci_base_addr1_in,
145 
        pci_base_addr2_in,
146 
        pci_base_addr3_in,
147 
        pci_base_addr4_in,
148 
        pci_base_addr5_in,
149 
        pci_addr_mask0_in,
150 
        pci_addr_mask1_in,
151 
        pci_addr_mask2_in,
152 
        pci_addr_mask3_in,
153 
        pci_addr_mask4_in,
154 
        pci_addr_mask5_in,
155 
        pci_tran_addr0_in,
156 
        pci_tran_addr1_in,
157 
        pci_tran_addr2_in,
158 
        pci_tran_addr3_in,
159 
        pci_tran_addr4_in,
160 
        pci_tran_addr5_in,
161 
        addr_tran_en0_in,
162 
        addr_tran_en1_in,
163 
        addr_tran_en2_in,
164 
        addr_tran_en3_in,
165 
        addr_tran_en4_in,
166 
        addr_tran_en5_in
167 
) ;
168 
 
169 
/*==================================================================================================================
170 
System inputs.
171 
==================================================================================================================*/
172 
// PCI side clock and reset
173 
input   clk_in,
174 
        reset_in ;
175 
 
176 
 
177 
/*==================================================================================================================
178 
Side of the PCI Target state machine
179 
==================================================================================================================*/
180 
// Data, byte enables, bus commands and address ports
181 
input   [31:0]   address_in ;            // current request address input - registered
182 
output          addr_claim_out ;        // current request address claim output
183 
input   [3:0]   bc_in ;                          // current request bus command input - registered
184 
input                   bc0_in ;                        // current cycle RW signal
185 
output  [31:0]  data_out ;                       // for read operations - current dataphase data output
186 
input   [31:0]  data_in ;                        // for write operations - current request data input - registered
187 
input   [3:0]    be_in ;                         // current dataphase byte enable inputs - registered
188 
// Port connection control signals from PCI FSM
189 
input           req_in ;                // Read is requested to WB master from PCI side
190 
input           rdy_in ;                // DATA / ADDRESS selection from PCI side when read or write - registered
191 
input                   addr_phase_in ;         // Indicates address phase and also fast-back-to-back address phase - registered
192 
input                   bckp_trdy_in ;          // TRDY output (which is registered) equivalent
193 
input               last_reg_in ;               // Indicates last data phase - registered
194 
input                   frame_reg_in ;          // FRAME input signal - registered
195 
input               fetch_pcir_fifo_in ;// Read enable for PCIR_FIFO when when read is finishen on WB side
196 
input               load_medium_reg_in ;// Load data from PCIR_FIFO to medium register (first data must be prepared on time)
197 
input               sel_fifo_mreg_in ;  // Read data selection between PCIR_FIFO and medium register
198 
input               sel_conf_fifo_in ;  // Read data selection between Configuration registers and "FIFO"
199 
input               fetch_conf_in ;             // Read enable for configuration space registers
200 
input               load_to_pciw_fifo_in ;// Write enable to PCIW_FIFO
201 
input               load_to_conf_in ;   // Write enable to Configuration space registers
202 
 
203 
 
204 
/*==================================================================================================================
205 
Status outputs to PCI side (FSM)
206 
==================================================================================================================*/
207 
output                  same_read_out ;                         // Indicates the same read request (important when read is finished on WB side)
208 
output                  norm_access_to_config_out ;     // Indicates the access to Configuration space with MEMORY commands
209 
output                  read_completed_out ;            // Indicates that read request is completed on WB side
210 
output                  read_processing_out ;           // Indicates that read request is processing on WB side
211 
output                  target_abort_out ;                      // Indicates target abort termination
212 
output                  disconect_wo_data_out ;         // Indicates disconnect with OR without data termination
213 
output                  pciw_fifo_full_out ;            // Indicates that write PCIW_FIFO is full
214 
output                  pcir_fifo_data_err_out ;        // Indicates data error on current data read from PCIR_FIFO
215 
output                  wbw_fifo_empty_out ;            // Indicates that WB SLAVE has no data to be written to PCI bus
216 
 
217 
 
218 
/*==================================================================================================================
219 
Read request interface through Delayed sinchronization module to WB Master
220 
==================================================================================================================*/
221 
// request, completion, done and progress indicator outputs for delayed_sync module where they are synchronized
222 
output                  req_out,                // request qualifier - when 1 it indicates that valid data is provided on outputs
223 
                        done_out,               // done output - when 1 indicates that PCI Target has completed a cycle on its bus
224 
                        in_progress_out ;       // out progress indicator - indicates that current completion is in progress on
225 
                                                                        //   PCI Target side
226 
// pending indication inputs - PCI Target side must know about requests and completions
227 
input                   req_req_pending_in ;    // request pending input for PCI Target side
228 
input                   req_comp_pending_in ;   // completion pending input for PCI Target side - it indicates when completion
229 
                                                                                //   is ready for completing on PCI Target bus
230 
// various data outputs - PCI Target sets address, bus command, byte enables, write enable and burst
231 
output  [31:0]   addr_out ;   // address bus output
232 
output  [3:0]    be_out ;     // byte enable output
233 
output          we_out ;     // write enable output - read/write request indication 1 = write request / 0 = read request
234 
output  [3:0]    bc_out ;     // bus command output
235 
output                  burst_out ;  // pre-fetch enable & burst read - qualifies pre-fetch for access to current image space
236 
 
237 
// completion side signals encoded termination status - 0 = normal completion / 1 = error terminated completion
238 
input   [31:0]   strd_addr_in ;  // Stored requested read access address
239 
input   [3:0]    strd_bc_in ;    // Stored requested read access bus command
240 
input                   status_in ;     // Error status reported - NOT USED because FIFO control bits determin data error status
241 
input               comp_flush_in ;     // If completition counter (2^16 clk periods) has expired, PCIR_FIFO must flush data
242 
 
243 
 
244 
/*==================================================================================================================
245 
PCIR_PCIW_FIFO signals from pci side
246 
==================================================================================================================*/
247 
// PCIR_FIFO control signals used for fetching data from PCIR_FIFO
248 
output                  pcir_fifo_renable_out ;                 // read enable output to PCIR_FIFO
249 
input   [31:0]   pcir_fifo_data_in ;                             // data input from PCIR_FIFO
250 
input   [3:0]    pcir_fifo_be_in ;                               // byte enable input from PCIR_FIFO
251 
input   [3:0]    pcir_fifo_control_in ;                  // control signals input from PCIR_FIFO
252 
output                  pcir_fifo_flush_out ;                   // flush PCIR_FIFO
253 
input                   pcir_fifo_almost_empty_in ;             // almost empty indicator from PCIR_FIFO
254 
input                   pcir_fifo_empty_in ;                    // empty indicator
255 
 
256 
// PCIW_FIFO control signals used for sinking data into PCIW_FIFO and status monitoring
257 
output                  pciw_fifo_wenable_out ;         // write enable output to PCIW_FIFO
258 
output  [31:0]   pciw_fifo_addr_data_out ;       // address / data output signals to PCIW_FIFO
259 
output  [3:0]    pciw_fifo_cbe_out ;                     // command / byte enable signals to PCIW_FIFO
260 
output  [3:0]    pciw_fifo_control_out ;         // control signals to PCIW_FIFO
261 
input                   pciw_fifo_two_left_in ;         // two data spaces left in PCIW_FIFO
262 
input                   pciw_fifo_almost_full_in ;      // almost full indicator from PCIW_FIFO
263 
input                   pciw_fifo_full_in ;                     // full indicator from PCIW_FIFO
264 
 
265 
// WBW_FIFO empy control signal used when delayed read is complete in PCIR_FIFO
266 
input                   wbw_fifo_empty_in ;                     // empty indicator from WBW_FIFO
267 
 
268 
 
269 
/*==================================================================================================================
270 
Configuration space signals - from and to registers
271 
==================================================================================================================*/
272 
// BUS for reading and writing to configuration space registers
273 
output                  conf_hit_out ;  // like "chip select" for configuration space
274 
output  [11:0]   conf_addr_out ; // address to configuration space when there is access to it
275 
output  [31:0]   conf_data_out ; // data to configuration space - for writing to registers
276 
input   [31:0]   conf_data_in ;  // data from configuration space - for reading from registers
277 
output  [3:0]    conf_be_out ;   // byte enables used for correct writing to configuration space
278 
output                  conf_we_out ;   // write enable control signal - 1 for writing / 0 for nothing
279 
output                  conf_re_out ;   // read enable control signal - 1 for reading / 0 for nothing
280 
 
281 
// Inputs for image control registers
282 
input                   mem_enable_in ; // allowed access to memory mapped image
283 
input                   io_enable_in ;  // allowed access to io mapped image
284 
 
285 
// Inputs needed for determining if image is assigned to memory or io space with pre-fetch and address translation
286 
input                   mem_io_addr_space0_in ; // bit-0 in pci_base_addr0 register
287 
input                   mem_io_addr_space1_in ; // bit-0 in pci_base_addr1 register
288 
input                   mem_io_addr_space2_in ; // bit-0 in pci_base_addr2 register
289 
input                   mem_io_addr_space3_in ; // bit-0 in pci_base_addr3 register
290 
input                   mem_io_addr_space4_in ; // bit-0 in pci_base_addr4 register
291 
input                   mem_io_addr_space5_in ; // bit-0 in pci_base_addr5 register
292 
input                   pre_fetch_en0_in ;      // bit-1 in pci_image_ctr0 register
293 
input                   pre_fetch_en1_in ;      // bit-1 in pci_image_ctr1 register
294 
input                   pre_fetch_en2_in ;      // bit-1 in pci_image_ctr2 register
295 
input                   pre_fetch_en3_in ;      // bit-1 in pci_image_ctr3 register
296 
input                   pre_fetch_en4_in ;      // bit-1 in pci_image_ctr4 register
297 
input                   pre_fetch_en5_in ;      // bit-1 in pci_image_ctr5 register
298 
 
299 
// Input from image registers - register values needed for decoder to work properly
300 
input   [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)]    pci_base_addr0_in ;     // base address from base address register
301 
input   [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)]    pci_base_addr1_in ; // base address from base address register
302 
input   [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)]    pci_base_addr2_in ; // base address from base address register
303 
input   [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)]    pci_base_addr3_in ; // base address from base address register
304 
input   [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)]    pci_base_addr4_in ; // base address from base address register
305 
input   [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)]    pci_base_addr5_in ; // base address from base address register
306 
input   [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)]    pci_addr_mask0_in ; // masking of base address from address mask register
307 
input   [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)]    pci_addr_mask1_in ; // masking of base address from address mask register
308 
input   [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)]    pci_addr_mask2_in ; // masking of base address from address mask register
309 
input   [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)]    pci_addr_mask3_in ; // masking of base address from address mask register
310 
input   [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)]    pci_addr_mask4_in ; // masking of base address from address mask register
311 
input   [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)]    pci_addr_mask5_in ; // masking of base address from address mask register
312 
input   [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)]    pci_tran_addr0_in ; // translation address from address translation register
313 
input   [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)]    pci_tran_addr1_in ; // translation address from address translation register
314 
input   [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)]    pci_tran_addr2_in ; // translation address from address translation register
315 
input   [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)]    pci_tran_addr3_in ; // translation address from address translation register
316 
input   [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)]    pci_tran_addr4_in ; // translation address from address translation register
317 
input   [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)]    pci_tran_addr5_in ; // translation address from address translation register
318 
 
319 
input                   addr_tran_en0_in ;      // address translation enable bit
320 
input                   addr_tran_en1_in ;      // address translation enable bit
321 
input                   addr_tran_en2_in ;      // address translation enable bit
322 
input                   addr_tran_en3_in ;      // address translation enable bit
323 
input                   addr_tran_en4_in ;      // address translation enable bit
324 
input                   addr_tran_en5_in ;      // address translation enable bit
325 
 
326 
/*==================================================================================================================
327 
END of input / output PORT DEFINITONS !!!
328 
==================================================================================================================*/
329 
 
330 
// address output from address multiplexer
331 
reg             [31:0]   address ;
332 
// prefetch enable for access to selected image space
333 
reg                             pre_fetch_en ;
334 
 
335 
// Input addresses and image hits from address decoders - addresses are multiplexed to address
336 
wire                    hit0_in ;
337 
wire    [31:0]   address0_in ;
338 
wire                    hit1_in ;
339 
wire    [31:0]   address1_in ;
340 
`ifdef          PCI_IMAGE2
341 
wire                    hit2_in ;
342 
wire    [31:0]   address2_in ;
343 
`endif
344 
`ifdef          PCI_IMAGE3
345 
wire                    hit2_in ;
346 
wire    [31:0]   address2_in ;
347 
wire                    hit3_in ;
348 
wire    [31:0]   address3_in ;
349 
`endif
350 
`ifdef          PCI_IMAGE4
351 
wire                    hit2_in ;
352 
wire    [31:0]   address2_in ;
353 
wire                    hit3_in ;
354 
wire    [31:0]   address3_in ;
355 
wire                    hit4_in ;
356 
wire    [31:0]   address4_in ;
357 
`endif
358 
`ifdef          PCI_IMAGE5
359 
wire                    hit2_in ;
360 
wire    [31:0]   address2_in ;
361 
wire                    hit3_in ;
362 
wire    [31:0]   address3_in ;
363 
wire                    hit4_in ;
364 
wire    [31:0]   address4_in ;
365 
wire                    hit5_in ;
366 
wire    [31:0]   address5_in ;
367 
`endif
368 
`ifdef          PCI_IMAGE6
369 
wire                    hit2_in ;
370 
wire    [31:0]   address2_in ;
371 
wire                    hit3_in ;
372 
wire    [31:0]   address3_in ;
373 
wire                    hit4_in ;
374 
wire    [31:0]   address4_in ;
375 
wire                    hit5_in ;
376 
wire    [31:0]   address5_in ;
377 
`endif
378 
 
379 
// Include address decoders
380 
        PCI_DECODER   #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder0
381 
                                   (.hit                        (hit0_in),
382 
                                        .addr_out               (address0_in),
383 
                                        .addr_in                (address_in),
384 
                                        .base_addr              (pci_base_addr0_in),
385 
                                        .mask_addr              (pci_addr_mask0_in),
386 
                                        .tran_addr              (pci_tran_addr0_in),
387 
                                        .at_en                  (addr_tran_en0_in),
388 
                                        .mem_io_space   (mem_io_addr_space0_in),
389 
                                        .mem_en                 (mem_enable_in),
390 
                                        .io_en                  (io_enable_in)
391 
                                        ) ;
392 
        PCI_DECODER   #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder1
393 
                                   (.hit                        (hit1_in),
394 
                                        .addr_out               (address1_in),
395 
                                        .addr_in                (address_in),
396 
                                        .base_addr              (pci_base_addr1_in),
397 
                                        .mask_addr              (pci_addr_mask1_in),
398 
                                        .tran_addr              (pci_tran_addr1_in),
399 
                                        .at_en                  (addr_tran_en1_in),
400 
                                        .mem_io_space   (mem_io_addr_space1_in),
401 
                                        .mem_en                 (mem_enable_in),
402 
                                        .io_en                  (io_enable_in)
403 
                                        ) ;
404 
`ifdef          PCI_IMAGE2
405 
        PCI_DECODER   #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder2
406 
                                   (.hit                        (hit2_in),
407 
                                        .addr_out               (address2_in),
408 
                                        .addr_in                (address_in),
409 
                                        .base_addr              (pci_base_addr2_in),
410 
                                        .mask_addr              (pci_addr_mask2_in),
411 
                                        .tran_addr              (pci_tran_addr2_in),
412 
                                        .at_en                  (addr_tran_en2_in),
413 
                                        .mem_io_space   (mem_io_addr_space2_in),
414 
                                        .mem_en                 (mem_enable_in),
415 
                                        .io_en                  (io_enable_in)
416 
                                        ) ;
417 
`endif
418 
`ifdef          PCI_IMAGE3
419 
        PCI_DECODER   #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder2
420 
                                   (.hit                        (hit2_in),
421 
                                        .addr_out               (address2_in),
422 
                                        .addr_in                (address_in),
423 
                                        .base_addr              (pci_base_addr2_in),
424 
                                        .mask_addr              (pci_addr_mask2_in),
425 
                                        .tran_addr              (pci_tran_addr2_in),
426 
                                        .at_en                  (addr_tran_en2_in),
427 
                                        .mem_io_space   (mem_io_addr_space2_in),
428 
                                        .mem_en                 (mem_enable_in),
429 
                                        .io_en                  (io_enable_in)
430 
                                        ) ;
431 
        PCI_DECODER   #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder3
432 
                                   (.hit                        (hit3_in),
433 
                                        .addr_out               (address3_in),
434 
                                        .addr_in                (address_in),
435 
                                        .base_addr              (pci_base_addr3_in),
436 
                                        .mask_addr              (pci_addr_mask3_in),
437 
                                        .tran_addr              (pci_tran_addr3_in),
438 
                                        .at_en                  (addr_tran_en3_in),
439 
                                        .mem_io_space   (mem_io_addr_space3_in),
440 
                                        .mem_en                 (mem_enable_in),
441 
                                        .io_en                  (io_enable_in)
442 
                                        ) ;
443 
`endif
444 
`ifdef          PCI_IMAGE4
445 
        PCI_DECODER   #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder2
446 
                                   (.hit                        (hit2_in),
447 
                                        .addr_out               (address2_in),
448 
                                        .addr_in                (address_in),
449 
                                        .base_addr              (pci_base_addr2_in),
450 
                                        .mask_addr              (pci_addr_mask2_in),
451 
                                        .tran_addr              (pci_tran_addr2_in),
452 
                                        .at_en                  (addr_tran_en2_in),
453 
                                        .mem_io_space   (mem_io_addr_space2_in),
454 
                                        .mem_en                 (mem_enable_in),
455 
                                        .io_en                  (io_enable_in)
456 
                                        ) ;
457 
        PCI_DECODER   #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder3
458 
                                   (.hit                        (hit3_in),
459 
                                        .addr_out               (address3_in),
460 
                                        .addr_in                (address_in),
461 
                                        .base_addr              (pci_base_addr3_in),
462 
                                        .mask_addr              (pci_addr_mask3_in),
463 
                                        .tran_addr              (pci_tran_addr3_in),
464 
                                        .at_en                  (addr_tran_en3_in),
465 
                                        .mem_io_space   (mem_io_addr_space3_in),
466 
                                        .mem_en                 (mem_enable_in),
467 
                                        .io_en                  (io_enable_in)
468 
                                        ) ;
469 
        PCI_DECODER   #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder4
470 
                                   (.hit                        (hit4_in),
471 
                                        .addr_out               (address4_in),
472 
                                        .addr_in                (address_in),
473 
                                        .base_addr              (pci_base_addr4_in),
474 
                                        .mask_addr              (pci_addr_mask4_in),
475 
                                        .tran_addr              (pci_tran_addr4_in),
476 
                                        .at_en                  (addr_tran_en4_in),
477 
                                        .mem_io_space   (mem_io_addr_space4_in),
478 
                                        .mem_en                 (mem_enable_in),
479 
                                        .io_en                  (io_enable_in)
480 
                                        ) ;
481 
`endif
482 
`ifdef          PCI_IMAGE5
483 
        PCI_DECODER   #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder2
484 
                                   (.hit                        (hit2_in),
485 
                                        .addr_out               (address2_in),
486 
                                        .addr_in                (address_in),
487 
                                        .base_addr              (pci_base_addr2_in),
488 
                                        .mask_addr              (pci_addr_mask2_in),
489 
                                        .tran_addr              (pci_tran_addr2_in),
490 
                                        .at_en                  (addr_tran_en2_in),
491 
                                        .mem_io_space   (mem_io_addr_space2_in),
492 
                                        .mem_en                 (mem_enable_in),
493 
                                        .io_en                  (io_enable_in)
494 
                                        ) ;
495 
        PCI_DECODER   #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder3
496 
                                   (.hit                        (hit3_in),
497 
                                        .addr_out               (address3_in),
498 
                                        .addr_in                (address_in),
499 
                                        .base_addr              (pci_base_addr3_in),
500 
                                        .mask_addr              (pci_addr_mask3_in),
501 
                                        .tran_addr              (pci_tran_addr3_in),
502 
                                        .at_en                  (addr_tran_en3_in),
503 
                                        .mem_io_space   (mem_io_addr_space3_in),
504 
                                        .mem_en                 (mem_enable_in),
505 
                                        .io_en                  (io_enable_in)
506 
                                        ) ;
507 
        PCI_DECODER   #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder4
508 
                                   (.hit                        (hit4_in),
509 
                                        .addr_out               (address4_in),
510 
                                        .addr_in                (address_in),
511 
                                        .base_addr              (pci_base_addr4_in),
512 
                                        .mask_addr              (pci_addr_mask4_in),
513 
                                        .tran_addr              (pci_tran_addr4_in),
514 
                                        .at_en                  (addr_tran_en4_in),
515 
                                        .mem_io_space   (mem_io_addr_space4_in),
516 
                                        .mem_en                 (mem_enable_in),
517 
                                        .io_en                  (io_enable_in)
518 
                                        ) ;
519 
        PCI_DECODER   #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder5
520 
                                   (.hit                        (hit5_in),
521 
                                        .addr_out               (address5_in),
522 
                                        .addr_in                (address_in),
523 
                                        .base_addr              (pci_base_addr5_in),
524 
                                        .mask_addr              (pci_addr_mask5_in),
525 
                                        .tran_addr              (pci_tran_addr5_in),
526 
                                        .at_en                  (addr_tran_en5_in),
527 
                                        .mem_io_space   (mem_io_addr_space5_in),
528 
                                        .mem_en                 (mem_enable_in),
529 
                                        .io_en                  (io_enable_in)
530 
                                        ) ;
531 
`endif
532 
`ifdef          PCI_IMAGE6
533 
        PCI_DECODER   #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder2
534 
                                   (.hit                        (hit2_in),
535 
                                        .addr_out               (address2_in),
536 
                                        .addr_in                (address_in),
537 
                                        .base_addr              (pci_base_addr2_in),
538 
                                        .mask_addr              (pci_addr_mask2_in),
539 
                                        .tran_addr              (pci_tran_addr2_in),
540 
                                        .at_en                  (addr_tran_en2_in),
541 
                                        .mem_io_space   (mem_io_addr_space2_in),
542 
                                        .mem_en                 (mem_enable_in),
543 
                                        .io_en                  (io_enable_in)
544 
                                        ) ;
545 
        PCI_DECODER   #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder3
546 
                                   (.hit                        (hit3_in),
547 
                                        .addr_out               (address3_in),
548 
                                        .addr_in                (address_in),
549 
                                        .base_addr              (pci_base_addr3_in),
550 
                                        .mask_addr              (pci_addr_mask3_in),
551 
                                        .tran_addr              (pci_tran_addr3_in),
552 
                                        .at_en                  (addr_tran_en3_in),
553 
                                        .mem_io_space   (mem_io_addr_space3_in),
554 
                                        .mem_en                 (mem_enable_in),
555 
                                        .io_en                  (io_enable_in)
556 
                                        ) ;
557 
        PCI_DECODER   #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder4
558 
                                   (.hit                        (hit4_in),
559 
                                        .addr_out               (address4_in),
560 
                                        .addr_in                (address_in),
561 
                                        .base_addr              (pci_base_addr4_in),
562 
                                        .mask_addr              (pci_addr_mask4_in),
563 
                                        .tran_addr              (pci_tran_addr4_in),
564 
                                        .at_en                  (addr_tran_en4_in),
565 
                                        .mem_io_space   (mem_io_addr_space4_in),
566 
                                        .mem_en                 (mem_enable_in),
567 
                                        .io_en                  (io_enable_in)
568 
                                        ) ;
569 
        PCI_DECODER   #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder5
570 
                                   (.hit                        (hit5_in),
571 
                                        .addr_out               (address5_in),
572 
                                        .addr_in                (address_in),
573 
                                        .base_addr              (pci_base_addr5_in),
574 
                                        .mask_addr              (pci_addr_mask5_in),
575 
                                        .tran_addr              (pci_tran_addr5_in),
576 
                                        .at_en                  (addr_tran_en5_in),
577 
                                        .mem_io_space   (mem_io_addr_space5_in),
578 
                                        .mem_en                 (mem_enable_in),
579 
                                        .io_en                  (io_enable_in)
580 
                                        ) ;
581 
`endif
582 
 
583 
// Internal signals for image hit determination
584 
reg                             addr_claim ;// address claim signal is asinchronous set for addr_claim_out signal to PCI Target SM
585 
 
586 
// Determining if image 0 is assigned to configuration space or as normal pci to wb access!
587 
//   if normal access is allowed to configuration space, then hit0 is hit0_conf
588 
`ifdef          HOST
589 
        `ifdef  PCI_IMAGE6
590 
                parameter       hit0_conf = 1'b0 ;
591 
        `else
592 
                parameter       hit0_conf = 1'b1 ;      // if normal access is allowed to configuration space, then hit0 is hit0_conf
593 
        `endif
594 
`else
595 
                parameter       hit0_conf = 1'b1 ;      // if normal access is allowed to configuration space, then hit0 is hit0_conf
596 
`endif
597 
 
598 
// Logic with address mux, determining if address is still in the same image space and if it is prefetced or not
599 
`ifdef          PCI_IMAGE6
600 
        always@(hit5_in or     hit4_in or     hit3_in or     hit2_in or     hit1_in or     hit0_in or
601 
                        address5_in or address4_in or address3_in or address2_in or address1_in or address0_in or
602 
                        pre_fetch_en5_in or
603 
                        pre_fetch_en4_in or
604 
                        pre_fetch_en3_in or
605 
                        pre_fetch_en2_in or
606 
                        pre_fetch_en1_in or
607 
                        pre_fetch_en0_in
608 
                        )
609 
        begin
610 
                addr_claim <= (hit5_in || hit4_in || hit3_in || hit2_in) || (hit1_in || hit0_in) ;
611 
                case ({hit5_in, hit4_in, hit3_in, hit2_in, hit1_in, hit0_in})
612 
                6'b010000 :
613 
                begin
614 
                        address <= address4_in ;
615 
                        pre_fetch_en <= pre_fetch_en4_in ;
616 
                end
617 
                6'b001000 :
618 
                begin
619 
                        address <= address3_in ;
620 
                        pre_fetch_en <= pre_fetch_en3_in ;
621 
                end
622 
                6'b000100 :
623 
                begin
624 
                        address <= address2_in ;
625 
                        pre_fetch_en <= pre_fetch_en2_in ;
626 
                end
627 
                6'b000010 :
628 
                begin
629 
                        address <= address1_in ;
630 
                        pre_fetch_en <= pre_fetch_en1_in ;
631 
                end
632 
                6'b000001 :
633 
                begin
634 
                        address <= address0_in ;
635 
                        pre_fetch_en <= pre_fetch_en0_in ;
636 
                end
637 
                default :
638 
                begin
639 
                        address <= address5_in ;
640 
                        pre_fetch_en <= pre_fetch_en5_in ;
641 
                end
642 
                endcase
643 
        end
644 
`else
645 
        `ifdef          PCI_IMAGE5
646 
                always@(hit5_in or     hit4_in or     hit3_in or     hit2_in or     hit1_in or     hit0_in or
647 
                                address5_in or address4_in or address3_in or address2_in or address1_in or address0_in or
648 
                                pre_fetch_en5_in or
649 
                                pre_fetch_en4_in or
650 
                                pre_fetch_en3_in or
651 
                                pre_fetch_en2_in or
652 
                                pre_fetch_en1_in or
653 
                                pre_fetch_en0_in
654 
                                )
655 
                begin
656 
                        addr_claim <= (hit5_in || hit4_in || hit3_in || hit2_in) || (hit1_in || hit0_in) ;
657 
                        case ({hit5_in, hit4_in, hit3_in, hit2_in, hit1_in, hit0_in})
658 
                        6'b010000 :
659 
                        begin
660 
                                address <= address4_in ;
661 
                                pre_fetch_en <= pre_fetch_en4_in ;
662 
                        end
663 
                        6'b001000 :
664 
                        begin
665 
                                address <= address3_in ;
666 
                                pre_fetch_en <= pre_fetch_en3_in ;
667 
                        end
668 
                        6'b000100 :
669 
                        begin
670 
                                address <= address2_in ;
671 
                                pre_fetch_en <= pre_fetch_en2_in ;
672 
                        end
673 
                        6'b000010 :
674 
                        begin
675 
                                address <= address1_in ;
676 
                                pre_fetch_en <= pre_fetch_en1_in ;
677 
                        end
678 
                        6'b000001 :
679 
                        begin
680 
                                address <= address0_in ;
681 
                                pre_fetch_en <= pre_fetch_en0_in ;
682 
                        end
683 
                        default :
684 
                        begin
685 
                                address <= address5_in ;
686 
                                pre_fetch_en <= pre_fetch_en5_in ;
687 
                        end
688 
                        endcase
689 
                end
690 
        `else
691 
                `ifdef          PCI_IMAGE4
692 
                        always@(hit4_in or     hit3_in or     hit2_in or     hit1_in or     hit0_in or
693 
                                        address4_in or address3_in or address2_in or address1_in or address0_in or
694 
                                        pre_fetch_en4_in or
695 
                                        pre_fetch_en3_in or
696 
                                        pre_fetch_en2_in or
697 
                                        pre_fetch_en1_in or
698 
                                        pre_fetch_en0_in
699 
                                        )
700 
                        begin
701 
                                addr_claim <= hit4_in || (hit3_in || hit2_in || hit1_in || hit0_in) ;
702 
                                case ({hit4_in, hit3_in, hit2_in, hit1_in, hit0_in})
703 
                                5'b01000 :
704 
                                begin
705 
                                        address <= address3_in ;
706 
                                        pre_fetch_en <= pre_fetch_en3_in ;
707 
                                end
708 
                                5'b00100 :
709 
                                begin
710 
                                        address <= address2_in ;
711 
                                        pre_fetch_en <= pre_fetch_en2_in ;
712 
                                end
713 
                                5'b00010 :
714 
                                begin
715 
                                        address <= address1_in ;
716 
                                        pre_fetch_en <= pre_fetch_en1_in ;
717 
                                end
718 
                                5'b00001 :
719 
                                begin
720 
                                        address <= address0_in ;
721 
                                        pre_fetch_en <= pre_fetch_en0_in ;
722 
                                end
723 
                                default :
724 
                                begin
725 
                                        address <= address4_in ;
726 
                                        pre_fetch_en <= pre_fetch_en4_in ;
727 
                                end
728 
                                endcase
729 
                        end
730 
                `else
731 
                        `ifdef          PCI_IMAGE3
732 
                                always@(hit3_in or     hit2_in or     hit1_in or     hit0_in or
733 
                                                address3_in or address2_in or address1_in or address0_in or
734 
                                                pre_fetch_en3_in or
735 
                                                pre_fetch_en2_in or
736 
                                                pre_fetch_en1_in or
737 
                                                pre_fetch_en0_in
738 
                                                )
739 
                                begin
740 
                                        addr_claim <= (hit3_in || hit2_in || hit1_in || hit0_in) ;
741 
                                        case ({hit3_in, hit2_in, hit1_in, hit0_in})
742 
                                        4'b0100 :
743 
                                        begin
744 
                                                address <= address2_in ;
745 
                                                pre_fetch_en <= pre_fetch_en2_in ;
746 
                                        end
747 
                                        4'b0010 :
748 
                                        begin
749 
                                                address <= address1_in ;
750 
                                                pre_fetch_en <= pre_fetch_en1_in ;
751 
                                        end
752 
                                        4'b0001 :
753 
                                        begin
754 
                                                address <= address0_in ;
755 
                                                pre_fetch_en <= pre_fetch_en0_in ;
756 
                                        end
757 
                                        default :
758 
                                        begin
759 
                                                address <= address3_in ;
760 
                                                pre_fetch_en <= pre_fetch_en3_in ;
761 
                                        end
762 
                                        endcase
763 
                                end
764 
                        `else
765 
                                `ifdef          PCI_IMAGE2
766 
                                        always@(hit2_in or     hit1_in or     hit0_in or
767 
                                                        address2_in or address1_in or address0_in or
768 
                                                        pre_fetch_en2_in or
769 
                                                        pre_fetch_en1_in or
770 
                                                        pre_fetch_en0_in
771 
                                                        )
772 
                                        begin
773 
                                                addr_claim <= (hit2_in || hit1_in || hit0_in) ;
774 
                                                case ({hit2_in, hit1_in, hit0_in})
775 
                                                3'b010 :
776 
                                                begin
777 
                                                        address <= address1_in ;
778 
                                                        pre_fetch_en <= pre_fetch_en1_in ;
779 
                                                end
780 
                                                3'b001 :
781 
                                                begin
782 
                                                        address <= address0_in ;
783 
                                                        pre_fetch_en <= pre_fetch_en0_in ;
784 
                                                end
785 
                                                default :
786 
                                                begin
787 
                                                        address <= address2_in ;
788 
                                                        pre_fetch_en <= pre_fetch_en2_in ;
789 
                                                end
790 
                                                endcase
791 
                                        end
792 
                                `else
793 
                                        always@(hit1_in or     hit0_in or
794 
                                                        address1_in or address0_in or
795 
                                                        pre_fetch_en1_in or
796 
                                                        pre_fetch_en0_in
797 
                                                        )
798 
                                        begin
799 
                                                addr_claim <= (hit1_in || hit0_in) ;
800 
                                                case ({hit1_in, hit0_in})
801 
                                                2'b01 :
802 
                                                begin
803 
                                                        address <= address0_in ;
804 
                                                        pre_fetch_en <= pre_fetch_en0_in ;
805 
                                                end
806 
                                                default :
807 
                                                begin
808 
                                                        address <= address1_in ;
809 
                                                        pre_fetch_en <= pre_fetch_en1_in ;
810 
                                                end
811 
                                                endcase
812 
                                        end
813 
                                `endif
814 
                        `endif
815 
                `endif
816 
        `endif
817 
`endif
818 
 
819 
// Address claim output to PCI Target SM
820 
assign  addr_claim_out = addr_claim ;
821 
 
822 
reg             [11:0]   strd_address ;          // stored INPUT address for accessing Configuration space registers
823 
reg             [31:0]   norm_address ;          // stored normal address (decoded and translated) for access to WB
824 
reg                             norm_prf_en ;           // stored pre-fetch enable
825 
reg             [3:0]    norm_bc ;                       // stored bus-command
826 
reg                             same_read_reg ;         // stored SAME_READ information
827 
reg                             bckp_trdy_reg ;         // delayed registered TRDY output equivalent signal
828 
reg                             trdy_asserted_reg ;     // delayed bckp_trdy_reg signal
829 
 
830 
always@(posedge clk_in or posedge reset_in)
831 
begin
832 
    if (reset_in)
833 
        begin
834 
                strd_address <= 12'h000 ;
835 
                norm_address <= 32'h0000_0000 ;
836 
                norm_prf_en <= 1'b0 ;
837 
                norm_bc <= 4'h0 ;
838 
                same_read_reg <= 1'b0 ;
839 
        end
840 
        else
841 
        begin
842 
                if (addr_phase_in)
843 
                begin
844 
                        strd_address <= address_in[11:0] ;
845 
                        norm_address <= address ;
846 
                        norm_prf_en <= pre_fetch_en ;
847 
                        norm_bc <= bc_in ;
848 
                        same_read_reg <= same_read_out ;
849 
                end
850 
        end
851 
end
852 
always@(posedge clk_in or posedge reset_in)
853 
begin
854 
    if (reset_in)
855 
        begin
856 
                bckp_trdy_reg <= 1'b0 ;
857 
                trdy_asserted_reg <= 1'b0 ;
858 
        end
859 
        else
860 
        begin
861 
                bckp_trdy_reg <= bckp_trdy_in ;
862 
                trdy_asserted_reg <= bckp_trdy_reg ;
863 
        end
864 
end
865 
// Signal indicates when target ready is deaserted on PCI bus
866 
wire    trdy_asserted = trdy_asserted_reg && bckp_trdy_reg ;
867 
 
868 
reg                             same_read_request ;
869 
 
870 
// When delayed read is completed on WB, addres and bc must be compered, if there is the same read request
871 
always@(address or strd_addr_in or bc_in or strd_bc_in)
872 
begin
873 
        if ((address == strd_addr_in) & (bc_in == strd_bc_in))
874 
                same_read_request <= 1'b1 ;
875 
        else
876 
                same_read_request <= 1'b0 ;
877 
end
878 
 
879 
assign  same_read_out = (same_read_request) ; // && ~pcir_fifo_empty_in) ;
880 
 
881 
// Signals for byte enable checking
882 
reg                             addr_burst_ok ;
883 
reg                             io_be_ok ;
884 
reg                             conf_be_ok ;
885 
 
886 
// Byte enable checking for IO, MEMORY and CONFIGURATION spaces - be_in is active low!
887 
always@(strd_address or be_in)
888 
begin
889 
        case (strd_address[1:0])
890 
        2'b11 :
891 
        begin
892 
                addr_burst_ok <= 1'b0 ;
893 
                io_be_ok <= (be_in[2] && be_in[1] && be_in[0]) ; // only be3 can be active
894 
                conf_be_ok <= 1'b0 ;
895 
        end
896 
        2'b10 :
897 
        begin
898 
                addr_burst_ok <= 1'b0 ;
899 
                io_be_ok <= (~be_in[2] && be_in[1] && be_in[0]) || (be_in[3] && be_in[2] && be_in[1] && be_in[0]) ;
900 
                conf_be_ok <= 1'b0 ;
901 
        end
902 
        2'b01 :
903 
        begin
904 
                addr_burst_ok <= 1'b0 ;
905 
                io_be_ok <= (~be_in[1] && be_in[0]) || (be_in[3] && be_in[2] && be_in[1] && be_in[0]) ;
906 
                conf_be_ok <= 1'b0 ;
907 
        end
908 
        default :       // 2'b00
909 
        begin
910 
                addr_burst_ok <= 1'b1 ;
911 
                io_be_ok <= (~be_in[0]) || (be_in[3] && be_in[2] && be_in[1] && be_in[0]) ;
912 
                conf_be_ok <= 1'b1 ;
913 
        end
914 
        endcase
915 
end
916 
 
917 
reg                             calc_target_abort ;
918 
// Target abort indication regarding the registered bus command and current signals for byte enable checking
919 
always@(bc_in or hit0_in or io_be_ok or conf_be_ok)
920 
begin
921 
        case (bc_in)
922 
        // READ COMMANDS
923 
        `BC_IO_READ :
924 
        begin
925 
                case ({hit0_in, hit0_conf})
926 
                2'b11 :
927 
                begin
928 
                        calc_target_abort <= 1'b1 ;
929 
                end
930 
                default :
931 
                begin
932 
                        if (io_be_ok)
933 
                        begin
934 
                                calc_target_abort <= 1'b0 ;
935 
                        end
936 
                        else
937 
                        begin
938 
                                calc_target_abort <= 1'b1 ;
939 
                        end
940 
                end
941 
                endcase
942 
        end
943 
        `BC_MEM_READ :
944 
        begin
945 
                case ({hit0_in, hit0_conf})
946 
                2'b11 :
947 
                begin
948 
                        calc_target_abort <= 1'b0 ;
949 
                end
950 
                default :
951 
                begin
952 
                        calc_target_abort <= 1'b0 ;
953 
                end
954 
                endcase
955 
        end
956 
        `BC_CONF_READ :
957 
        begin
958 
                case (conf_be_ok)
959 
                1'b1 :
960 
                begin
961 
                        calc_target_abort <= 1'b0 ;
962 
                end
963 
                default :
964 
                begin
965 
                        calc_target_abort <= 1'b1 ;
966 
                end
967 
                endcase
968 
        end
969 
        `BC_MEM_READ_LN,
970 
        `BC_MEM_READ_MUL :
971 
        begin
972 
                case ({hit0_in, hit0_conf})
973 
                2'b11 :
974 
                begin
975 
                        calc_target_abort <= 1'b1 ;
976 
                end
977 
                default :
978 
                begin
979 
                        calc_target_abort <= 1'b0 ;
980 
                end
981 
                endcase
982 
        end
983 
        // WRITE COMMANDS
984 
        `BC_IO_WRITE :
985 
        begin
986 
                case ({hit0_in, hit0_conf})
987 
                2'b11 :
988 
                begin
989 
                        calc_target_abort <= 1'b1 ;
990 
                end
991 
                default :
992 
                begin
993 
                        if (io_be_ok)
994 
                        begin
995 
                                calc_target_abort <= 1'b0 ;
996 
                        end
997 
                        else
998 
                        begin
999 
                                calc_target_abort <= 1'b1 ;
1000 
                        end
1001 
                end
1002 
                endcase
1003 
        end
1004 
        `BC_MEM_WRITE :
1005 
        begin
1006 
                case ({hit0_in, hit0_conf})
1007 
                2'b11 :
1008 
                begin
1009 
                        calc_target_abort <= 1'b0 ;
1010 
                end
1011 
                default :
1012 
                begin
1013 
                        calc_target_abort <= 1'b0 ;
1014 
                end
1015 
                endcase
1016 
        end
1017 
        `BC_CONF_WRITE :
1018 
        begin
1019 
                case (conf_be_ok)
1020 
                1'b1 :
1021 
                begin
1022 
                        calc_target_abort <= 1'b0 ;
1023 
                end
1024 
                default :
1025 
                begin
1026 
                        calc_target_abort <= 1'b1 ;
1027 
                end
1028 
                endcase
1029 
        end
1030 
        `BC_MEM_WRITE_INVAL :
1031 
        begin
1032 
                case ({hit0_in, hit0_conf})
1033 
                2'b11 :
1034 
                begin
1035 
                        calc_target_abort <= 1'b1 ;
1036 
                end
1037 
                default :
1038 
                begin
1039 
                        calc_target_abort <= 1'b0 ;
1040 
                end
1041 
                endcase
1042 
        end
1043 
        default :
1044 
        begin
1045 
                calc_target_abort <= 1'b0 ;
1046 
        end
1047 
        endcase
1048 
end
1049 
 
1050 
// Medium registers for data and control busses from PCIR_FIFO
1051 
reg             [31:0]   pcir_fifo_data_reg ;
1052 
reg             [3:0]    pcir_fifo_ctrl_reg ;
1053 
 
1054 
always@(posedge clk_in or posedge reset_in)
1055 
begin
1056 
    if (reset_in)
1057 
    begin
1058 
        pcir_fifo_data_reg <= 32'h0000_0000 ;
1059 
        pcir_fifo_ctrl_reg <=  4'h0 ;
1060 
    end
1061 
    else
1062 
    begin
1063 
        if (load_medium_reg_in)
1064 
        begin
1065 
                pcir_fifo_data_reg <= pcir_fifo_data_in ;
1066 
                pcir_fifo_ctrl_reg <= pcir_fifo_control_in ;
1067 
        end
1068 
    end
1069 
end
1070 
 
1071 
// selecting "fifo data" from medium registers or from PCIR_FIFO
1072 
wire [31:0]      pcir_fifo_data = sel_fifo_mreg_in ? pcir_fifo_data_in : pcir_fifo_data_reg ;
1073 
wire [3:0]       pcir_fifo_ctrl = sel_fifo_mreg_in ? pcir_fifo_control_in : pcir_fifo_ctrl_reg ;
1074 
 
1075 
// signal assignments to PCI Target FSM
1076 
assign  norm_access_to_config_out = (hit0_in && hit0_conf) ;
1077 
assign  read_completed_out = req_comp_pending_in ; // completion pending input for requesting side of the bridge
1078 
assign  read_processing_out = req_req_pending_in ; // request pending input for requesting side
1079 
assign  disconect_wo_data_out = (
1080 
        ((pcir_fifo_ctrl[`LAST_CTRL_BIT] || pcir_fifo_empty_in || ~addr_burst_ok) && ~bc0_in && ~frame_reg_in) ||
1081 
        ((pciw_fifo_full_in || pciw_fifo_almost_full_in || pciw_fifo_two_left_in || ~addr_burst_ok) && bc0_in && ~frame_reg_in)
1082 
                                                                ) ;
1083 
assign  target_abort_out = (addr_phase_in && calc_target_abort) ;
1084 
 
1085 
// control signal assignments to read request sinchronization module
1086 
assign  done_out = (~sel_conf_fifo_in && same_read_reg && ~trdy_asserted && last_reg_in) ;
1087 
assign  in_progress_out = (~sel_conf_fifo_in && same_read_reg && ~bckp_trdy_in) ;
1088 
 
1089 
// signal used for PCIR_FIFO flush (with comp_flush_in signal)
1090 
wire    pcir_fifo_flush = (~sel_conf_fifo_in && same_read_reg && ~trdy_asserted && last_reg_in && ~pcir_fifo_empty_in) ;
1091 
// flush signal for PCIR_FIFO must be registered, since it asinchronously resets some status registers
1092 
reg             pcir_fifo_flush_reg ;
1093 
always@(posedge clk_in or posedge reset_in)
1094 
begin
1095 
    if (reset_in)
1096 
    begin
1097 
        pcir_fifo_flush_reg <=  1'b0 ;
1098 
    end
1099 
    else
1100 
    begin
1101 
        pcir_fifo_flush_reg <= comp_flush_in || pcir_fifo_flush ;
1102 
    end
1103 
end
1104 
 
1105 
// signal assignments from fifo to PCI Target FSM
1106 
assign  wbw_fifo_empty_out = wbw_fifo_empty_in ;
1107 
assign  pciw_fifo_full_out = (pciw_fifo_full_in || pciw_fifo_almost_full_in || pciw_fifo_two_left_in) ;
1108 
assign  pcir_fifo_data_err_out = pcir_fifo_ctrl[`DATA_ERROR_CTRL_BIT] ;
1109 
// signal assignments to fifo
1110 
assign  pcir_fifo_flush_out                                                     = pcir_fifo_flush_reg ;
1111 
assign  pcir_fifo_renable_out                                           = fetch_pcir_fifo_in ;
1112 
assign  pciw_fifo_wenable_out                                           = load_to_pciw_fifo_in ;
1113 
assign  pciw_fifo_control_out[`ADDR_CTRL_BIT]           = 1'b0 ;
1114 
assign  pciw_fifo_control_out[`BURST_BIT]                       = rdy_in ? 1'b0 : ~frame_reg_in ;
1115 
assign  pciw_fifo_control_out[`DATA_ERROR_CTRL_BIT]     = 1'b0 ;
1116 
assign  pciw_fifo_control_out[`LAST_CTRL_BIT]           = rdy_in ? (last_reg_in || pciw_fifo_almost_full_in) : 1'b0 ;
1117 
 
1118 
// data and address outputs assignments to PCI Target FSM
1119 
assign  data_out = sel_conf_fifo_in ? conf_data_in : pcir_fifo_data ;
1120 
// data and address outputs assignments to read request sinchronization module
1121 
assign  req_out = req_in ;
1122 
assign  addr_out = norm_address ;
1123 
assign  be_out = be_in ;
1124 
assign  we_out = 1'b0 ;
1125 
assign  bc_out = norm_bc ;
1126 
assign  burst_out = ~frame_reg_in && norm_prf_en ;
1127 
// data and address outputs assignments to PCIW_FIFO
1128 
assign  pciw_fifo_addr_data_out = rdy_in ? data_in : norm_address ;
1129 
assign  pciw_fifo_cbe_out = rdy_in ? be_in : norm_bc ;
1130 
// data and address outputs assignments to Configuration space
1131 
assign  conf_data_out = data_in ;
1132 
assign  conf_addr_out = strd_address[11:0] ;
1133 
assign  conf_be_out = be_in ;
1134 
assign  conf_we_out = load_to_conf_in ;
1135 
assign  conf_re_out = fetch_conf_in ;
1136 
 
1137 
 
1138 
endmodule

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