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[/] [pci/] [tags/] [rel_8/] [apps/] [crt/] [rtl/] [verilog/] [crtc_iob.v] - Blame information for rev 154

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module CRTC_IOB
(
    reset_in,
    clk_in,
    hsync_in,
    vsync_in,
    rgb_in,
    hsync_out,
    vsync_out,
    rgb_out
) ;
 
input   reset_in,
        clk_in ;
 
input   hsync_in,
        vsync_in ;
 
input   [15:4]  rgb_in ;
 
output          hsync_out,
                vsync_out ;
output  [15:4]  rgb_out ;
 
reg             hsync_out,
                vsync_out ;
 
reg     [15:4]  rgb_out ;
 
always@(posedge clk_in or posedge reset_in)
begin
    if ( reset_in )
    begin
        hsync_out <= #1 1'b0 ;
        vsync_out <= #1 1'b0 ;
        rgb_out   <= #1 12'h000 ;
    end
    else
    begin
        hsync_out <= #1 hsync_in ;
        vsync_out <= #1 vsync_in ;
        rgb_out   <= #1 rgb_in ;
    end
end
endmodule

Line No.	Rev	Author	Line
1	14	mihad	`module CRTC_IOB`
2			`(`
3			`reset_in,`
4			`clk_in,`
5			`hsync_in,`
6			`vsync_in,`
7			`rgb_in,`
8			`hsync_out,`
9			`vsync_out,`
10			`rgb_out`
11			`) ;`
12
13			`input reset_in,`
14			`clk_in ;`
15
16			`input hsync_in,`
17			`vsync_in ;`
18
19			`input [15:4] rgb_in ;`
20
21			`output hsync_out,`
22			`vsync_out ;`
23			`output [15:4] rgb_out ;`
24
25			`reg hsync_out,`
26			`vsync_out ;`
27
28			`reg [15:4] rgb_out ;`
29
30			`always@(posedge clk_in or posedge reset_in)`
31			`begin`
32			`if ( reset_in )`
33			`begin`
34			`hsync_out <= #1 1'b0 ;`
35			`vsync_out <= #1 1'b0 ;`
36			`rgb_out <= #1 12'h000 ;`
37			`end`
38			`else`
39			`begin`
40			`hsync_out <= #1 hsync_in ;`
41			`vsync_out <= #1 vsync_in ;`
42			`rgb_out <= #1 rgb_in ;`
43			`end`
44			`end`
45			`endmodule`

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[/] [pci/] [tags/] [rel_8/] [apps/] [crt/] [rtl/] [verilog/] [crtc_iob.v] - Blame information for rev 154