URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_8/] [apps/] [crt/] [rtl/] [verilog/] [ssvga_crtc.v] - Blame information for rev 2

Go to most recent revision | Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Simple Small VGA IP Core                                    ////
////                                                              ////
////  This file is part of the Simple Small VGA project           ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Hsync/Vsync generator.                                      ////
////                                                              ////
////  To Do:                                                      ////
////   Nothing                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
`include "ssvga_defines.v"
 
module ssvga_crtc(
        crt_clk, rst, hsync, vsync, hblank, vblank
);
 
//
// I/O ports
//
input                           crt_clk;// Pixel Clock
input                           rst;    // Reset
output                          hsync;  // H sync
output                          vsync;  // V sync
output                          hblank; // H blank
output                          vblank; // V blank
 
//
// Internal wires and regs
//
reg     [`SSVGA_HCW-1:0] hcntr;  // Horizontal counter
reg     [`SSVGA_VCW-1:0] vcntr;  // Vertical counter
reg                             hsync;  // Horizontal sync
reg                             vsync;  // Vertical sync
 
// flip - flops for decoding end of one line
reg line_end1 ;
reg line_end2 ;
 
always@(posedge crt_clk or posedge rst)
begin
    if (rst)
    begin
        line_end1 <= #1 1'b0 ;
        line_end2 <= #1 1'b0 ;
    end
    else
    begin
        line_end1 <= #1 hsync ;
        line_end2 <= #1 line_end1 ;
    end
end
 
wire line_end = ~line_end2 && line_end1 ;
 
//
// Assert hblank when hsync is not asserted
//
reg hblank ;
always@(posedge crt_clk or posedge rst)
begin
    if (rst)
        hblank <= #1 1'b0 ;
    else
    if ( hcntr == (`SSVGA_HPULSE + `SSVGA_HBACKP) )
        hblank <= #1 1'b0 ;
    else
    if ( hcntr == (`SSVGA_HTOT - `SSVGA_HFRONTP) )
        hblank <= #1 1'b1 ;
end
 
reg vblank ;
always@(posedge crt_clk or posedge rst)
begin
    if ( rst )
        vblank <= #1 1'b0 ;
    else
    if ((vcntr == (`SSVGA_VPULSE + `SSVGA_VBACKP)) && line_end)
        vblank <= #1 1'b0 ;
    else
    if ((vcntr == (`SSVGA_VTOT - `SSVGA_VFRONTP)) && line_end)
        vblank <= #1 1'b1 ;
end
 
//
// Horizontal counter
//
always @(posedge crt_clk or posedge rst)
                if (rst)
                        hcntr <= #1 `SSVGA_HCW'h0;
                else if (hcntr == `SSVGA_HTOT - 1)
                        hcntr <= #1 `SSVGA_HCW'h0;
                else
                        hcntr <= #1 hcntr + 1;
//
// Horizontal sync
//
always @(posedge crt_clk or posedge rst)
                if (rst)
                        hsync <= #1 1'b0;
                else if (hcntr == `SSVGA_HCW'h0)
                        hsync <= #1 1'b1;
                else if (hcntr == `SSVGA_HPULSE)
                        hsync <= #1 1'b0 ;
 
//
// Vertical counter
//
always @(posedge crt_clk or posedge rst)
                if (rst)
                        vcntr <= #1 `SSVGA_VCW'h0;
                else if ((vcntr == `SSVGA_VTOT - 1) && line_end)
                        vcntr <= #1 `SSVGA_VCW'h0;
                else if ( line_end )
                        vcntr <= #1 vcntr + 1;
//
// Vertical sync
//
always @(posedge crt_clk or posedge rst)
                if (rst)
                        vsync <= #1 1'b0;
                else if ((vcntr == `SSVGA_VCW'd0) && line_end)
                        vsync <= #1 1'b1;
                else if ((vcntr == `SSVGA_VPULSE) && line_end)
                        vsync <= #1 1'b0;
endmodule

Line No.	Rev	Author	Line
1	2	mihad	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Simple Small VGA IP Core ////`
4			`//// ////`
5			`//// This file is part of the Simple Small VGA project ////`
6			`//// ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Hsync/Vsync generator. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// Nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`//`
48
49			`// synopsys translate_off`
50			`include "timescale.v"
51			`// synopsys translate_on`
52
53			`include "ssvga_defines.v"
54
55			`module ssvga_crtc(`
56			`crt_clk, rst, hsync, vsync, hblank, vblank`
57			`);`
58
59			`//`
60			`// I/O ports`
61			`//`
62			`input crt_clk;// Pixel Clock`
63			`input rst; // Reset`
64			`output hsync; // H sync`
65			`output vsync; // V sync`
66			`output hblank; // H blank`
67			`output vblank; // V blank`
68
69			`//`
70			`// Internal wires and regs`
71			`//`
72			reg [`SSVGA_HCW-1:0] hcntr; // Horizontal counter
73			reg [`SSVGA_VCW-1:0] vcntr; // Vertical counter
74			`reg hsync; // Horizontal sync`
75			`reg vsync; // Vertical sync`
76
77			`// flip - flops for decoding end of one line`
78			`reg line_end1 ;`
79			`reg line_end2 ;`
80
81			`always@(posedge crt_clk or posedge rst)`
82			`begin`
83			`if (rst)`
84			`begin`
85			`line_end1 <= #1 1'b0 ;`
86			`line_end2 <= #1 1'b0 ;`
87			`end`
88			`else`
89			`begin`
90			`line_end1 <= #1 hsync ;`
91			`line_end2 <= #1 line_end1 ;`
92			`end`
93			`end`
94
95			`wire line_end = ~line_end2 && line_end1 ;`
96
97			`//`
98			`// Assert hblank when hsync is not asserted`
99			`//`
100			`reg hblank ;`
101			`always@(posedge crt_clk or posedge rst)`
102			`begin`
103			`if (rst)`
104			`hblank <= #1 1'b0 ;`
105			`else`
106			if ( hcntr == (`SSVGA_HPULSE + `SSVGA_HBACKP) )
107			`hblank <= #1 1'b0 ;`
108			`else`
109			if ( hcntr == (`SSVGA_HTOT - `SSVGA_HFRONTP) )
110			`hblank <= #1 1'b1 ;`
111			`end`
112
113			`reg vblank ;`
114			`always@(posedge crt_clk or posedge rst)`
115			`begin`
116			`if ( rst )`
117			`vblank <= #1 1'b0 ;`
118			`else`
119			if ((vcntr == (`SSVGA_VPULSE + `SSVGA_VBACKP)) && line_end)
120			`vblank <= #1 1'b0 ;`
121			`else`
122			if ((vcntr == (`SSVGA_VTOT - `SSVGA_VFRONTP)) && line_end)
123			`vblank <= #1 1'b1 ;`
124			`end`
125
126			`//`
127			`// Horizontal counter`
128			`//`
129			`always @(posedge crt_clk or posedge rst)`
130			`if (rst)`
131			hcntr <= #1 `SSVGA_HCW'h0;
132			else if (hcntr == `SSVGA_HTOT - 1)
133			hcntr <= #1 `SSVGA_HCW'h0;
134			`else`
135			`hcntr <= #1 hcntr + 1;`
136			`//`
137			`// Horizontal sync`
138			`//`
139			`always @(posedge crt_clk or posedge rst)`
140			`if (rst)`
141			`hsync <= #1 1'b0;`
142			else if (hcntr == `SSVGA_HCW'h0)
143			`hsync <= #1 1'b1;`
144			else if (hcntr == `SSVGA_HPULSE)
145			`hsync <= #1 1'b0 ;`
146
147			`//`
148			`// Vertical counter`
149			`//`
150			`always @(posedge crt_clk or posedge rst)`
151			`if (rst)`
152			vcntr <= #1 `SSVGA_VCW'h0;
153			else if ((vcntr == `SSVGA_VTOT - 1) && line_end)
154			vcntr <= #1 `SSVGA_VCW'h0;
155			`else if ( line_end )`
156			`vcntr <= #1 vcntr + 1;`
157			`//`
158			`// Vertical sync`
159			`//`
160			`always @(posedge crt_clk or posedge rst)`
161			`if (rst)`
162			`vsync <= #1 1'b0;`
163			else if ((vcntr == `SSVGA_VCW'd0) && line_end)
164			`vsync <= #1 1'b1;`
165			else if ((vcntr == `SSVGA_VPULSE) && line_end)
166			`vsync <= #1 1'b0;`
167			`endmodule`

Browse

Tools

Subversion Repositories pci

[/] [pci/] [tags/] [rel_8/] [apps/] [crt/] [rtl/] [verilog/] [ssvga_crtc.v] - Blame information for rev 2