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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Simple Small VGA IP Core                                    ////
////                                                              ////
////  This file is part of the Simple Small VGA project           ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  LITTLE-ENDIAN WISHBONE master interface.                    ////
////                                                              ////
////  To Do:                                                      ////
////   Nothing                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2  2002/02/01 15:24:46  mihad
// Repaired a few bugs, updated specification, added test bench files and design document
//
// Revision 1.1.1.1  2001/10/02 15:33:33  mihad
// New project directory structure
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "ssvga_defines.v"
 
module ssvga_wbm_if(
        // Clock and reset
        wb_clk_i, wb_rst_i,
 
        // WISHBONE Master I/F
        wbm_cyc_o, wbm_stb_o, wbm_sel_o, wbm_we_o,
        wbm_adr_o, wbm_dat_o, wbm_cab_o,
        wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
 
        // Other signals
        ssvga_en, fifo_full,
        fifo_wr_en, fifo_dat,
    pix_start_addr, resync
);
 
//
// I/O ports
//
 
//
// Clock and reset
//
input                   wb_clk_i;       // Pixel Clock
input                   wb_rst_i;       // Reset
 
//
// WISHBONE Master I/F
//
output                  wbm_cyc_o;
output                  wbm_stb_o;
output  [3:0]            wbm_sel_o;
output                  wbm_we_o;
output  [31:0]           wbm_adr_o;
output  [31:0]           wbm_dat_o;
output                  wbm_cab_o;
input   [31:0]           wbm_dat_i;
input                   wbm_ack_i;
input                   wbm_err_i;
input                   wbm_rty_i;
 
//
// Other signals
//
input                   ssvga_en;       // Global enable
input                   fifo_full;      // FIFO is full
output                  fifo_wr_en;     // FIFO write enable
output  [31:0]           fifo_dat;       // FIFO data
input   [31:2]  pix_start_addr ;
input           resync ;    // when pixel buffer underrun occures, master must resynchronize operation to start of screen
 
//
// Internal regs and wires
//
reg     [`SSVGA_VMCW-1:0] vmaddr_r;      // Video memory address counter
//reg   [31:0]          shift_r;        // Shift register
//reg   [1:0]           shift_empty_r;  // Shift register empty flags
 
// frame finished indicator - whenever video memory address shows 640x480 pixels read
reg  frame_read ;
wire frame_read_in = ( vmaddr_r == `SSVGA_VMCW'h0_00_00 ) & wbm_ack_i & wbm_stb_o || ~ssvga_en || resync ;
 
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if (wb_rst_i)
        frame_read <= #1 1'b0 ;
    else
        frame_read <= #1 frame_read_in ;
end
 
//
// Video memory address generation
//
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                vmaddr_r <= #1 ((`PIXEL_NUM/4)-1) ;
        else if (frame_read)
                vmaddr_r <= #1 ((`PIXEL_NUM/4)-1);
        else if (wbm_ack_i & wbm_stb_o)
                vmaddr_r <= #1 vmaddr_r - 1;
 
reg [31:2] wbm_adr ;
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
    if (wb_rst_i)
                wbm_adr <= #1 30'h0000_0000 ;
    else if (frame_read)
        wbm_adr <= #1 pix_start_addr ;
    else if (wbm_ack_i & wbm_stb_o)
        wbm_adr <= #1 wbm_adr + 1 ;
end
 
//
// Shift register
//
/*always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                shift_r <= #1 32'h0000_0000;
        else if (wbm_ack_i & wbm_cyc_o)
                shift_r <= #1 wbm_dat_i;
        else if (!fifo_full)
                shift_r <= #1 {16'h00, shift_r[31:16]};
 
//
// Shift register empty flags
//
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                shift_empty_r <= #1 2'b11 ;
        else if (wbm_ack_i & wbm_cyc_o)
                shift_empty_r <= #1 2'b00;
        else if (!fifo_full)
                shift_empty_r <= #1 {1'b1, shift_empty_r[1]};
*/
//
// Generate WISHBONE output signals
//
assign wbm_cyc_o = ssvga_en & !frame_read ;
assign wbm_stb_o = wbm_cyc_o & !fifo_full;
assign wbm_sel_o = 4'b1111;
assign wbm_we_o = 1'b0;
assign wbm_adr_o = {wbm_adr, 2'b00};
assign wbm_dat_o = 32'h0000_0000;
assign wbm_cab_o = 1'b1;
 
//
// Generate other signals
//
assign fifo_wr_en = wbm_ack_i & wbm_stb_o ;
assign fifo_dat = wbm_dat_i ;
 
endmodule

Line No.	Rev	Author	Line
1	2	mihad	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Simple Small VGA IP Core ////`
4			`//// ////`
5			`//// This file is part of the Simple Small VGA project ////`
6			`//// ////`
7			`//// ////`
8			`//// Description ////`
9			`//// LITTLE-ENDIAN WISHBONE master interface. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// Nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	75	mihad	`// Revision 1.2 2002/02/01 15:24:46 mihad`
48			`// Repaired a few bugs, updated specification, added test bench files and design document`
49			`//`
50	21	mihad	`// Revision 1.1.1.1 2001/10/02 15:33:33 mihad`
51			`// New project directory structure`
52	2	mihad	`//`
53	21	mihad	`//`
54	2	mihad
55			`// synopsys translate_off`
56			`include "timescale.v"
57	75	mihad	`// synopsys translate_on`
58	2	mihad	`include "ssvga_defines.v"
59
60			`module ssvga_wbm_if(`
61			`// Clock and reset`
62			`wb_clk_i, wb_rst_i,`
63	21	mihad
64	2	mihad	`// WISHBONE Master I/F`
65			`wbm_cyc_o, wbm_stb_o, wbm_sel_o, wbm_we_o,`
66			`wbm_adr_o, wbm_dat_o, wbm_cab_o,`
67			`wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,`
68
69			`// Other signals`
70			`ssvga_en, fifo_full,`
71			`fifo_wr_en, fifo_dat,`
72			`pix_start_addr, resync`
73			`);`
74
75			`//`
76			`// I/O ports`
77			`//`
78
79			`//`
80			`// Clock and reset`
81			`//`
82			`input wb_clk_i; // Pixel Clock`
83			`input wb_rst_i; // Reset`
84
85			`//`
86			`// WISHBONE Master I/F`
87			`//`
88			`output wbm_cyc_o;`
89			`output wbm_stb_o;`
90			`output [3:0] wbm_sel_o;`
91			`output wbm_we_o;`
92			`output [31:0] wbm_adr_o;`
93			`output [31:0] wbm_dat_o;`
94			`output wbm_cab_o;`
95			`input [31:0] wbm_dat_i;`
96			`input wbm_ack_i;`
97			`input wbm_err_i;`
98			`input wbm_rty_i;`
99
100			`//`
101			`// Other signals`
102			`//`
103			`input ssvga_en; // Global enable`
104			`input fifo_full; // FIFO is full`
105			`output fifo_wr_en; // FIFO write enable`
106			`output [31:0] fifo_dat; // FIFO data`
107			`input [31:2] pix_start_addr ;`
108			`input resync ; // when pixel buffer underrun occures, master must resynchronize operation to start of screen`
109
110			`//`
111			`// Internal regs and wires`
112			`//`
113			reg [`SSVGA_VMCW-1:0] vmaddr_r; // Video memory address counter
114			`//reg [31:0] shift_r; // Shift register`
115			`//reg [1:0] shift_empty_r; // Shift register empty flags`
116
117			`// frame finished indicator - whenever video memory address shows 640x480 pixels read`
118			`reg frame_read ;`
119			wire frame_read_in = ( vmaddr_r == `SSVGA_VMCW'h0_00_00 ) & wbm_ack_i & wbm_stb_o \|\| ~ssvga_en \|\| resync ;
120
121			`always@(posedge wb_clk_i or posedge wb_rst_i)`
122			`begin`
123			`if (wb_rst_i)`
124			`frame_read <= #1 1'b0 ;`
125			`else`
126			`frame_read <= #1 frame_read_in ;`
127			`end`
128
129			`//`
130			`// Video memory address generation`
131			`//`
132			`always @(posedge wb_clk_i or posedge wb_rst_i)`
133			`if (wb_rst_i)`
134			vmaddr_r <= #1 ((`PIXEL_NUM/4)-1) ;
135			`else if (frame_read)`
136			vmaddr_r <= #1 ((`PIXEL_NUM/4)-1);
137			`else if (wbm_ack_i & wbm_stb_o)`
138			`vmaddr_r <= #1 vmaddr_r - 1;`
139
140			`reg [31:2] wbm_adr ;`
141			`always@(posedge wb_clk_i or posedge wb_rst_i)`
142			`begin`
143			`if (wb_rst_i)`
144			`wbm_adr <= #1 30'h0000_0000 ;`
145			`else if (frame_read)`
146			`wbm_adr <= #1 pix_start_addr ;`
147			`else if (wbm_ack_i & wbm_stb_o)`
148			`wbm_adr <= #1 wbm_adr + 1 ;`
149			`end`
150
151			`//`
152			`// Shift register`
153			`//`
154			`/*always @(posedge wb_clk_i or posedge wb_rst_i)`
155			`if (wb_rst_i)`
156			`shift_r <= #1 32'h0000_0000;`
157			`else if (wbm_ack_i & wbm_cyc_o)`
158			`shift_r <= #1 wbm_dat_i;`
159			`else if (!fifo_full)`
160			`shift_r <= #1 {16'h00, shift_r[31:16]};`
161
162			`//`
163			`// Shift register empty flags`
164			`//`
165			`always @(posedge wb_clk_i or posedge wb_rst_i)`
166			`if (wb_rst_i)`
167			`shift_empty_r <= #1 2'b11 ;`
168			`else if (wbm_ack_i & wbm_cyc_o)`
169			`shift_empty_r <= #1 2'b00;`
170			`else if (!fifo_full)`
171			`shift_empty_r <= #1 {1'b1, shift_empty_r[1]};`
172			`*/`
173			`//`
174			`// Generate WISHBONE output signals`
175			`//`
176			`assign wbm_cyc_o = ssvga_en & !frame_read ;`
177			`assign wbm_stb_o = wbm_cyc_o & !fifo_full;`
178			`assign wbm_sel_o = 4'b1111;`
179			`assign wbm_we_o = 1'b0;`
180			`assign wbm_adr_o = {wbm_adr, 2'b00};`
181			`assign wbm_dat_o = 32'h0000_0000;`
182			`assign wbm_cab_o = 1'b1;`
183
184			`//`
185			`// Generate other signals`
186			`//`
187			`assign fifo_wr_en = wbm_ack_i & wbm_stb_o ;`
188			`assign fifo_dat = wbm_dat_i ;`
189
190			`endmodule`

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[/] [pci/] [tags/] [rel_8/] [apps/] [crt/] [rtl/] [verilog/] [ssvga_wbm_if.v] - Blame information for rev 75