1 |
29 |
tadej |
ngdbuild -p xc2s150-5-pq208 -uc pci_crt.ucf -dd .. f:\mihad\fpga_t~1\pci_crt\pci_crt.edf pci_crt.ngd
|
2 |
|
|
Release 3.3.08i - ngdbuild D.27
|
3 |
|
|
Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved.
|
4 |
|
|
|
5 |
|
|
Command Line: ngdbuild -p xc2s150-5-pq208 -uc pci_crt.ucf -dd ..
|
6 |
|
|
f:\mihad\fpga_t~1\pci_crt\pci_crt.edf pci_crt.ngd
|
7 |
|
|
|
8 |
|
|
Launcher: Executing edif2ngd "f:\mihad\fpga_t~1\pci_crt\pci_crt.edf"
|
9 |
|
|
"F:\mihad\fpga_t~1\pci_crt\xproj\ver2\pci_crt.ngo"
|
10 |
|
|
Release 3.3.08i - edif2ngd D.27
|
11 |
|
|
Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved.
|
12 |
|
|
Writing the design to "F:/mihad/fpga_t~1/pci_crt/xproj/ver2/pci_crt.ngo"...
|
13 |
|
|
Reading NGO file "F:/mihad/fpga_t~1/pci_crt/xproj/ver2/pci_crt.ngo" ...
|
14 |
|
|
Reading component libraries for design expansion...
|
15 |
|
|
|
16 |
|
|
Annotating constraints to design from file "pci_crt.ucf" ...
|
17 |
|
|
|
18 |
|
|
Checking timing specifications ...
|
19 |
|
|
|
20 |
|
|
Checking expanded design ...
|
21 |
|
|
WARNING:NgdBuild:526 - On the RAMB4_S16_S16 symbol "CRT/ssvga_pallete", the
|
22 |
|
|
following properties are undefined: INIT_00, INIT_01, INIT_02, INIT_03,
|
23 |
|
|
INIT_04, INIT_05, INIT_06, INIT_07, INIT_08, INIT_09, INIT_0A, INIT_0B,
|
24 |
|
|
INIT_0C, INIT_0D, INIT_0E, INIT_0F. A default value of all zeroes will be
|
25 |
|
|
used.
|
26 |
|
|
WARNING:NgdBuild:526 - On the RAMB4_S8_S16 symbol "CRT/ssvga_fifo/ramb4_s8_1",
|
27 |
|
|
the following properties are undefined: INIT_00, INIT_01, INIT_02, INIT_03,
|
28 |
|
|
INIT_04, INIT_05, INIT_06, INIT_07, INIT_08, INIT_09, INIT_0A, INIT_0B,
|
29 |
|
|
INIT_0C, INIT_0D, INIT_0E, INIT_0F. A default value of all zeroes will be
|
30 |
|
|
used.
|
31 |
|
|
WARNING:NgdBuild:526 - On the RAMB4_S8_S16 symbol "CRT/ssvga_fifo/ramb4_s8_0",
|
32 |
|
|
the following properties are undefined: INIT_00, INIT_01, INIT_02, INIT_03,
|
33 |
|
|
INIT_04, INIT_05, INIT_06, INIT_07, INIT_08, INIT_09, INIT_0A, INIT_0B,
|
34 |
|
|
INIT_0C, INIT_0D, INIT_0E, INIT_0F. A default value of all zeroes will be
|
35 |
|
|
used.
|
36 |
|
|
WARNING:NgdBuild:526 - On the RAMB4_S16_S16 symbol
|
37 |
|
|
"bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_0", the
|
38 |
|
|
following properties are undefined: INIT_00, INIT_01, INIT_02, INIT_03,
|
39 |
|
|
INIT_04, INIT_05, INIT_06, INIT_07, INIT_08, INIT_09, INIT_0A, INIT_0B,
|
40 |
|
|
INIT_0C, INIT_0D, INIT_0E, INIT_0F. A default value of all zeroes will be
|
41 |
|
|
used.
|
42 |
|
|
WARNING:NgdBuild:526 - On the RAMB4_S16_S16 symbol
|
43 |
|
|
"bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_1", the
|
44 |
|
|
following properties are undefined: INIT_00, INIT_01, INIT_02, INIT_03,
|
45 |
|
|
INIT_04, INIT_05, INIT_06, INIT_07, INIT_08, INIT_09, INIT_0A, INIT_0B,
|
46 |
|
|
INIT_0C, INIT_0D, INIT_0E, INIT_0F. A default value of all zeroes will be
|
47 |
|
|
used.
|
48 |
|
|
WARNING:NgdBuild:526 - On the RAMB4_S16_S16 symbol
|
49 |
|
|
"bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2", the
|
50 |
|
|
following properties are undefined: INIT_00, INIT_01, INIT_02, INIT_03,
|
51 |
|
|
INIT_04, INIT_05, INIT_06, INIT_07, INIT_08, INIT_09, INIT_0A, INIT_0B,
|
52 |
|
|
INIT_0C, INIT_0D, INIT_0E, INIT_0F. A default value of all zeroes will be
|
53 |
|
|
used.
|
54 |
|
|
|
55 |
|
|
NGDBUILD Design Results Summary:
|
56 |
|
|
Number of errors: 0
|
57 |
|
|
Number of warnings: 6
|
58 |
|
|
|
59 |
|
|
Writing NGD file "pci_crt.ngd" ...
|
60 |
|
|
|
61 |
|
|
Writing NGDBUILD log file "pci_crt.bld"...
|
62 |
|
|
|
63 |
|
|
NGDBUILD done.
|
64 |
|
|
|
65 |
|
|
==================================================
|
66 |
|
|
|
67 |
|
|
map -p xc2s150-5-pq208 -o map.ncd -pr b pci_crt.ngd pci_crt.pcf
|
68 |
|
|
Release 3.3.08i - Map D.27
|
69 |
|
|
Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved.
|
70 |
|
|
Using target part "2s150pq208-5".
|
71 |
|
|
Reading NGD file "pci_crt.ngd"...
|
72 |
|
|
Processing FMAPs...
|
73 |
|
|
Removing unused or disabled logic...
|
74 |
|
|
Running cover...
|
75 |
|
|
Writing file map.ngm...
|
76 |
|
|
Running directed packing...
|
77 |
|
|
Running delay-based packing...
|
78 |
|
|
Running related packing...
|
79 |
|
|
Writing design file "map.ncd"...
|
80 |
|
|
|
81 |
|
|
Design Summary:
|
82 |
|
|
Number of errors: 0
|
83 |
|
|
Number of warnings: 72
|
84 |
|
|
Number of Slices: 1,402 out of 1,728 81%
|
85 |
|
|
Number of Slices containing
|
86 |
|
|
unrelated logic: 0 out of 1,402 0%
|
87 |
|
|
Number of Slice Flip Flops: 1,135 out of 3,456 32%
|
88 |
|
|
Total Number 4 input LUTs: 1,863 out of 3,456 53%
|
89 |
|
|
Number used as LUTs: 1,720
|
90 |
|
|
Number used as a route-thru: 1
|
91 |
|
|
Number used for Dual Port RAMs: 142
|
92 |
|
|
(Two LUTs used per Dual Port RAM)
|
93 |
|
|
Number of bonded IOBs: 64 out of 140 45%
|
94 |
|
|
IOB Flip Flops: 147
|
95 |
|
|
Number of Block RAMs: 6 out of 12 50%
|
96 |
|
|
Number of GCLKs: 2 out of 4 50%
|
97 |
|
|
Number of GCLKIOBs: 2 out of 4 50%
|
98 |
|
|
Total equivalent gate count for design: 129,333
|
99 |
|
|
Additional JTAG gate count for IOBs: 3,168
|
100 |
|
|
|
101 |
|
|
Removed Logic Summary:
|
102 |
|
|
11 block(s) removed
|
103 |
|
|
121 block(s) optimized away
|
104 |
|
|
1 signal(s) removed
|
105 |
|
|
|
106 |
|
|
Mapping completed.
|
107 |
|
|
See MAP report file "map.mrp" for details.
|
108 |
|
|
|
109 |
|
|
==================================================
|
110 |
|
|
|
111 |
|
|
par -w -ol 2 map.ncd pci_crt.ncd pci_crt.pcf
|
112 |
|
|
Release 3.3.08i - Par D.27
|
113 |
|
|
Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved.
|
114 |
|
|
|
115 |
|
|
|
116 |
|
|
|
117 |
|
|
|
118 |
|
|
Constraints file: pci_crt.pcf
|
119 |
|
|
|
120 |
|
|
Loading design for application par from file map.ncd.
|
121 |
|
|
"TOP" is an NCD, version 2.35, device xc2s150, package pq208, speed -5
|
122 |
|
|
Loading device for application par from file 'v150.nph' in environment
|
123 |
|
|
C:/Foundation.
|
124 |
|
|
Device speed data version: PRELIMINARY 1.21 2001-04-09.
|
125 |
|
|
|
126 |
|
|
|
127 |
|
|
Resolving physical constraints.
|
128 |
|
|
Finished resolving physical constraints.
|
129 |
|
|
|
130 |
|
|
Device utilization summary:
|
131 |
|
|
|
132 |
|
|
Number of External GCLKIOBs 2 out of 4 50%
|
133 |
|
|
Number of External IOBs 64 out of 140 45%
|
134 |
|
|
|
135 |
|
|
Number of BLOCKRAMs 6 out of 12 50%
|
136 |
|
|
Number of SLICEs 1402 out of 1728 81%
|
137 |
|
|
|
138 |
|
|
Number of GCLKs 2 out of 4 50%
|
139 |
|
|
|
140 |
|
|
|
141 |
|
|
|
142 |
|
|
Overall effort level (-ol): 2 (set by user)
|
143 |
|
|
Placer effort level (-pl): 2 (set by user)
|
144 |
|
|
Placer cost table entry (-t): 1
|
145 |
|
|
Router effort level (-rl): 2 (set by user)
|
146 |
|
|
|
147 |
|
|
Starting initial Timing Analysis. REAL time: 14 secs
|
148 |
|
|
Finished initial Timing Analysis. REAL time: 40 secs
|
149 |
|
|
|
150 |
|
|
Design passed SelectIO DRC.
|
151 |
|
|
Starting the placer. REAL time: 43 secs
|
152 |
|
|
Placement pass 1 ...................
|
153 |
|
|
Placer score = 379658
|
154 |
|
|
Placement pass 2 .........................
|
155 |
|
|
Placer score = 368407
|
156 |
|
|
Placement pass 3 .....................
|
157 |
|
|
Placer score = 369308
|
158 |
|
|
Optimizing ...
|
159 |
|
|
Placer score = 301933
|
160 |
|
|
Improving the placement. REAL time: 1 mins 15 secs
|
161 |
|
|
Placer score = 474349
|
162 |
|
|
Placer score = 507794
|
163 |
|
|
Placer score = 471774
|
164 |
|
|
Placer score = 440616
|
165 |
|
|
Placer score = 418456
|
166 |
|
|
Placer score = 403030
|
167 |
|
|
Placer score = 390280
|
168 |
|
|
Placer score = 381864
|
169 |
|
|
Placer score = 372761
|
170 |
|
|
Placer score = 367215
|
171 |
|
|
Placer score = 361011
|
172 |
|
|
Placer score = 356024
|
173 |
|
|
Placer score = 346592
|
174 |
|
|
Placer score = 342238
|
175 |
|
|
Placer score = 339291
|
176 |
|
|
Placer score = 335589
|
177 |
|
|
Placer score = 332722
|
178 |
|
|
Placer score = 328768
|
179 |
|
|
Placer score = 324807
|
180 |
|
|
Placer score = 319970
|
181 |
|
|
Placer score = 316171
|
182 |
|
|
Placer score = 310589
|
183 |
|
|
Placer score = 305289
|
184 |
|
|
Placer score = 300126
|
185 |
|
|
Placer score = 295734
|
186 |
|
|
Placer score = 293094
|
187 |
|
|
Placer score = 290570
|
188 |
|
|
Placer score = 288768
|
189 |
|
|
Placer score = 287281
|
190 |
|
|
Placer score = 285736
|
191 |
|
|
Placer score = 284379
|
192 |
|
|
Placer score = 283262
|
193 |
|
|
Placer score = 282647
|
194 |
|
|
Placer score = 282077
|
195 |
|
|
Placer stage completed in real time: 2 mins 38 secs
|
196 |
|
|
|
197 |
|
|
All IOBs have been constrained to specific sites.
|
198 |
|
|
|
199 |
|
|
Select IO Utilization and Usage Summary
|
200 |
|
|
_______________________________________
|
201 |
|
|
|
202 |
|
|
NR - means Not Required.
|
203 |
|
|
Each Group of a specific Standard is listed.
|
204 |
|
|
|
205 |
|
|
IO standard (PCI33_5 Vref=NR Vcco=3.30) occupies 48 pads.
|
206 |
|
|
IO standard (LVTTL Vref=NR Vcco=3.30) occupies 18 pads.
|
207 |
|
|
|
208 |
|
|
Bank Summary
|
209 |
|
|
____________
|
210 |
|
|
If an IOB is placed in a Vref site, it will be indicated by the word 'Vref' at
|
211 |
|
|
the end of a summary row. IOBs can be placed in a bank's Vref sites when none of
|
212 |
|
|
the IOBs in the bank require a Vref site.
|
213 |
|
|
NR - means Not Required
|
214 |
|
|
|
215 |
|
|
Bank 0 has 17 pads and is 58% utilized.
|
216 |
|
|
Vref should be set to NR volts.
|
217 |
|
|
Vcco should be set to 3.30 volts.
|
218 |
|
|
Name IO Select Std Vref Vcco Pad Pin
|
219 |
|
|
---- -- ---------- ------ ------ ------ ------
|
220 |
|
|
AD<28> IO PCI33_5 NR 3.30 PAD2 P206
|
221 |
|
|
AD<29> IO PCI33_5 NR 3.30 PAD6 P205
|
222 |
|
|
AD<30> IO PCI33_5 NR 3.30 PAD10 P204
|
223 |
|
|
AD<31> IO PCI33_5 NR 3.30 PAD11 P203 Vref
|
224 |
|
|
LED O LVTTL 3.30 PAD12 P202
|
225 |
|
|
REQ O PCI33_5 3.30 PAD16 P201
|
226 |
|
|
GNT I PCI33_5 NR PAD18 P200 Vref
|
227 |
|
|
RST I PCI33_5 NR PAD19 P199
|
228 |
|
|
INTA O PCI33_5 3.30 PAD20 P195
|
229 |
|
|
CLK I LVTTL NR GCLKPAD3 P185
|
230 |
|
|
|
231 |
|
|
Bank 1 has 19 pads and is 68% utilized.
|
232 |
|
|
Vref should be set to NR volts.
|
233 |
|
|
Vcco should be set to 3.30 volts.
|
234 |
|
|
Name IO Select Std Vref Vcco Pad Pin
|
235 |
|
|
---- -- ---------- ------ ------ ------ ------
|
236 |
|
|
CRT_CLK I LVTTL NR GCLKPAD2 P182
|
237 |
|
|
RGB<15> O LVTTL 3.30 PAD38 P181
|
238 |
|
|
RGB<14> O LVTTL 3.30 PAD40 P180
|
239 |
|
|
RGB<13> O LVTTL 3.30 PAD42 P179
|
240 |
|
|
RGB<12> O LVTTL 3.30 PAD43 P178 Vref
|
241 |
|
|
RGB<11> O LVTTL 3.30 PAD44 P176
|
242 |
|
|
RGB<10> O LVTTL 3.30 PAD45 P175
|
243 |
|
|
RGB<9> O LVTTL 3.30 PAD48 P174
|
244 |
|
|
RGB<8> O LVTTL 3.30 PAD52 P173
|
245 |
|
|
RGB<7> O LVTTL 3.30 PAD53 P172
|
246 |
|
|
RGB<6> O LVTTL 3.30 PAD54 P168
|
247 |
|
|
RGB<5> O LVTTL 3.30 PAD55 P167 Vref
|
248 |
|
|
RGB<4> O LVTTL 3.30 PAD57 P166
|
249 |
|
|
|
250 |
|
|
Bank 4 has 19 pads and is 10% utilized.
|
251 |
|
|
Vcco should be set to 3.30 volts.
|
252 |
|
|
Name IO Select Std Vref Vcco Pad Pin
|
253 |
|
|
---- -- ---------- ------ ------ ------ ------
|
254 |
|
|
VSYNC O LVTTL 3.30 PAD174 P84 Vref
|
255 |
|
|
HSYNC O LVTTL 3.30 PAD175 P83
|
256 |
|
|
|
257 |
|
|
Bank 5 has 16 pads and is 43% utilized.
|
258 |
|
|
Vref should be set to NR volts.
|
259 |
|
|
Vcco should be set to 3.30 volts.
|
260 |
|
|
Name IO Select Std Vref Vcco Pad Pin
|
261 |
|
|
---- -- ---------- ------ ------ ------ ------
|
262 |
|
|
AD<0> IO PCI33_5 NR 3.30 PAD197 P67
|
263 |
|
|
AD<1> IO PCI33_5 NR 3.30 PAD198 P63
|
264 |
|
|
AD<2> IO PCI33_5 NR 3.30 PAD199 P62 Vref
|
265 |
|
|
AD<3> IO PCI33_5 NR 3.30 PAD201 P61
|
266 |
|
|
AD<4> IO PCI33_5 NR 3.30 PAD206 P59 Vref
|
267 |
|
|
AD<5> IO PCI33_5 NR 3.30 PAD207 P58
|
268 |
|
|
AD<6> IO PCI33_5 NR 3.30 PAD211 P57
|
269 |
|
|
|
270 |
|
|
Bank 6 has 18 pads and is 94% utilized.
|
271 |
|
|
Vref should be set to NR volts.
|
272 |
|
|
Vcco should be set to 3.30 volts.
|
273 |
|
|
Name IO Select Std Vref Vcco Pad Pin
|
274 |
|
|
---- -- ---------- ------ ------ ------ ------
|
275 |
|
|
AD<7> IO PCI33_5 NR 3.30 PAD217 P49
|
276 |
|
|
CBE<0> IO PCI33_5 NR 3.30 PAD218 P48
|
277 |
|
|
AD<8> IO PCI33_5 NR 3.30 PAD222 P47
|
278 |
|
|
AD<9> IO PCI33_5 NR 3.30 PAD226 P46
|
279 |
|
|
AD<10> IO PCI33_5 NR 3.30 PAD227 P45 Vref
|
280 |
|
|
AD<11> IO PCI33_5 NR 3.30 PAD232 P43
|
281 |
|
|
AD<12> IO PCI33_5 NR 3.30 PAD234 P42 Vref
|
282 |
|
|
AD<13> IO PCI33_5 NR 3.30 PAD235 P41
|
283 |
|
|
AD<14> IO PCI33_5 NR 3.30 PAD236 P37
|
284 |
|
|
AD<15> IO PCI33_5 NR 3.30 PAD237 P36
|
285 |
|
|
CBE<1> IO PCI33_5 NR 3.30 PAD241 P35
|
286 |
|
|
PAR IO PCI33_5 NR 3.30 PAD244 P34
|
287 |
|
|
SERR O PCI33_5 3.30 PAD245 P33
|
288 |
|
|
PERR IO PCI33_5 NR 3.30 PAD246 P31 Vref
|
289 |
|
|
STOP IO PCI33_5 NR 3.30 PAD247 P30
|
290 |
|
|
DEVSEL IO PCI33_5 NR 3.30 PAD249 P29
|
291 |
|
|
TRDY IO PCI33_5 NR 3.30 PAD252 P27
|
292 |
|
|
|
293 |
|
|
Bank 7 has 18 pads and is 94% utilized.
|
294 |
|
|
Vref should be set to NR volts.
|
295 |
|
|
Vcco should be set to 3.30 volts.
|
296 |
|
|
Name IO Select Std Vref Vcco Pad Pin
|
297 |
|
|
---- -- ---------- ------ ------ ------ ------
|
298 |
|
|
IRDY IO PCI33_5 NR 3.30 PAD253 P24
|
299 |
|
|
FRAME IO PCI33_5 NR 3.30 PAD254 P23
|
300 |
|
|
CBE<2> IO PCI33_5 NR 3.30 PAD256 P22
|
301 |
|
|
AD<16> IO PCI33_5 NR 3.30 PAD258 P21
|
302 |
|
|
AD<17> IO PCI33_5 NR 3.30 PAD259 P20 Vref
|
303 |
|
|
AD<18> IO PCI33_5 NR 3.30 PAD260 P18
|
304 |
|
|
AD<19> IO PCI33_5 NR 3.30 PAD261 P17
|
305 |
|
|
AD<20> IO PCI33_5 NR 3.30 PAD264 P16
|
306 |
|
|
AD<21> IO PCI33_5 NR 3.30 PAD268 P15
|
307 |
|
|
AD<22> IO PCI33_5 NR 3.30 PAD269 P14
|
308 |
|
|
AD<23> IO PCI33_5 NR 3.30 PAD270 P10
|
309 |
|
|
IDSEL I LVTTL NR PAD271 P9 Vref
|
310 |
|
|
CBE<3> IO PCI33_5 NR 3.30 PAD273 P8
|
311 |
|
|
AD<24> IO PCI33_5 NR 3.30 PAD278 P6 Vref
|
312 |
|
|
AD<25> IO PCI33_5 NR 3.30 PAD279 P5
|
313 |
|
|
AD<26> IO PCI33_5 NR 3.30 PAD283 P4
|
314 |
|
|
AD<27> IO PCI33_5 NR 3.30 PAD287 P3
|
315 |
|
|
|
316 |
|
|
Placer completed in real time: 2 mins 40 secs
|
317 |
|
|
|
318 |
|
|
Dumping design to file pci_crt.ncd.
|
319 |
|
|
|
320 |
|
|
Total REAL time to Placer completion: 2 mins 49 secs
|
321 |
|
|
Total CPU time to Placer completion: 2 mins 30 secs
|
322 |
|
|
|
323 |
|
|
|
324 |
|
|
Starting router resource preassignment
|
325 |
|
|
Completed router resource preassignment. REAL time: 3 mins 4 secs
|
326 |
|
|
Starting iterative routing.
|
327 |
|
|
Routing active signals.
|
328 |
|
|
.....................
|
329 |
|
|
End of iteration 1
|
330 |
|
|
9845 successful; 0 unrouted; (0) REAL time: 5 mins 31 secs
|
331 |
|
|
Constraints are met.
|
332 |
|
|
Total REAL time: 5 mins 36 secs
|
333 |
|
|
Total CPU time: 5 mins
|
334 |
|
|
End of route. 9845 routed (100.00%); 0 unrouted.
|
335 |
|
|
No errors found.
|
336 |
|
|
Completely routed.
|
337 |
|
|
|
338 |
|
|
Total REAL time to Router completion: 5 mins 43 secs
|
339 |
|
|
Total CPU time to Router completion: 5 mins 5 secs
|
340 |
|
|
|
341 |
|
|
Generating PAR statistics.
|
342 |
|
|
Timing Score: 0
|
343 |
|
|
|
344 |
|
|
Asterisk (*) preceding a constraint indicates it was not met.
|
345 |
|
|
|
346 |
|
|
--------------------------------------------------------------------------------
|
347 |
|
|
Constraint | Requested | Actual | Logic
|
348 |
|
|
| | | Levels
|
349 |
|
|
--------------------------------------------------------------------------------
|
350 |
|
|
TS_CLK = PERIOD TIMEGRP "CLK" 30 nS HI | 30.000ns | 23.294ns | 8
|
351 |
|
|
GH 50.000 % | | |
|
352 |
|
|
--------------------------------------------------------------------------------
|
353 |
|
|
TS_CRT_CLK = PERIOD TIMEGRP "CRT_CLK" 44 | 44.000ns | 23.360ns | 6
|
354 |
|
|
nS HIGH 50.000 % | | |
|
355 |
|
|
--------------------------------------------------------------------------------
|
356 |
|
|
TS_CLK_2_CRT_CLK = MAXDELAY FROM TIMEGRP | 30.000ns | 21.603ns | 9
|
357 |
|
|
"CLK" TO TIMEGRP "CRT_CLK" 30 nS | | |
|
358 |
|
|
--------------------------------------------------------------------------------
|
359 |
|
|
TS_CRT_CLK_2_CLK = MAXDELAY FROM TIMEGRP | 30.000ns | 16.423ns | 8
|
360 |
|
|
"CRT_CLK" TO TIMEGRP "CLK" 30 nS | | |
|
361 |
|
|
--------------------------------------------------------------------------------
|
362 |
|
|
COMP "REQ" OFFSET = OUT 12 nS AFTER COMP | 12.000ns | 9.486ns | 1
|
363 |
|
|
"CLK" | | |
|
364 |
|
|
--------------------------------------------------------------------------------
|
365 |
|
|
COMP "SERR" OFFSET = OUT 11 nS AFTER COM | 11.000ns | 9.434ns | 1
|
366 |
|
|
P "CLK" | | |
|
367 |
|
|
--------------------------------------------------------------------------------
|
368 |
|
|
COMP "GNT" OFFSET = IN 10 nS BEFORE COMP | 10.000ns | 9.535ns | 5
|
369 |
|
|
"CLK" | | |
|
370 |
|
|
--------------------------------------------------------------------------------
|
371 |
|
|
COMP "FRAME" OFFSET = IN 7 nS BEFORE COM | 7.000ns | 6.287ns | 4
|
372 |
|
|
P "CLK" | | |
|
373 |
|
|
--------------------------------------------------------------------------------
|
374 |
|
|
COMP "FRAME" OFFSET = OUT 11 nS AFTER CO | 11.000ns | 9.432ns | 1
|
375 |
|
|
MP "CLK" | | |
|
376 |
|
|
--------------------------------------------------------------------------------
|
377 |
|
|
COMP "IRDY" OFFSET = IN 7 nS BEFORE COMP | 7.000ns | 6.442ns | 4
|
378 |
|
|
"CLK" | | |
|
379 |
|
|
--------------------------------------------------------------------------------
|
380 |
|
|
COMP "IRDY" OFFSET = OUT 11 nS AFTER COM | 11.000ns | 9.432ns | 1
|
381 |
|
|
P "CLK" | | |
|
382 |
|
|
--------------------------------------------------------------------------------
|
383 |
|
|
COMP "DEVSEL" OFFSET = IN 7 nS BEFORE CO | 7.000ns | 3.800ns | 3
|
384 |
|
|
MP "CLK" | | |
|
385 |
|
|
--------------------------------------------------------------------------------
|
386 |
|
|
COMP "DEVSEL" OFFSET = OUT 11 nS AFTER C | 11.000ns | 9.432ns | 1
|
387 |
|
|
OMP "CLK" | | |
|
388 |
|
|
--------------------------------------------------------------------------------
|
389 |
|
|
COMP "TRDY" OFFSET = IN 7 nS BEFORE COMP | 7.000ns | 6.473ns | 3
|
390 |
|
|
"CLK" | | |
|
391 |
|
|
--------------------------------------------------------------------------------
|
392 |
|
|
COMP "TRDY" OFFSET = OUT 10 nS AFTER COM | 10.000ns | 9.435ns | 1
|
393 |
|
|
P "CLK" | | |
|
394 |
|
|
--------------------------------------------------------------------------------
|
395 |
|
|
COMP "STOP" OFFSET = IN 7 nS BEFORE COMP | 7.000ns | 5.665ns | 3
|
396 |
|
|
"CLK" | | |
|
397 |
|
|
--------------------------------------------------------------------------------
|
398 |
|
|
COMP "STOP" OFFSET = OUT 11 nS AFTER COM | 11.000ns | 9.432ns | 1
|
399 |
|
|
P "CLK" | | |
|
400 |
|
|
--------------------------------------------------------------------------------
|
401 |
|
|
COMP "PAR" OFFSET = IN 7 nS BEFORE COMP | 7.000ns | 4.610ns | 4
|
402 |
|
|
"CLK" | | |
|
403 |
|
|
--------------------------------------------------------------------------------
|
404 |
|
|
COMP "PAR" OFFSET = OUT 11 nS AFTER COMP | 11.000ns | 9.434ns | 1
|
405 |
|
|
"CLK" | | |
|
406 |
|
|
--------------------------------------------------------------------------------
|
407 |
|
|
COMP "PERR" OFFSET = IN 7 nS BEFORE COMP | 7.000ns | 2.145ns | 2
|
408 |
|
|
"CLK" | | |
|
409 |
|
|
--------------------------------------------------------------------------------
|
410 |
|
|
COMP "PERR" OFFSET = OUT 11 nS AFTER COM | 11.000ns | 9.434ns | 1
|
411 |
|
|
P "CLK" | | |
|
412 |
|
|
--------------------------------------------------------------------------------
|
413 |
|
|
TIMEGRP "PCI_AD" OFFSET = IN 7 nS BEFORE | 7.000ns | 2.762ns | 1
|
414 |
|
|
COMP "CLK" | | |
|
415 |
|
|
--------------------------------------------------------------------------------
|
416 |
|
|
TIMEGRP "PCI_AD" OFFSET = OUT 11 nS AFTE | 11.000ns | 9.540ns | 1
|
417 |
|
|
R COMP "CLK" | | |
|
418 |
|
|
--------------------------------------------------------------------------------
|
419 |
|
|
TIMEGRP "PCI_CBE" OFFSET = IN 7 nS BEFOR | 7.000ns | 5.437ns | 4
|
420 |
|
|
E COMP "CLK" | | |
|
421 |
|
|
--------------------------------------------------------------------------------
|
422 |
|
|
TIMEGRP "PCI_CBE" OFFSET = OUT 11 nS AFT | 11.000ns | 9.435ns | 1
|
423 |
|
|
ER COMP "CLK" | | |
|
424 |
|
|
--------------------------------------------------------------------------------
|
425 |
|
|
|
426 |
|
|
|
427 |
|
|
All constraints were met.
|
428 |
|
|
Dumping design to file pci_crt.ncd.
|
429 |
|
|
|
430 |
|
|
|
431 |
|
|
All signals are completely routed.
|
432 |
|
|
|
433 |
|
|
Total REAL time to PAR completion: 7 mins 13 secs
|
434 |
|
|
Total CPU time to PAR completion: 6 mins 10 secs
|
435 |
|
|
|
436 |
|
|
Placement: Completed - No errors found.
|
437 |
|
|
Routing: Completed - No errors found.
|
438 |
|
|
Timing: Completed - No errors found.
|
439 |
|
|
|
440 |
|
|
PAR done.
|
441 |
|
|
|
442 |
|
|
==================================================
|
443 |
|
|
|
444 |
|
|
trce pci_crt.ncd pci_crt.pcf -e 3 -o pci_crt.twr -xml pci_crt_trce.xml
|
445 |
|
|
Release 3.3.08i - Trace D.27
|
446 |
|
|
Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved.
|
447 |
|
|
|
448 |
|
|
|
449 |
|
|
|
450 |
|
|
Loading design for application trce from file pci_crt.ncd.
|
451 |
|
|
"TOP" is an NCD, version 2.35, device xc2s150, package pq208, speed -5
|
452 |
|
|
Loading device for application trce from file 'v150.nph' in environment
|
453 |
|
|
C:/Foundation.
|
454 |
|
|
--------------------------------------------------------------------------------
|
455 |
|
|
Xilinx TRACE, Version D.27
|
456 |
|
|
Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved.
|
457 |
|
|
|
458 |
|
|
trce pci_crt.ncd pci_crt.pcf -e 3 -o pci_crt.twr -xml pci_crt_trce.xml
|
459 |
|
|
|
460 |
|
|
Design file: pci_crt.ncd
|
461 |
|
|
Physical constraint file: pci_crt.pcf
|
462 |
|
|
Device,speed: xc2s150,-5 (PRELIMINARY 1.21 2001-04-09)
|
463 |
|
|
Report level: error report
|
464 |
|
|
--------------------------------------------------------------------------------
|
465 |
|
|
|
466 |
|
|
|
467 |
|
|
|
468 |
|
|
Timing summary:
|
469 |
|
|
---------------
|
470 |
|
|
|
471 |
|
|
Timing errors: 0 Score: 0
|
472 |
|
|
|
473 |
|
|
Constraints cover 97754 paths, 0 nets, and 8987 connections (91.8% coverage)
|
474 |
|
|
|
475 |
|
|
Design statistics:
|
476 |
|
|
Minimum period: 23.360ns (Maximum frequency: 42.808MHz)
|
477 |
|
|
Maximum path delay from/to any node: 21.603ns
|
478 |
|
|
Minimum input arrival time before clock: 9.535ns
|
479 |
|
|
Minimum output required time after clock: 9.540ns
|
480 |
|
|
|
481 |
|
|
|
482 |
|
|
Analysis completed Tue Jan 15 13:36:48 2002
|
483 |
|
|
--------------------------------------------------------------------------------
|
484 |
|
|
|
485 |
|
|
Total time: 1 mins 6 secs
|
486 |
|
|
|
487 |
|
|
==================================================
|
488 |
|
|
|
489 |
|
|
ngdanno pci_crt.ncd
|
490 |
|
|
Release 3.3.08i - ngdanno D.27
|
491 |
|
|
Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved.
|
492 |
|
|
|
493 |
|
|
Loading design for application ngdanno from file pci_crt.ncd.
|
494 |
|
|
"TOP" is an NCD, version 2.35, device xc2s150, package pq208, speed -5
|
495 |
|
|
Loading device for application ngdanno from file 'v150.nph' in environment
|
496 |
|
|
C:/Foundation.
|
497 |
|
|
Loading constraints from file "pci_crt.pcf"...
|
498 |
|
|
WARNING:Anno:12 - Since the .ngm file was not specified, the .nga will be
|
499 |
|
|
created from the .ncd.
|
500 |
|
|
Building NGA image...
|
501 |
|
|
Annotating NGA image...
|
502 |
|
|
Distributing delays...
|
503 |
|
|
Resolving logical and physical hierarchies...
|
504 |
|
|
Running NGD DRC...
|
505 |
|
|
WARNING:Ngd:333 - NOTE: This design contains the undriven net "GSR" which you
|
506 |
|
|
could drive during simulation to get valid results.
|
507 |
|
|
WARNING:Ngd:333 - NOTE: This design contains the undriven net "GTS" which you
|
508 |
|
|
could drive during simulation to get valid results.
|
509 |
|
|
Writing .nga file "pci_crt.nga"...
|
510 |
|
|
1476 physical models annotated
|
511 |
|
|
|
512 |
|
|
==================================================
|
513 |
|
|
|
514 |
|
|
ngd2ver -w pci_crt.nga pci_crt_time_sim.v
|
515 |
|
|
Release 3.3.08i - ngd2ver D.27
|
516 |
|
|
Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved.
|
517 |
|
|
--- Initializing ...
|
518 |
|
|
--- Reading pci_crt.nga.
|
519 |
|
|
--- Running prep.
|
520 |
|
|
--- Initializing module list.
|
521 |
|
|
--- Processing netlist ...
|
522 |
|
|
WARNING:NetListWriters:106 - Wire bridge/pciu_err_addr_out[10] not found for
|
523 |
|
|
wire bus bridge/pciu_err_addr_out[31:0] on block TOP.
|
524 |
|
|
WARNING:NetListWriters:106 - Wire bridge/pciu_err_addr_out[9] not found for
|
525 |
|
|
wire bus bridge/pciu_err_addr_out[31:0] on block TOP.
|
526 |
|
|
WARNING:NetListWriters:106 - Wire bridge/pciu_err_addr_out[8] not found for
|
527 |
|
|
wire bus bridge/pciu_err_addr_out[31:0] on block TOP.
|
528 |
|
|
WARNING:NetListWriters:106 - Wire bridge/pciu_err_addr_out[7] not found for
|
529 |
|
|
wire bus bridge/pciu_err_addr_out[31:0] on block TOP.
|
530 |
|
|
WARNING:NetListWriters:106 - Wire bridge/pciu_err_addr_out[6] not found for
|
531 |
|
|
wire bus bridge/pciu_err_addr_out[31:0] on block TOP.
|
532 |
|
|
WARNING:NetListWriters:106 - Wire bridge/pciu_err_addr_out[5] not found for
|
533 |
|
|
wire bus bridge/pciu_err_addr_out[31:0] on block TOP.
|
534 |
|
|
WARNING:NetListWriters:106 - Wire bridge/pciu_err_addr_out[4] not found for
|
535 |
|
|
wire bus bridge/pciu_err_addr_out[31:0] on block TOP.
|
536 |
|
|
WARNING:NetListWriters:106 - Wire bridge/pciu_err_addr_out[3] not found for
|
537 |
|
|
wire bus bridge/pciu_err_addr_out[31:0] on block TOP.
|
538 |
|
|
WARNING:NetListWriters:106 - Wire bridge/pciu_err_addr_out[2] not found for
|
539 |
|
|
wire bus bridge/pciu_err_addr_out[31:0] on block TOP.
|
540 |
|
|
WARNING:NetListWriters:107 - Signal bus bridge/pciu_err_addr_out[31:0] on block
|
541 |
|
|
TOP is not reconstructed.
|
542 |
|
|
WARNING:NetListWriters:106 - Wire
|
543 |
|
|
bridge/pci_target_unit/pcit_if_pciw_fifo_control_out[1] not found for wire
|
544 |
|
|
bus bridge/pci_target_unit/pcit_if_pciw_fifo_control_out[2:0] on block TOP.
|
545 |
|
|
WARNING:NetListWriters:107 - Signal bus
|
546 |
|
|
bridge/pci_target_unit/pcit_if_pciw_fifo_control_out[2:0] on block TOP is not
|
547 |
|
|
reconstructed.
|
548 |
|
|
WARNING:NetListWriters:106 - Wire
|
549 |
|
|
bridge/pci_target_unit/fifos_pciw_control_out[1] not found for wire bus
|
550 |
|
|
bridge/pci_target_unit/fifos_pciw_control_out[2:0] on block TOP.
|
551 |
|
|
WARNING:NetListWriters:107 - Signal bus
|
552 |
|
|
bridge/pci_target_unit/fifos_pciw_control_out[2:0] on block TOP is not
|
553 |
|
|
reconstructed.
|
554 |
|
|
--- Generating ngd2ver output file(s) ...
|
555 |
|
|
--- Writing sdf file pci_crt_time_sim.sdf.
|
556 |
|
|
--- Writing netlist file pci_crt_time_sim.v.
|
557 |
|
|
WARNING:NetListWriters:108 - In order to compile this verilog file
|
558 |
|
|
successfully, please add $XILINX/verilog/src/glbl.v to your compile command.
|
559 |
|
|
--- ngd2ver is done !
|
560 |
|
|
|
561 |
|
|
==================================================
|
562 |
|
|
|
563 |
|
|
xcpy pci_crt_time_sim.v f:\mihad\fpga_t~1\pci_crt\pci_crt_time_sim.v
|
564 |
|
|
|
565 |
|
|
==================================================
|
566 |
|
|
|
567 |
|
|
xcpy pci_crt_time_sim.sdf f:\mihad\fpga_t~1\pci_crt\pci_crt_time_sim.sdf
|
568 |
|
|
|
569 |
|
|
==================================================
|
570 |
|
|
|
571 |
|
|
bitgen pci_crt.ncd -l -w -f bitgen.ut
|
572 |
|
|
Release 3.3.08i - Bitgen D.27
|
573 |
|
|
Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved.
|
574 |
|
|
|
575 |
|
|
Loading design for application Bitgen from file pci_crt.ncd.
|
576 |
|
|
"TOP" is an NCD, version 2.35, device xc2s150, package pq208, speed -5
|
577 |
|
|
Loading device for application Bitgen from file 'v150.nph' in environment
|
578 |
|
|
C:/Foundation.
|
579 |
|
|
Opened constraints file pci_crt.pcf.
|
580 |
|
|
|
581 |
|
|
Tue Jan 15 13:40:02 2002
|
582 |
|
|
|
583 |
|
|
Running DRC.
|
584 |
|
|
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOA0 of comp
|
585 |
|
|
bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not
|
586 |
|
|
connected.
|
587 |
|
|
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOA1 of comp
|
588 |
|
|
bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not
|
589 |
|
|
connected.
|
590 |
|
|
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOA2 of comp
|
591 |
|
|
bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not
|
592 |
|
|
connected.
|
593 |
|
|
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOA3 of comp
|
594 |
|
|
bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not
|
595 |
|
|
connected.
|
596 |
|
|
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOA6 of comp
|
597 |
|
|
bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not
|
598 |
|
|
connected.
|
599 |
|
|
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOA7 of comp
|
600 |
|
|
bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not
|
601 |
|
|
connected.
|
602 |
|
|
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOA8 of comp
|
603 |
|
|
bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not
|
604 |
|
|
connected.
|
605 |
|
|
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOA9 of comp
|
606 |
|
|
bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not
|
607 |
|
|
connected.
|
608 |
|
|
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOA10 of comp
|
609 |
|
|
bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not
|
610 |
|
|
connected.
|
611 |
|
|
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOA11 of comp
|
612 |
|
|
bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not
|
613 |
|
|
connected.
|
614 |
|
|
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOA12 of comp
|
615 |
|
|
bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not
|
616 |
|
|
connected.
|
617 |
|
|
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOA13 of comp
|
618 |
|
|
bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not
|
619 |
|
|
connected.
|
620 |
|
|
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOA14 of comp
|
621 |
|
|
bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not
|
622 |
|
|
connected.
|
623 |
|
|
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOA15 of comp
|
624 |
|
|
bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not
|
625 |
|
|
connected.
|
626 |
|
|
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB5 of comp
|
627 |
|
|
bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not
|
628 |
|
|
connected.
|
629 |
|
|
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB6 of comp
|
630 |
|
|
bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not
|
631 |
|
|
connected.
|
632 |
|
|
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB7 of comp
|
633 |
|
|
bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not
|
634 |
|
|
connected.
|
635 |
|
|
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB8 of comp
|
636 |
|
|
bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not
|
637 |
|
|
connected.
|
638 |
|
|
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB9 of comp
|
639 |
|
|
bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not
|
640 |
|
|
connected.
|
641 |
|
|
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB10 of comp
|
642 |
|
|
bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not
|
643 |
|
|
connected.
|
644 |
|
|
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB11 of comp
|
645 |
|
|
bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not
|
646 |
|
|
connected.
|
647 |
|
|
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB12 of comp
|
648 |
|
|
bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not
|
649 |
|
|
connected.
|
650 |
|
|
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB13 of comp
|
651 |
|
|
bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not
|
652 |
|
|
connected.
|
653 |
|
|
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB14 of comp
|
654 |
|
|
bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not
|
655 |
|
|
connected.
|
656 |
|
|
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB15 of comp
|
657 |
|
|
bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not
|
658 |
|
|
connected.
|
659 |
|
|
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB0 of comp
|
660 |
|
|
CRT/ssvga_fifo/ramb4_s8_0 is not connected.
|
661 |
|
|
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB1 of comp
|
662 |
|
|
CRT/ssvga_fifo/ramb4_s8_0 is not connected.
|
663 |
|
|
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB2 of comp
|
664 |
|
|
CRT/ssvga_fifo/ramb4_s8_0 is not connected.
|
665 |
|
|
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB3 of comp
|
666 |
|
|
CRT/ssvga_fifo/ramb4_s8_0 is not connected.
|
667 |
|
|
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB4 of comp
|
668 |
|
|
CRT/ssvga_fifo/ramb4_s8_0 is not connected.
|
669 |
|
|
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB5 of comp
|
670 |
|
|
CRT/ssvga_fifo/ramb4_s8_0 is not connected.
|
671 |
|
|
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB6 of comp
|
672 |
|
|
CRT/ssvga_fifo/ramb4_s8_0 is not connected.
|
673 |
|
|
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB7 of comp
|
674 |
|
|
CRT/ssvga_fifo/ramb4_s8_0 is not connected.
|
675 |
|
|
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB8 of comp
|
676 |
|
|
CRT/ssvga_fifo/ramb4_s8_0 is not connected.
|
677 |
|
|
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB9 of comp
|
678 |
|
|
CRT/ssvga_fifo/ramb4_s8_0 is not connected.
|
679 |
|
|
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB10 of comp
|
680 |
|
|
CRT/ssvga_fifo/ramb4_s8_0 is not connected.
|
681 |
|
|
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB11 of comp
|
682 |
|
|
CRT/ssvga_fifo/ramb4_s8_0 is not connected.
|
683 |
|
|
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB12 of comp
|
684 |
|
|
CRT/ssvga_fifo/ramb4_s8_0 is not connected.
|
685 |
|
|
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB13 of comp
|
686 |
|
|
CRT/ssvga_fifo/ramb4_s8_0 is not connected.
|
687 |
|
|
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB14 of comp
|
688 |
|
|
CRT/ssvga_fifo/ramb4_s8_0 is not connected.
|
689 |
|
|
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB15 of comp
|
690 |
|
|
CRT/ssvga_fifo/ramb4_s8_0 is not connected.
|
691 |
|
|
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB0 of comp
|
692 |
|
|
CRT/ssvga_fifo/ramb4_s8_1 is not connected.
|
693 |
|
|
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB1 of comp
|
694 |
|
|
CRT/ssvga_fifo/ramb4_s8_1 is not connected.
|
695 |
|
|
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB2 of comp
|
696 |
|
|
CRT/ssvga_fifo/ramb4_s8_1 is not connected.
|
697 |
|
|
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB3 of comp
|
698 |
|
|
CRT/ssvga_fifo/ramb4_s8_1 is not connected.
|
699 |
|
|
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB4 of comp
|
700 |
|
|
CRT/ssvga_fifo/ramb4_s8_1 is not connected.
|
701 |
|
|
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB5 of comp
|
702 |
|
|
CRT/ssvga_fifo/ramb4_s8_1 is not connected.
|
703 |
|
|
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB6 of comp
|
704 |
|
|
CRT/ssvga_fifo/ramb4_s8_1 is not connected.
|
705 |
|
|
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB7 of comp
|
706 |
|
|
CRT/ssvga_fifo/ramb4_s8_1 is not connected.
|
707 |
|
|
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB8 of comp
|
708 |
|
|
CRT/ssvga_fifo/ramb4_s8_1 is not connected.
|
709 |
|
|
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB9 of comp
|
710 |
|
|
CRT/ssvga_fifo/ramb4_s8_1 is not connected.
|
711 |
|
|
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB10 of comp
|
712 |
|
|
CRT/ssvga_fifo/ramb4_s8_1 is not connected.
|
713 |
|
|
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB11 of comp
|
714 |
|
|
CRT/ssvga_fifo/ramb4_s8_1 is not connected.
|
715 |
|
|
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB12 of comp
|
716 |
|
|
CRT/ssvga_fifo/ramb4_s8_1 is not connected.
|
717 |
|
|
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB13 of comp
|
718 |
|
|
CRT/ssvga_fifo/ramb4_s8_1 is not connected.
|
719 |
|
|
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB14 of comp
|
720 |
|
|
CRT/ssvga_fifo/ramb4_s8_1 is not connected.
|
721 |
|
|
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB15 of comp
|
722 |
|
|
CRT/ssvga_fifo/ramb4_s8_1 is not connected.
|
723 |
|
|
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB0 of comp
|
724 |
|
|
CRT/ssvga_pallete is not connected.
|
725 |
|
|
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB1 of comp
|
726 |
|
|
CRT/ssvga_pallete is not connected.
|
727 |
|
|
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB2 of comp
|
728 |
|
|
CRT/ssvga_pallete is not connected.
|
729 |
|
|
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB3 of comp
|
730 |
|
|
CRT/ssvga_pallete is not connected.
|
731 |
|
|
DRC detected 0 errors and 61 warnings.
|
732 |
|
|
Saving ll file in "pci_crt.ll".
|
733 |
|
|
Creating bit map...
|
734 |
|
|
Saving bit stream in "pci_crt.bit".
|
735 |
|
|
|
736 |
|
|
==================================================
|
737 |
|
|
|
738 |
|
|
xcpy pci_crt.bit f:\mihad\fpga_t~1\pci_crt\pci_crt.bit
|
739 |
|
|
|
740 |
|
|
==================================================
|
741 |
|
|
|
742 |
|
|
xcpy pci_crt.ll f:\mihad\fpga_t~1\pci_crt\pci_crt.ll
|