Subversion Repositories pci

#-- Synplicity, Inc.

#-- Version 7.2

#-- Project file /shared/projects/pci/mihad/pci/apps/crt/syn/synplify/pci_crt.prj

#-- Written on Mon Mar 10 13:16:14 2003

#add_file options

add_file -verilog "$LIB/xilinx/virtex.v"

add_file -verilog "../../../../rtl/verilog/meta_flop.v"

add_file -verilog "../../../../rtl/verilog/pci_async_reset_flop.v"

add_file -verilog "../../../../rtl/verilog/pci_bridge32.v"

add_file -verilog "../../../../rtl/verilog/pci_cbe_en_crit.v"

add_file -verilog "../../../../rtl/verilog/pci_conf_cyc_addr_dec.v"

add_file -verilog "../../../../rtl/verilog/pci_conf_space.v"

add_file -verilog "../../../../rtl/verilog/pci_cur_out_reg.v"

add_file -verilog "../../../../rtl/verilog/pci_delayed_sync.v"

add_file -verilog "../../../../rtl/verilog/pci_delayed_write_reg.v"

add_file -verilog "../../../../rtl/verilog/pci_frame_crit.v"

add_file -verilog "../../../../rtl/verilog/pci_frame_en_crit.v"

add_file -verilog "../../../../rtl/verilog/pci_frame_load_crit.v"

add_file -verilog "../../../../rtl/verilog/pci_in_reg.v"

add_file -verilog "../../../../rtl/verilog/pci_io_mux_ad_en_crit.v"

add_file -verilog "../../../../rtl/verilog/pci_io_mux_ad_load_crit.v"

add_file -verilog "../../../../rtl/verilog/pci_io_mux.v"

add_file -verilog "../../../../rtl/verilog/pci_irdy_out_crit.v"

add_file -verilog "../../../../rtl/verilog/pci_mas_ad_en_crit.v"

add_file -verilog "../../../../rtl/verilog/pci_mas_ad_load_crit.v"

add_file -verilog "../../../../rtl/verilog/pci_mas_ch_state_crit.v"

add_file -verilog "../../../../rtl/verilog/pci_master32_sm_if.v"

add_file -verilog "../../../../rtl/verilog/pci_master32_sm.v"

add_file -verilog "../../../../rtl/verilog/pci_out_reg.v"

add_file -verilog "../../../../rtl/verilog/pci_par_crit.v"

add_file -verilog "../../../../rtl/verilog/pci_parity_check.v"

add_file -verilog "../../../../rtl/verilog/pci_pci_decoder.v"

add_file -verilog "../../../../rtl/verilog/pci_pcir_fifo_control.v"

add_file -verilog "../../../../rtl/verilog/pci_pci_tpram.v"

add_file -verilog "../../../../rtl/verilog/pci_pciw_fifo_control.v"

add_file -verilog "../../../../rtl/verilog/pci_pciw_pcir_fifos.v"

add_file -verilog "../../../../rtl/verilog/pci_perr_crit.v"

add_file -verilog "../../../../rtl/verilog/pci_perr_en_crit.v"

add_file -verilog "../../../../rtl/verilog/pci_ram_16x40d.v"

add_file -verilog "../../../../rtl/verilog/pci_rst_int.v"

add_file -verilog "../../../../rtl/verilog/pci_serr_crit.v"

add_file -verilog "../../../../rtl/verilog/pci_serr_en_crit.v"

add_file -verilog "../../../../rtl/verilog/pci_sync_module.v"

add_file -verilog "../../../../rtl/verilog/pci_target32_clk_en.v"

add_file -verilog "../../../../rtl/verilog/pci_target32_devs_crit.v"

add_file -verilog "../../../../rtl/verilog/pci_target32_interface.v"

add_file -verilog "../../../../rtl/verilog/pci_target32_sm.v"

add_file -verilog "../../../../rtl/verilog/pci_target32_stop_crit.v"

add_file -verilog "../../../../rtl/verilog/pci_target32_trdy_crit.v"

add_file -verilog "../../../../rtl/verilog/pci_target_unit.v"

add_file -verilog "../../../../rtl/verilog/pci_wb_addr_mux.v"

add_file -verilog "../../../../rtl/verilog/pci_wb_decoder.v"

add_file -verilog "../../../../rtl/verilog/pci_wb_master.v"

add_file -verilog "../../../../rtl/verilog/pci_wbr_fifo_control.v"

add_file -verilog "../../../../rtl/verilog/pci_wb_slave_unit.v"

add_file -verilog "../../../../rtl/verilog/pci_wb_slave.v"

add_file -verilog "../../../../rtl/verilog/pci_wb_tpram.v"

add_file -verilog "../../../../rtl/verilog/pci_wbw_fifo_control.v"

add_file -verilog "../../../../rtl/verilog/pci_wbw_wbr_fifos.v"

add_file -verilog "../../../../rtl/verilog/synchronizer_flop.v"

add_file -verilog "../../rtl/verilog/crtc_iob.v"

add_file -verilog "../../rtl/verilog/ssvga_crtc.v"

add_file -verilog "../../rtl/verilog/ssvga_fifo.v"

add_file -verilog "../../rtl/verilog/ssvga_top.v"

add_file -verilog "../../rtl/verilog/ssvga_wbm_if.v"

add_file -verilog "../../rtl/verilog/ssvga_wbs_if.v"

add_file -constraint "pci_crt.sdc"

add_file -verilog "../../rtl/verilog/top.v"

#implementation: "rev_1"

impl -add rev_1

#device options

set_option -technology SPARTAN2

set_option -part XC2S150

set_option -package PQ208

set_option -speed_grade -5

#compilation/mapping options

set_option -default_enum_encoding default

set_option -symbolic_fsm_compiler 1

set_option -resource_sharing 0

set_option -use_fsm_explorer 0

#map options

set_option -frequency 50.000

set_option -fanout_limit 50

set_option -disable_io_insertion 0

set_option -pipe 1

set_option -retiming 1

set_option -modular 0

set_option -update_models_cp 0

set_option -verification_mode 0

#simulation options

set_option -write_verilog 0

set_option -write_vhdl 0

#automatic place and route (vendor) options

set_option -write_apr_constraint 1

#set result format/file last

project -result_file "rev_1/top.edf"

#implementation attributes

set_option -compiler_compatible 0

set_option -random_floorplan 0

set_option -popfeed 1

set_option -constprop 1

set_option -createhierarchy 0

set_option -floorplan ""

set_option -nfilter_user_path ""

set_option -pin_assignment ""

set_option -include_path "../../rtl/verilog/;../../../../rtl/verilog/"

impl -active "rev_1"