1 |
59 |
mihad |
#-- Synplicity, Inc.
|
2 |
|
|
#-- Version Amplify 3.1
|
3 |
|
|
#-- Project file /shared/projects/pci/mihad/pci/apps/crt/syn/synplify/pci_crt.prj
|
4 |
|
|
#-- Written on Fri Sep 27 16:20:50 2002
|
5 |
|
|
|
6 |
|
|
|
7 |
|
|
#add_file options
|
8 |
|
|
add_file -verilog "$LIB/xilinx/virtex.v"
|
9 |
|
|
add_file -verilog "../../../../rtl/verilog/async_reset_flop.v"
|
10 |
|
|
add_file -verilog "../../../../rtl/verilog/cbe_en_crit.v"
|
11 |
|
|
add_file -verilog "../../../../rtl/verilog/conf_cyc_addr_dec.v"
|
12 |
|
|
add_file -verilog "../../../../rtl/verilog/conf_space.v"
|
13 |
|
|
add_file -verilog "../../../../rtl/verilog/cur_out_reg.v"
|
14 |
|
|
add_file -verilog "../../../../rtl/verilog/decoder.v"
|
15 |
|
|
add_file -verilog "../../../../rtl/verilog/delayed_sync.v"
|
16 |
|
|
add_file -verilog "../../../../rtl/verilog/delayed_write_reg.v"
|
17 |
|
|
add_file -verilog "../../../../rtl/verilog/fifo_control.v"
|
18 |
|
|
add_file -verilog "../../../../rtl/verilog/frame_crit.v"
|
19 |
|
|
add_file -verilog "../../../../rtl/verilog/frame_en_crit.v"
|
20 |
|
|
add_file -verilog "../../../../rtl/verilog/frame_load_crit.v"
|
21 |
|
|
add_file -verilog "../../../../rtl/verilog/irdy_out_crit.v"
|
22 |
|
|
add_file -verilog "../../../../rtl/verilog/mas_ad_en_crit.v"
|
23 |
|
|
add_file -verilog "../../../../rtl/verilog/mas_ad_load_crit.v"
|
24 |
|
|
add_file -verilog "../../../../rtl/verilog/mas_ch_state_crit.v"
|
25 |
|
|
add_file -verilog "../../../../rtl/verilog/out_reg.v"
|
26 |
|
|
add_file -verilog "../../../../rtl/verilog/par_crit.v"
|
27 |
|
|
add_file -verilog "../../../../rtl/verilog/pci_bridge32.v"
|
28 |
|
|
add_file -verilog "../../../../rtl/verilog/pci_decoder.v"
|
29 |
|
|
add_file -verilog "../../../../rtl/verilog/pci_in_reg.v"
|
30 |
|
|
add_file -verilog "../../../../rtl/verilog/pci_io_mux_ad_en_crit.v"
|
31 |
|
|
add_file -verilog "../../../../rtl/verilog/pci_io_mux_ad_load_crit.v"
|
32 |
|
|
add_file -verilog "../../../../rtl/verilog/pci_io_mux.v"
|
33 |
|
|
add_file -verilog "../../../../rtl/verilog/pci_master32_sm_if.v"
|
34 |
|
|
add_file -verilog "../../../../rtl/verilog/pci_master32_sm.v"
|
35 |
|
|
add_file -verilog "../../../../rtl/verilog/pci_parity_check.v"
|
36 |
|
|
add_file -verilog "../../../../rtl/verilog/pci_ram_16x40d.v"
|
37 |
|
|
add_file -verilog "../../../../rtl/verilog/pci_rst_int.v"
|
38 |
|
|
add_file -verilog "../../../../rtl/verilog/pci_target32_clk_en.v"
|
39 |
|
|
add_file -verilog "../../../../rtl/verilog/pci_target32_devs_crit.v"
|
40 |
|
|
add_file -verilog "../../../../rtl/verilog/pci_target32_interface.v"
|
41 |
|
|
add_file -verilog "../../../../rtl/verilog/pci_target32_sm.v"
|
42 |
|
|
add_file -verilog "../../../../rtl/verilog/pci_target32_stop_crit.v"
|
43 |
|
|
add_file -verilog "../../../../rtl/verilog/pci_target32_trdy_crit.v"
|
44 |
|
|
add_file -verilog "../../../../rtl/verilog/pci_target_unit.v"
|
45 |
|
|
add_file -verilog "../../../../rtl/verilog/pci_tpram.v"
|
46 |
|
|
add_file -verilog "../../../../rtl/verilog/pciw_fifo_control.v"
|
47 |
|
|
add_file -verilog "../../../../rtl/verilog/pciw_pcir_fifos.v"
|
48 |
|
|
add_file -verilog "../../../../rtl/verilog/perr_crit.v"
|
49 |
|
|
add_file -verilog "../../../../rtl/verilog/perr_en_crit.v"
|
50 |
|
|
add_file -verilog "../../../../rtl/verilog/serr_crit.v"
|
51 |
|
|
add_file -verilog "../../../../rtl/verilog/serr_en_crit.v"
|
52 |
|
|
add_file -verilog "../../../../rtl/verilog/synchronizer_flop.v"
|
53 |
|
|
add_file -verilog "../../../../rtl/verilog/sync_module.v"
|
54 |
|
|
add_file -verilog "../../../../rtl/verilog/wb_addr_mux.v"
|
55 |
|
|
add_file -verilog "../../../../rtl/verilog/wb_master.v"
|
56 |
|
|
add_file -verilog "../../../../rtl/verilog/wbr_fifo_control.v"
|
57 |
|
|
add_file -verilog "../../../../rtl/verilog/wb_slave_unit.v"
|
58 |
|
|
add_file -verilog "../../../../rtl/verilog/wb_slave.v"
|
59 |
|
|
add_file -verilog "../../../../rtl/verilog/wb_tpram.v"
|
60 |
|
|
add_file -verilog "../../../../rtl/verilog/wbw_fifo_control.v"
|
61 |
|
|
add_file -verilog "../../../../rtl/verilog/wbw_wbr_fifos.v"
|
62 |
|
|
add_file -verilog "../../rtl/verilog/crtc_iob.v"
|
63 |
|
|
add_file -verilog "../../rtl/verilog/ssvga_crtc.v"
|
64 |
|
|
add_file -verilog "../../rtl/verilog/ssvga_fifo.v"
|
65 |
|
|
add_file -verilog "../../rtl/verilog/ssvga_top.v"
|
66 |
|
|
add_file -verilog "../../rtl/verilog/ssvga_wbm_if.v"
|
67 |
|
|
add_file -verilog "../../rtl/verilog/ssvga_wbs_if.v"
|
68 |
|
|
add_file -constraint "pci_crt.sdc"
|
69 |
|
|
add_file -verilog "/shared/projects/pci/mihad/pci/rtl/verilog/meta_flop.v"
|
70 |
|
|
add_file -verilog "../../rtl/verilog/top.v"
|
71 |
|
|
|
72 |
|
|
#reporting options
|
73 |
|
|
|
74 |
|
|
|
75 |
|
|
#implementation: "rev_1"
|
76 |
|
|
impl -add rev_1
|
77 |
|
|
|
78 |
|
|
#device options
|
79 |
|
|
set_option -technology SPARTAN2
|
80 |
|
|
set_option -part XC2S150
|
81 |
|
|
set_option -package PQ208
|
82 |
|
|
set_option -speed_grade -5
|
83 |
|
|
|
84 |
|
|
#compilation/mapping options
|
85 |
|
|
set_option -default_enum_encoding default
|
86 |
|
|
set_option -symbolic_fsm_compiler 0
|
87 |
|
|
set_option -resource_sharing 0
|
88 |
|
|
set_option -use_fsm_explorer 0
|
89 |
|
|
|
90 |
|
|
#map options
|
91 |
|
|
set_option -frequency 50.000
|
92 |
|
|
set_option -fanout_limit 50
|
93 |
|
|
set_option -disable_io_insertion 0
|
94 |
|
|
set_option -pipe 0
|
95 |
|
|
set_option -fixgatedclocks 0
|
96 |
|
|
set_option -retiming 0
|
97 |
|
|
set_option -modular 0
|
98 |
|
|
|
99 |
|
|
#simulation options
|
100 |
|
|
set_option -write_verilog 0
|
101 |
|
|
set_option -write_vhdl 0
|
102 |
|
|
|
103 |
|
|
#automatic place and route (vendor) options
|
104 |
|
|
set_option -write_apr_constraint 1
|
105 |
|
|
|
106 |
|
|
#set result format/file last
|
107 |
|
|
project -result_file "rev_1/top.edf"
|
108 |
|
|
|
109 |
|
|
#implementation attributes
|
110 |
|
|
set_option -vlog_std v95
|
111 |
|
|
set_option -compiler_compatible 0
|
112 |
|
|
set_option -random_floorplan 0
|
113 |
|
|
set_option -include_path "../../../../rtl/verilog/;../../rtl/verilog/"
|
114 |
|
|
|
115 |
|
|
#netlist optimizer options
|
116 |
|
|
set_option -enable_nfilter 0
|
117 |
|
|
set_option -feedthrough 1
|
118 |
|
|
set_option -constant_prop 1
|
119 |
|
|
set_option -level_hierarchy 0
|
120 |
|
|
|
121 |
|
|
#physical constraint options
|
122 |
|
|
set_option -floorplan ""
|
123 |
|
|
set_option -nfilter_user_path ""
|
124 |
|
|
set_option -pin_assignment ""
|
125 |
|
|
impl -active "rev_1"
|