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##############################################
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# BASIC UCF SYNTAX EXAMPLES V2.1.6 #
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##############################################
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#
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# The "#" symbol is a comment character. To use this sample file, find the
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# specification necessary, remove the comment character (#) from the beginning
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# of the line, and modify the line (if necessary) to fit your design.
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#
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# TIMING SPECIFICATIONS
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#
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# Timing specifications can be applied to the entire device (global) or to
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# specific groups in your design (called "time groups'). The time groups are
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# declared in two basic ways.
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#
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# Method 1: Based on a net name, where 'my_net' is a net that touches all the
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# logic to be grouped in to 'logic_grp'. Example:
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#NET my_net TNM_NET = logic_grp ;
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#
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# Method 2: Group using the key word 'TIMEGRP' and declare using the names of
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# logic in your design. Example:
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#TIMEGRP group_name = FFS ("U1/*");
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# creates a group called 'group_name' for all flip-flops within
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# the hierarchical block called U1. Wildcards are valid.
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#
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# Grouping is very important because it lets you tell the software which parts
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# of a design run at which speeds. For the majority of the designs with only
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# one clock, use simple global constraints.
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#
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# The type of grouping constraint you use can vary depending on the synthesis
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# tools you are using. Foundation Express does better with Method 2.
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#
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#
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############################################################
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# Internal to the device clock speed specifications - Tsys #
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############################################################
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#
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# data _________ /^^^^^\ _________ out
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# ----------| D Q |-----{ LOGIC } -----| D Q |------
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# | | \vvvvv/ | |
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# ---|> CLK | ---|> CLK |
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# clock | --------- | ---------
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# ------------------------------------
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#
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# ---------------
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# Single Clock
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# ---------------
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#
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# ----------------
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# PERIOD TIME-SPEC
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# ----------------
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# The PERIOD spec. covers all timing paths that start or end at a
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# register, latch, or synchronous RAM which are clocked by the reference
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# net (excluding pad destinations). Also covered is the setup
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# requirement of the synchronous element relative to other elements
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# (ex. flip flops, pads, etc...).
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# NOTE: The default unit for time is nanoseconds.
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#
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#NET clock PERIOD = 50ns ;
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#
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# -OR-
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#
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# ------------------
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# FROM:TO TIME-SPECs
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# ------------------
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# FROM:TO style timespecs can be used to constrain paths between time
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# groups. NOTE: Keywords: RAMS, FFS, PADS, and LATCHES are predefined
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# time groups used to specify all elements of each type in a design.
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#TIMEGRP RFFS = RISING FFS ("*"); // creates a rising group called RFFS
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#TIMEGRP FFFS = FALLING FFS ("*"); // creates a falling group called FFFS
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#TIMESPEC TSF2F = FROM : FFS : TO : FFS : 50 ns; // Flip-flips with the same edge
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#TIMESPEC TSR2F = FROM : RFFS : TO : FFFS : 25 ns; // rising edge to falling edge
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#TIMESPEC TSF2R = FROM : FFFS : TO : RFFS : 25 ns; // falling edge to rising edge
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#
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# ---------------
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# Multiple Clocks
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# ---------------
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# Requires a combination of the 'Period' and 'FROM:TO' type time specifications
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#NET clock1 TNM_NET = clk1_grp ;
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#NET clock2 TNM_NET = clk2_grp ;
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#
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#TIMESPEC TS_clk1 = PERIOD : clk1_grp : 50 ;
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#TIMESPEC TS_clk2 = PERIOD : clk2_grp : 30 ;
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#TIMESPEC TS_ck1_2_ck2 = FROM : clk1_grp : TO : clk2_grp : 50 ;
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#TIMESPEC TS_ck2_2_ck1 = FROM : clk2_grp : TO : clk1_grp : 30 ;
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#
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#
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############################################################
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# CLOCK TO OUT specifications - Tco #
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############################################################
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#
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# from _________ /^^^^^\ --------\
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# ----------| D Q |-----{ LOGIC } -----| Pad >
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# PLD | | \vvvvv/ --------/
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# ---|> CLK |
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# clock | ---------
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# --------
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#
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# ----------------
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# OFFSET TIME-SPEC
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# ----------------
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# To automatically include clock buffer/routing delay in your
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# clock-to-out timing specifications, use OFFSET constraints .
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# For an output where the maximum clock-to-out (Tco) is 25 ns:
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#
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#NET out_net_name OFFSET = OUT 25 AFTER clock_net_name ;
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#
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# -OR-
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#
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# ------------------
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# FROM:TO TIME-SPECs
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# ------------------
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#TIMESPEC TSF2P = FROM : FFS : TO : PADS : 25 ns;
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# Note that FROM: FFS : TO: PADS constraints start the delay analysis
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# at the flip flop itself, and not the clock input pin. The recommended
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# method to create a clock-to-out constraint is to use an OFFSET constraint.
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#
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#
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############################################################
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# Pad to Flip-Flop speed specifications - Tsu #
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############################################################
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#
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# ------\ /^^^^^\ _________ into PLD
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# |pad >-------{ LOGIC } -----| D Q |------
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# ------/ \vvvvv/ | |
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# ---|> CLK |
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# clock | ---------
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# ----------------------------
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#
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# ----------------
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# OFFSET TIME-SPEC
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# ----------------
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# To automatically account for clock delay in your input setup timing
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# specifications, use OFFSET constraints.
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# For an input where the maximum setup time is 25 ns:
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#NET in_net_name OFFSET = IN 25 BEFORE clock_net_name ;
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#
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# -OR-
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#
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# ------------------
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# FROM:TO TIME-SPECs
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# ------------------
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#TIMESPEC TSP2F = FROM : PADS : TO : FFS : 25 ns;
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# Note that FROM: PADS : TO: FFS constraints do not take into account any
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# delay for the clock path. The recommended method to create an input
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# setup time constraint is to use an OFFSET constraint.
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#
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#
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############################################################
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# Pad to Pad speed specifications - Tpd #
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############################################################
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#
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# ------\ /^^^^^\ -------\
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# |pad >-------{ LOGIC } -----| pad >
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# ------/ \vvvvv/ -------/
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#
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# ------------------
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# FROM:TO TIME-SPECs
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# ------------------
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#TIMESPEC TSP2P = FROM : PADS : TO : PADS : 125 ns;
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#
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#
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############################################################
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# Other timing specifications #
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############################################################
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#
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# -------------
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# TIMING IGNORE
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# -------------
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# If you can ignore timing of paths, use Timing Ignore (TIG). NOTE: The
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# "*" character is a wild card, which can be used for bus names. A "?"
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# character can be used to wild-card one character.
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# Ignore timing of net reset_n:
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#NET : reset_n : TIG ;
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#
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# Ignore data_reg(7:0) net in instance mux_mem:
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#NET : mux_mem/data_reg* : TIG ;
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#
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# Ignore data_reg(7:0) net in instance mux_mem as related to a TIMESPEC
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# named TS01 only:
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#NET : mux_mem/data_reg* : TIG = TS01 ;
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#
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# Ignore data1_sig and data2_sig nets:
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#NET : data?_sig : TIG ;
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#
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# ---------------
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# PATH EXCEPTIONS
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# ---------------
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# If your design has outputs that can be slower than others, you can
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# create specific timespecs similar to this example for output nets
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# named out_data(7:0) and irq_n:
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#TIMEGRP slow_outs = PADS(out_data* : irq_n) ;
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#TIMEGRP fast_outs = PADS : EXCEPT : slow_outs ;
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#TIMESPEC TS08 = FROM : FFS : TO : fast_outs : 22 ;
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#TIMESPEC TS09 = FROM : FFS : TO : slow_outs : 75 ;
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#
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# If you have multi-cycle FF to FF paths, you can create a time group
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# using either the TIMEGRP or TNM statements.
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#
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# WARNING: Many VHDL/Verilog synthesizers do not predictably name flip
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# flop Q output nets. Most synthesizers do assign predictable instance
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# names to flip flops, however.
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#
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# TIMEGRP example:
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#TIMEGRP slowffs = FFS(inst_path/ff_q_output_net1* :
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#inst_path/ff_q_output_net2*);
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#
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# TNM attached to instance example:
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#INST inst_path/ff_instance_name1_reg* TNM = slowffs ;
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#INST inst_path/ff_instance_name2_reg* TNM = slowffs ;
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#
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# If a FF clock-enable is used on all flip flops of a multi-cycle path,
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# you can attach TNM to the clock enable net. NOTE: TNM attached to a
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# net "forward traces" to any FF, LATCH, RAM, or PAD attached to the
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# net.
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#NET ff_clock_enable_net TNM = slowffs ;
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#
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# Example of using "slowffs" timegroup, in a FROM:TO timespec, with
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# either of the three timegroup methods shown above:
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#TIMESPEC TS10 = FROM : slowffs : TO : FFS : 100 ;
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#
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# Constrain the skew or delay associate with a net.
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#NET any_net_name MAXSKEW = 7 ;
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#NET any_net_name MAXDELAY = 20 ns;
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#
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#
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# Constraint priority in your .ucf file is as follows:
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#
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# highest 1. Timing Ignore (TIG)
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# 2. FROM : THRU : TO specs
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# 3. FROM : TO specs
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# lowest 4. PERIOD specs
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#
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# See the on-line "Library Reference Guide" document for
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# additional timespec features and more information.
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#
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#
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############################################################
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# #
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# LOCATION and ATTRIBUTE SPECIFICATIONS #
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# #
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############################################################
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# Pin and CLB location locking constraints #
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############################################################
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#
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# -----------------------
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# Assign an IO pin number
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# -----------------------
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#INST io_buf_instance_name LOC = P110 ;
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#NET io_net_name LOC = P111 ;
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#
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# -----------------------
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# Assign a signal to a range of I/O pins
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# -----------------------
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#NET "signal_name" LOC=P32, P33, P34;
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#
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# -----------------------
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# Place a logic element(called a BEL) in a specific CLB location.
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# BEL = FF, LUT, RAM, etc...
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# -----------------------
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#INST instance_path/BEL_inst_name LOC = CLB_R17C36 ;
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#
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# -----------------------
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# Place CLB in rectangular area from CLB R1C1 to CLB R5C7
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# -----------------------
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#INST /U1/U2/reg<0> LOC=clb_r1c1:clb_r5c7;
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#
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# -----------------------
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# Place hierarchical logic block in rectangular area from CLB R1C1 to CLB R5C7
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# -----------------------
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#INST /U1* LOC=clb_r1c1:clb_r5c7;
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#
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# -----------------------
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# Prohibit IO pin P26 or CLBR5C3 from being used:
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# -----------------------
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#CONFIG PROHIBIT = P26 ;
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#CONFIG PROHIBIT = CLB_R5C3 ;
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# Config Prohibit is very important for forcing the software to not use critical
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# configuration pins like INIT or DOUT on the FPGA. The Mode pins and JTAG
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# Pins require a special pad so they will not be available to this constraint
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#
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# -----------------------
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# Assign an OBUF to be FAST or SLOW:
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# -----------------------
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#INST obuf_instance_name FAST ;
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#INST obuf_instance_name SLOW ;
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#
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# -----------------------
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# FPGAs only: IOB input Flip-flop delay specification
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# -----------------------
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# Declare an IOB input FF delay (default = MAXDELAY).
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# NOTE: MEDDELAY/NODELAY can be attached to a CLB FF that is pushed
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# into an IOB by the "map -pr i" option.
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#INST input_ff_instance_name MEDDELAY ;
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#INST input_ff_instance_name NODELAY ;
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#
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# -----------------------
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# Assign Global Clock Buffers Lower Left Right Side
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# -----------------------
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# INST gbuf1 LOC=SSW
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#
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# #
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# define a group of metastable Flip-Flops
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INST *sync_data_out* TNM = sync_ffs ;
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TIMESPEC TS_sync_flops = FROM : sync_ffs : TO : FFS : 15 ;
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INST *meta_q_o* TNM = meta_ffs ;
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TIMESPEC TS_meta_flops = FROM : meta_ffs : TO : FFS : 15 ;
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NET CLK TNM_NET = CLK_GRP ;
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NET CRT_CLK TNM_NET = CRT_CLK_GRP ;
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TIMESPEC TS_CLK_2_CRT_CLK = FROM : CLK_GRP : TO : CRT_CLK_GRP : 15 ;
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TIMESPEC TS_CRT_CLK_2_CLK = FROM : CRT_CLK_GRP : TO : CLK_GRP : 15 ;
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NET "AD0" IOSTANDARD = PCI33_5;
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NET "AD1" IOSTANDARD = PCI33_5;
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NET "AD2" IOSTANDARD = PCI33_5;
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NET "AD3" IOSTANDARD = PCI33_5;
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NET "AD4" IOSTANDARD = PCI33_5;
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NET "AD5" IOSTANDARD = PCI33_5;
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NET "AD6" IOSTANDARD = PCI33_5;
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NET "AD7" IOSTANDARD = PCI33_5;
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NET "AD8" IOSTANDARD = PCI33_5;
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NET "AD9" IOSTANDARD = PCI33_5;
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NET "AD10" IOSTANDARD = PCI33_5;
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NET "AD11" IOSTANDARD = PCI33_5;
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NET "AD12" IOSTANDARD = PCI33_5;
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NET "AD13" IOSTANDARD = PCI33_5;
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NET "AD14" IOSTANDARD = PCI33_5;
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NET "AD15" IOSTANDARD = PCI33_5;
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NET "AD16" IOSTANDARD = PCI33_5;
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NET "AD17" IOSTANDARD = PCI33_5;
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334 |
|
|
NET "AD18" IOSTANDARD = PCI33_5;
|
335 |
|
|
NET "AD19" IOSTANDARD = PCI33_5;
|
336 |
|
|
NET "AD20" IOSTANDARD = PCI33_5;
|
337 |
|
|
NET "AD21" IOSTANDARD = PCI33_5;
|
338 |
|
|
NET "AD22" IOSTANDARD = PCI33_5;
|
339 |
|
|
NET "AD23" IOSTANDARD = PCI33_5;
|
340 |
|
|
NET "AD24" IOSTANDARD = PCI33_5;
|
341 |
|
|
NET "AD25" IOSTANDARD = PCI33_5;
|
342 |
|
|
NET "AD26" IOSTANDARD = PCI33_5;
|
343 |
|
|
NET "AD27" IOSTANDARD = PCI33_5;
|
344 |
|
|
NET "AD28" IOSTANDARD = PCI33_5;
|
345 |
|
|
NET "AD29" IOSTANDARD = PCI33_5;
|
346 |
|
|
NET "AD30" IOSTANDARD = PCI33_5;
|
347 |
|
|
NET "AD31" IOSTANDARD = PCI33_5;
|
348 |
|
|
|
349 |
|
|
NET "CBE0" IOSTANDARD = PCI33_5;
|
350 |
|
|
NET "CBE1" IOSTANDARD = PCI33_5;
|
351 |
|
|
NET "CBE2" IOSTANDARD = PCI33_5;
|
352 |
|
|
NET "CBE3" IOSTANDARD = PCI33_5;
|
353 |
|
|
|
354 |
|
|
NET "DEVSEL" IOSTANDARD = PCI33_5;
|
355 |
|
|
|
356 |
|
|
NET "FRAME" IOSTANDARD = PCI33_5;
|
357 |
|
|
|
358 |
|
|
NET "GNT" IOSTANDARD = PCI33_5;
|
359 |
|
|
NET "RST" IOSTANDARD = PCI33_5;
|
360 |
|
|
NET "INTA" IOSTANDARD = PCI33_5;
|
361 |
|
|
|
362 |
|
|
NET "IRDY" IOSTANDARD = PCI33_5;
|
363 |
|
|
|
364 |
|
|
NET "PAR" IOSTANDARD = PCI33_5;
|
365 |
|
|
|
366 |
|
|
NET "PERR" IOSTANDARD = PCI33_5;
|
367 |
|
|
|
368 |
|
|
NET "REQ" IOSTANDARD = PCI33_5;
|
369 |
|
|
|
370 |
|
|
NET "SERR" IOSTANDARD = PCI33_5;
|
371 |
|
|
|
372 |
|
|
NET "STOP" IOSTANDARD = PCI33_5;
|
373 |
|
|
|
374 |
|
|
NET "TRDY" IOSTANDARD = PCI33_5;
|
375 |
|
|
|
376 |
|
|
NET "IDSEL" IOSTANDARD = PCI33_5;
|