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[/] [pci/] [tags/] [rel_9/] [bench/] [verilog/] [pci_bus_monitor.v] - Blame information for rev 15

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1 15 mihad 
//===========================================================================
2 
// $Id: pci_bus_monitor.v,v 1.1 2002-02-01 13:39:43 mihad Exp $
3 
//
4 
// Copyright 2001 Blue Beaver.  All Rights Reserved.
5 
//
6 
// Summary:  Watch the PCI Bus Wires to try to see Protocol Errors.
7 
//           This module also has access to the individual PCI Bus OE
8 
//           signals for each interface (either through extra output
9 
//           ports or through "." notation), and it can see when more
10 
//           than one interface is driving the bus, even if the values
11 
//           are the same.
12 
//           A future version of this module should write out a transcript
13 
//           of the activity seen on the PCI Bus.
14 
//
15 
// This library is free software; you can distribute it and/or modify it
16 
// under the terms of the GNU Lesser General Public License as published
17 
// by the Free Software Foundation; either version 2.1 of the License, or
18 
// (at your option) any later version.
19 
//
20 
// This library is distributed in the hope that it will be useful, but
21 
// WITHOUT ANY WARRANTY; without even the implied warranty of
22 
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
23 
// See the GNU Lesser General Public License for more details.
24 
//
25 
// You should have received a copy of the GNU Lesser General Public License
26 
// along with this library.  If not, write to
27 
// Free Software Foundation, Inc.
28 
// 59 Temple Place, Suite 330
29 
// Boston, MA 02111-1307 USA
30 
//
31 
// Author's note about this license:  The intention of the Author and of
32 
// the Gnu Lesser General Public License is that users should be able to
33 
// use this code for any purpose, including combining it with other source
34 
// code, combining it with other logic, translated it into a gate-level
35 
// representation, or projected it into gates in a programmable or
36 
// hardwired chip, as long as the users of the resulting source, compiled
37 
// source, or chip are given the means to get a copy of this source code
38 
// with no new restrictions on redistribution of this source.
39 
//
40 
// If you make changes, even substantial changes, to this code, or use
41 
// substantial parts of this code as an inseparable part of another work
42 
// of authorship, the users of the resulting IP must be given the means
43 
// to get a copy of the modified or combined source code, with no new
44 
// restrictions on redistribution of the resulting source.
45 
//
46 
// Separate parts of the combined source code, compiled code, or chip,
47 
// which are NOT derived from this source code do NOT need to be offered
48 
// to the final user of the chip merely because they are used in
49 
// combination with this code.  Other code is not forced to fall under
50 
// the GNU Lesser General Public License when it is linked to this code.
51 
// The license terms of other source code linked to this code might require
52 
// that it NOT be made available to users.  The GNU Lesser General Public
53 
// License does not prevent this code from being used in such a situation,
54 
// as long as the user of the resulting IP is given the means to get a
55 
// copy of this component of the IP with no new restrictions on
56 
// redistribution of this source.
57 
//
58 
// This code was developed using VeriLogger Pro, by Synapticad.
59 
// Their support is greatly appreciated.
60 
//
61 
// NOTE:  This module watches the PCI bus and gives commentary about what
62 
//        it sees.
63 
//        I hope that this can get a parameter which says whether to put
64 
//        its log in a file, on the terminal, or both.
65 
//
66 
// TO DO: create code to act on MONITOR_CREATE_BUS_ACTIVITY_TRANSCRIPT
67 
//
68 
//===========================================================================
69 
 
70 
// Note that master aborts are the norm on Special Cycles!
71 
 
72 
`timescale 1ns/10ps
73 
 
74 
module pci_bus_monitor (
75 
  pci_ext_ad, pci_ext_cbe_l, pci_ext_par,
76 
  pci_ext_frame_l, pci_ext_irdy_l,
77 
  pci_ext_devsel_l, pci_ext_trdy_l, pci_ext_stop_l,
78 
  pci_ext_perr_l, pci_ext_serr_l,
79 
  pci_real_req_l, pci_real_gnt_l,
80 
  pci_ext_req_l, pci_ext_gnt_l,
81 
  test_error_event, test_observe_r_oe_sigs,
82 
  test_observe_0_oe_sigs, test_observe_1_oe_sigs,
83 
  test_observe_2_oe_sigs, test_observe_3_oe_sigs,
84 
  pci_ext_reset_l, pci_ext_clk,
85 
  log_file_desc
86 
);
87 
 
88 
`include "pci_blue_options.vh"
89 
`include "pci_blue_constants.vh"
90 
 
91 
  input  [PCI_BUS_DATA_RANGE:0] pci_ext_ad;
92 
  input  [PCI_BUS_CBE_RANGE:0] pci_ext_cbe_l;
93 
  input   pci_ext_par;
94 
  input   pci_ext_frame_l, pci_ext_irdy_l;
95 
  input   pci_ext_devsel_l, pci_ext_trdy_l, pci_ext_stop_l;
96 
  input   pci_ext_perr_l, pci_ext_serr_l;
97 
  input   pci_real_req_l, pci_real_gnt_l;
98 
  input  [3:0] pci_ext_req_l;
99 
  input  [3:0] pci_ext_gnt_l;
100 
  output  test_error_event;
101 
  input  [5:0] test_observe_r_oe_sigs;
102 
  input  [5:0] test_observe_0_oe_sigs;
103 
  input  [5:0] test_observe_1_oe_sigs;
104 
  input  [5:0] test_observe_2_oe_sigs;
105 
  input  [5:0] test_observe_3_oe_sigs;
106 
 
107 
  input   pci_ext_reset_l, pci_ext_clk;
108 
 
109 
  input [31:0] log_file_desc ;
110 
// Make temporary Bip every time an error is detected
111 
  reg     test_error_event;
112 
  initial test_error_event <= 1'bZ;
113 
  reg     error_detected;
114 
  initial error_detected <= 1'b0;
115 
  always @(error_detected)
116 
  begin
117 
    test_error_event <= 1'b0;
118 
    #2;
119 
    test_error_event <= 1'bZ;
120 
  end
121 
 
122 
// watch for the PCI Clock going X
123 
  always @(pci_ext_clk)
124 
  begin
125 
    if (($time > 0) && ((pci_ext_clk ^ pci_ext_clk) === 1'bx))
126 
    begin
127 
      $display ("*** monitor - PCI External Clock invalid 'h%x, at %t",
128 
                  pci_ext_clk, $time);
129 
      $fdisplay (log_file_desc, "*** monitor - PCI External Clock invalid 'h%x, at %t",
130 
                  pci_ext_clk, $time);
131 
      error_detected <= ~error_detected;
132 
    end
133 
    `NO_ELSE;
134 
  end
135 
 
136 
// watch for the Reset signal going X
137 
  always @(pci_ext_reset_l)
138 
  begin
139 
    if (($time > 0) & ((pci_ext_reset_l ^ pci_ext_reset_l) === 1'bx))
140 
    begin
141 
      $display ("*** monitor - PCI External RESET_L invalid 'h%x, at %t",
142 
                  pci_ext_reset_l, $time);
143 
      $fdisplay (log_file_desc, "*** monitor - PCI External RESET_L invalid 'h%x, at %t",
144 
                  pci_ext_reset_l, $time);
145 
      error_detected <= ~error_detected;
146 
    end
147 
    `NO_ELSE;
148 
  end
149 
 
150 
// Make sure all PCI signals are HIGH-Z or Deasserted HIGH as needed
151 
//   when the external PCI bus leaves reset.
152 
// The values of some signals are set by pullups on the PC board
153 
  always @(posedge pci_ext_reset_l)
154 
  begin
155 
  if ($time > 0)
156 
    begin
157 
      if (pci_ext_ad[PCI_BUS_DATA_RANGE:0] !== `PCI_BUS_DATA_Z)
158 
      begin
159 
        $display ("*** monitor - PCI External AD not high-Z 'h%x, at %t",
160 
                    pci_ext_ad[PCI_BUS_DATA_RANGE:0], $time);
161 
        $fdisplay (log_file_desc, "*** monitor - PCI External AD not high-Z 'h%x, at %t",
162 
                    pci_ext_ad[PCI_BUS_DATA_RANGE:0], $time);
163 
        error_detected <= ~error_detected;
164 
      end
165 
      `NO_ELSE;
166 
      if (pci_ext_cbe_l[PCI_BUS_CBE_RANGE:0] !== `PCI_BUS_CBE_Z)
167 
      begin
168 
        $display ("*** monitor - PCI External CBE_L not high-Z 'h%x, at %t",
169 
                    pci_ext_cbe_l[PCI_BUS_CBE_RANGE:0], $time);
170 
        $fdisplay (log_file_desc, "*** monitor - PCI External CBE_L not high-Z 'h%x, at %t",
171 
                    pci_ext_cbe_l[PCI_BUS_CBE_RANGE:0], $time);
172 
        error_detected <= ~error_detected;
173 
      end
174 
      `NO_ELSE;
175 
      if (pci_ext_par !== 1'bz)
176 
      begin
177 
        $display ("*** monitor - PCI External PAR not high-Z 'h%x, at %t",
178 
                    pci_ext_par, $time);
179 
        $fdisplay (log_file_desc, "*** monitor - PCI External PAR not high-Z 'h%x, at %t",
180 
                    pci_ext_par, $time);
181 
        error_detected <= ~error_detected;
182 
      end
183 
      `NO_ELSE;
184 
      if (pci_ext_frame_l !== 1'b1)
185 
      begin
186 
        $display ("*** monitor - PCI External FRAME_L invalid 'h%x, at %t",
187 
                    pci_ext_frame_l, $time);
188 
        $fdisplay (log_file_desc, "*** monitor - PCI External FRAME_L invalid 'h%x, at %t",
189 
                    pci_ext_frame_l, $time);
190 
        error_detected <= ~error_detected;
191 
      end
192 
      `NO_ELSE;
193 
      if (pci_ext_irdy_l !== 1'b1)
194 
      begin
195 
        $display ("*** monitor - PCI External IRDY_L invalid 'h%x, at %t",
196 
                    pci_ext_irdy_l, $time);
197 
        $fdisplay (log_file_desc, "*** monitor - PCI External IRDY_L invalid 'h%x, at %t",
198 
                    pci_ext_irdy_l, $time);
199 
        error_detected <= ~error_detected;
200 
      end
201 
      `NO_ELSE;
202 
      if (pci_ext_devsel_l !== 1'b1)
203 
      begin
204 
        $display ("*** monitor - PCI External DEVSEL_L invalid 'h%x, at %t",
205 
                    pci_ext_devsel_l, $time);
206 
        $fdisplay (log_file_desc, "*** monitor - PCI External DEVSEL_L invalid 'h%x, at %t",
207 
                    pci_ext_devsel_l, $time);
208 
        error_detected <= ~error_detected;
209 
      end
210 
      `NO_ELSE;
211 
      if (pci_ext_trdy_l !== 1'b1)
212 
      begin
213 
        $display ("*** monitor - PCI External TRDY_L invalid 'h%x, at %t",
214 
                    pci_ext_trdy_l, $time);
215 
        $fdisplay (log_file_desc, "*** monitor - PCI External TRDY_L invalid 'h%x, at %t",
216 
                    pci_ext_trdy_l, $time);
217 
        error_detected <= ~error_detected;
218 
      end
219 
      `NO_ELSE;
220 
      if (pci_ext_stop_l !== 1'b1)
221 
      begin
222 
        $display ("*** monitor - PCI External STOP_L invalid 'h%x, at %t",
223 
                    pci_ext_stop_l, $time);
224 
        $fdisplay (log_file_desc, "*** monitor - PCI External STOP_L invalid 'h%x, at %t",
225 
                    pci_ext_stop_l, $time);
226 
        error_detected <= ~error_detected;
227 
      end
228 
      `NO_ELSE;
229 
      if (pci_ext_perr_l !== 1'b1)
230 
      begin
231 
        $display ("*** monitor - PCI External PERR_L invalid 'h%x, at %t",
232 
                    pci_ext_perr_l, $time);
233 
        $fdisplay (log_file_desc, "*** monitor - PCI External PERR_L invalid 'h%x, at %t",
234 
                    pci_ext_perr_l, $time);
235 
        error_detected <= ~error_detected;
236 
      end
237 
      `NO_ELSE;
238 
      if (pci_ext_serr_l !== 1'b1)
239 
      begin
240 
        $display ("*** monitor - PCI External SERR_L invalid 'h%x, at %t",
241 
                    pci_ext_serr_l, $time);
242 
        $fdisplay (log_file_desc, "*** monitor - PCI External SERR_L invalid 'h%x, at %t",
243 
                    pci_ext_serr_l, $time);
244 
        error_detected <= ~error_detected;
245 
      end
246 
      `NO_ELSE;
247 
      if (pci_real_req_l !== 1'b1)
248 
      begin
249 
        $display ("*** monitor - PCI Internal REQ_L invalid 'h%x, at %t",
250 
                    pci_real_req_l, $time);
251 
        $fdisplay (log_file_desc, "*** monitor - PCI Internal REQ_L invalid 'h%x, at %t",
252 
                    pci_real_req_l, $time);
253 
        error_detected <= ~error_detected;
254 
      end
255 
      `NO_ELSE;
256 
      if (pci_real_gnt_l !== 1'b1)
257 
      begin
258 
        $display ("*** monitor - PCI Internal GNT_L invalid 'h%x, at %t",
259 
                    pci_real_gnt_l, $time);
260 
        $fdisplay (log_file_desc, "*** monitor - PCI Internal GNT_L invalid 'h%x, at %t",
261 
                    pci_real_gnt_l, $time);
262 
        error_detected <= ~error_detected;
263 
      end
264 
      `NO_ELSE;
265 
      if (pci_ext_req_l[3:0] !== 4'hF)
266 
      begin
267 
        $display ("*** monitor - PCI External REQ_L invalid 'h%x, at %t",
268 
                    pci_ext_req_l[3:0], $time);
269 
        $fdisplay (log_file_desc, "*** monitor - PCI External REQ_L invalid 'h%x, at %t",
270 
                    pci_ext_req_l[3:0], $time);
271 
        error_detected <= ~error_detected;
272 
      end
273 
      `NO_ELSE;
274 
      if (pci_ext_gnt_l[3:0] !== 4'hF)
275 
      begin
276 
        $display ("*** monitor - PCI External GNT_L invalid 'h%x, at %t",
277 
                    pci_ext_gnt_l[3:0], $time);
278 
        $fdisplay (log_file_desc, "*** monitor - PCI External GNT_L invalid 'h%x, at %t",
279 
                    pci_ext_gnt_l[3:0], $time);
280 
        error_detected <= ~error_detected;
281 
      end
282 
      `NO_ELSE;
283 
    end
284 
    `NO_ELSE;
285 
  end
286 
 
287 
task Watch_For_X_On_OE_Sigs;
288 
  input  [2:0] signal_source;
289 
  input  [5:0] oe_signals;
290 
  begin
291 
    if ((^oe_signals[5:0]) === 1'bX)
292 
    begin
293 
      if (signal_source[2:0] == `Test_Master_Real)
294 
      begin
295 
        $display ("*** monitor - PCI Real OE signals have X's {F, I, D_T_S, AD, CBE, PERR} 'b%b, at %t",
296 
                    oe_signals[5:0], $time);
297 
        $fdisplay (log_file_desc, "*** monitor - PCI Real OE signals have X's {F, I, D_T_S, AD, CBE, PERR} 'b%b, at %t",
298 
                    oe_signals[5:0], $time);
299 
      end
300 
      else
301 
      begin
302 
        $display ("*** monitor - PCI Test %h OE signals have X's {F, I, D_T_S, AD, CBE, PERR} 'b%b, at %t",
303 
                    signal_source[2:0], oe_signals[5:0], $time);
304 
        $fdisplay (log_file_desc, "*** monitor - PCI Test %h OE signals have X's {F, I, D_T_S, AD, CBE, PERR} 'b%b, at %t",
305 
                    signal_source[2:0], oe_signals[5:0], $time);
306 
        error_detected <= ~error_detected;
307 
      end
308 
    end
309 
    `NO_ELSE;
310 
  end
311 
endtask
312 
 
313 
task Watch_For_Simultaneous_Drive_Of_OE_Sigs;
314 
  input  [2:0] signal_source_0;
315 
  input  [2:0] signal_source_1;
316 
  input  [5:0] oe_signals_0;
317 
  input  [5:0] oe_signals_1;
318 
  begin
319 
    if ((oe_signals_0 & oe_signals_1) !== 6'h00)
320 
    begin
321 
      if (signal_source_0[2:0] == `Test_Master_Real)
322 
      begin
323 
        $display ("*** monitor - PCI Real and Test %x drive bus simultaneously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
324 
                    signal_source_1[2:0], oe_signals_0[5:0],
325 
                    oe_signals_1[5:0], $time);
326 
        $fdisplay (log_file_desc, "*** monitor - PCI Real and Test %x drive bus simultaneously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
327 
                    signal_source_1[2:0], oe_signals_0[5:0],
328 
                    oe_signals_1[5:0], $time);
329 
      end
330 
      else if (signal_source_1[2:0] == `Test_Master_Real)
331 
      begin
332 
        $display ("*** monitor - PCI Test %x and Real drive bus simultaneously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
333 
                    signal_source_0[2:0], oe_signals_0[5:0],
334 
                    oe_signals_1[5:0], $time);
335 
        $fdisplay (log_file_desc, "*** monitor - PCI Test %x and Real drive bus simultaneously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
336 
                    signal_source_0[2:0], oe_signals_0[5:0],
337 
                    oe_signals_1[5:0], $time);
338 
      end
339 
      else
340 
      begin
341 
        $display ("*** monitor - PCI Test %x and Test %h drive bus simultaneously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
342 
                    signal_source_0[2:0], signal_source_1[1:0],
343 
                    oe_signals_0[5:0], oe_signals_1[5:0], $time);
344 
        $fdisplay (log_file_desc, "*** monitor - PCI Test %x and Test %h drive bus simultaneously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
345 
                    signal_source_0[2:0], signal_source_1[1:0],
346 
                    oe_signals_0[5:0], oe_signals_1[5:0], $time);
347 
      end
348 
      error_detected <= ~error_detected;
349 
    end
350 
    `NO_ELSE;
351 
  end
352 
endtask
353 
 
354 
task Watch_For_Deassert_Before_Tristate ;
355 
    input [2:0] signal_source ;
356 
    input [5:0] prev_oe_sigs ;
357 
    input [5:0] current_oe_sigs ;
358 
    input       prev_perr ;
359 
    input       prev_frame ;
360 
    input       prev_irdy ;
361 
    input       prev_trdy ;
362 
    input       prev_stop ;
363 
    input       prev_devsel ;
364 
    reg         do_error ;
365 
begin
366 
    do_error = 0 ;
367 
    if ( prev_oe_sigs[0] && !current_oe_sigs[0] && prev_perr )
368 
    begin
369 
        do_error = 1 ;
370 
        if ( signal_source == `Test_Master_Real )
371 
        begin
372 
            $display("*** monitor - PCI Real Stopped driving PERR before Deasserting it for one cycle, at %t", $time) ;
373 
            $fdisplay(log_file_desc, "*** monitor - PCI Real Stopped driving PERR before Deasserting it for one cycle, at %t", $time) ;
374 
        end
375 
        else
376 
        begin
377 
            $display("*** monitor - PCI Test %x Stopped driving PERR before Deasserting it for one cycle, at %t", signal_source, $time) ;
378 
            $fdisplay(log_file_desc, "*** monitor - PCI Test %x Stopped driving PERR before Deasserting it for one cycle, at %t", signal_source, $time) ;
379 
        end
380 
    end
381 
 
382 
    if ( prev_oe_sigs[3] && !current_oe_sigs[3] && prev_stop )
383 
    begin
384 
        do_error = 1 ;
385 
        if ( signal_source == `Test_Master_Real )
386 
        begin
387 
            $display("*** monitor - PCI Real Stopped driving STOP before Deasserting it for one cycle, at %t", $time) ;
388 
            $fdisplay(log_file_desc, "*** monitor - PCI Real Stopped driving STOP before Deasserting it for one cycle, at %t", $time) ;
389 
        end
390 
        else
391 
        begin
392 
            $display("*** monitor - PCI Test %x Stopped driving STOP before Deasserting it for one cycle, at %t", signal_source, $time) ;
393 
            $fdisplay(log_file_desc, "*** monitor - PCI Test %x Stopped driving STOP before Deasserting it for one cycle, at %t", signal_source, $time) ;
394 
        end
395 
    end
396 
 
397 
    if ( prev_oe_sigs[3] && !current_oe_sigs[3] && prev_trdy )
398 
    begin
399 
        do_error = 1 ;
400 
        if ( signal_source == `Test_Master_Real )
401 
        begin
402 
            $display("*** monitor - PCI Real Stopped driving TRDY before Deasserting it for one cycle, at %t", $time) ;
403 
            $fdisplay(log_file_desc, "*** monitor - PCI Real Stopped driving TRDY before Deasserting it for one cycle, at %t", $time) ;
404 
        end
405 
        else
406 
        begin
407 
            $display("*** monitor - PCI Test %x Stopped driving TRDY before Deasserting it for one cycle, at %t", signal_source, $time) ;
408 
            $fdisplay(log_file_desc, "*** monitor - PCI Test %x Stopped driving TRDY before Deasserting it for one cycle, at %t", signal_source, $time) ;
409 
        end
410 
    end
411 
 
412 
    if ( prev_oe_sigs[3] && !current_oe_sigs[3] && prev_devsel )
413 
    begin
414 
        do_error = 1 ;
415 
        if ( signal_source == `Test_Master_Real )
416 
        begin
417 
            $display("*** monitor - PCI Real Stopped driving DEVSEL before Deasserting it for one cycle, at %t", $time) ;
418 
            $fdisplay(log_file_desc, "*** monitor - PCI Real Stopped driving DEVSEL before Deasserting it for one cycle, at %t", $time) ;
419 
        end
420 
        else
421 
        begin
422 
            $display("*** monitor - PCI Test %x Stopped driving DEVSEL before Deasserting it for one cycle, at %t", signal_source, $time) ;
423 
            $fdisplay(log_file_desc, "*** monitor - PCI Test %x Stopped driving DEVSEL before Deasserting it for one cycle, at %t", signal_source, $time) ;
424 
        end
425 
    end
426 
 
427 
    if ( prev_oe_sigs[4] && !current_oe_sigs[4] && prev_irdy )
428 
    begin
429 
        do_error = 1 ;
430 
        if ( signal_source == `Test_Master_Real )
431 
        begin
432 
            $display("*** monitor - PCI Real Stopped driving IRDY before Deasserting it for one cycle, at %t", $time) ;
433 
            $fdisplay(log_file_desc, "*** monitor - PCI Real Stopped driving IRDY before Deasserting it for one cycle, at %t", $time) ;
434 
        end
435 
        else
436 
        begin
437 
            $display("*** monitor - PCI Test %x Stopped driving IRDY before Deasserting it for one cycle, at %t", signal_source, $time) ;
438 
            $fdisplay(log_file_desc, "*** monitor - PCI Test %x Stopped driving IRDY before Deasserting it for one cycle, at %t", signal_source, $time) ;
439 
        end
440 
    end
441 
 
442 
    if ( prev_oe_sigs[5] && !current_oe_sigs[5] && prev_frame )
443 
    begin
444 
        do_error = 1 ;
445 
        if ( signal_source == `Test_Master_Real )
446 
        begin
447 
            $display("*** monitor - PCI Real Stopped driving FRAME before Deasserting it for one cycle, at %t", $time) ;
448 
            $fdisplay(log_file_desc, "*** monitor - PCI Real Stopped driving FRAME before Deasserting it for one cycle, at %t", $time) ;
449 
        end
450 
        else
451 
        begin
452 
            $display("*** monitor - PCI Test %x Stopped driving FRAME before Deasserting it for one cycle, at %t", signal_source, $time) ;
453 
            $fdisplay(log_file_desc, "*** monitor - PCI Test %x Stopped driving FRAME before Deasserting it for one cycle, at %t", signal_source, $time) ;
454 
        end
455 
    end
456 
 
457 
    if ( do_error )
458 
        error_detected <= ~error_detected ;
459 
end
460 
endtask
461 
 
462 
task Watch_For_Back_To_Back_Drive_Of_OE_Sigs;
463 
  input  [2:0] signal_source_0;
464 
  input  [2:0] signal_source_1;
465 
  input  [5:0] oe_signals_0;
466 
  input  [5:0] oe_signals_1;
467 
  begin
468 
    if ((oe_signals_0 & oe_signals_1) !== 6'h00)
469 
    begin
470 
      if (signal_source_0[2:0] == `Test_Master_Real)
471 
      begin
472 
        $display ("*** monitor - PCI Real drives when Test %x drove previously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
473 
                    signal_source_1[2:0], oe_signals_0[5:0],
474 
                    oe_signals_1[5:0], $time);
475 
        $fdisplay (log_file_desc, "*** monitor - PCI Real drives when Test %x drove previously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
476 
                    signal_source_1[2:0], oe_signals_0[5:0],
477 
                    oe_signals_1[5:0], $time);
478 
      end
479 
      else if (signal_source_1[2:0] == `Test_Master_Real)
480 
      begin
481 
        $display ("*** monitor - PCI Test %x drives when Real drove previously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
482 
                    signal_source_0[2:0], oe_signals_0[5:0],
483 
                    oe_signals_1[5:0], $time);
484 
        $fdisplay (log_file_desc, "*** monitor - PCI Test %x drives when Real drove previously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
485 
                    signal_source_0[2:0], oe_signals_0[5:0],
486 
                    oe_signals_1[5:0], $time);
487 
      end
488 
      else
489 
      begin
490 
        $display ("*** monitor - PCI Test %x drives when Test %h drove previously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
491 
                    signal_source_0[2:0], signal_source_1[1:0],
492 
                    oe_signals_0[5:0], oe_signals_1[5:0], $time);
493 
        $fdisplay (log_file_desc, "*** monitor - PCI Test %x drives when Test %h drove previously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
494 
                    signal_source_0[2:0], signal_source_1[1:0],
495 
                    oe_signals_0[5:0], oe_signals_1[5:0], $time);
496 
      end
497 
      error_detected <= ~error_detected;
498 
    end
499 
    `NO_ELSE;
500 
  end
501 
endtask
502 
 
503 
// watch for PCI devices simultaneously driving PCI wires
504 
// OE Observation signals are
505 
// {frame_oe, irdy_oe, devsel_t_s_oe, ad_oe, cbe_oe, perr_oe}
506 
// Unused ports should be wired to 0
507 
  reg    [5:0] prev_real_oe_sigs;
508 
  reg    [5:0] prev_test_0_oe_sigs;
509 
  reg    [5:0] prev_test_1_oe_sigs;
510 
  reg    [5:0] prev_test_2_oe_sigs;
511 
  reg    [5:0] prev_test_3_oe_sigs;
512 
 
513 
  // Make Asserted HIGH signals to prevent (cause?) confusion
514 
  wire    frame_now =  ~pci_ext_frame_l;
515 
  wire    irdy_now =   ~pci_ext_irdy_l;
516 
  wire    devsel_now = ~pci_ext_devsel_l;
517 
  wire    trdy_now =   ~pci_ext_trdy_l;
518 
  wire    stop_now =   ~pci_ext_stop_l;
519 
  wire    perr_now =   ~pci_ext_perr_l;
520 
// Delay PCI bus signals, used by several tests below.
521 
// Detect Address Phases on the bus.
522 
// Ignore Dual Access Cycle, as mentioned in the PCI Local Bus Spec
523 
// Revision 2.2 section 3.1.1.
524 
  reg    [4:0] grant_prev;
525 
  reg    [PCI_BUS_DATA_RANGE:0] ad_prev;
526 
  reg    [PCI_BUS_CBE_RANGE:0] cbe_l_prev;
527 
  reg     frame_prev, irdy_prev, devsel_prev, trdy_prev, stop_prev, perr_prev;
528 
  reg     address_phase_prev, read_operation_prev;
529 
 
530 
  always @(posedge pci_ext_clk or negedge pci_ext_reset_l)
531 
  begin
532 
    if (pci_ext_reset_l == 1'b0)
533 
    begin
534 
      prev_real_oe_sigs <= 6'h00;
535 
      prev_test_0_oe_sigs <= 6'h00;
536 
      prev_test_1_oe_sigs <= 6'h00;
537 
      prev_test_2_oe_sigs <= 6'h00;
538 
      prev_test_3_oe_sigs <= 6'h00;
539 
    end
540 
    else
541 
    begin
542 
      prev_real_oe_sigs <= test_observe_r_oe_sigs[5:0];
543 
      prev_test_0_oe_sigs <= test_observe_0_oe_sigs[5:0];
544 
      prev_test_1_oe_sigs <= test_observe_1_oe_sigs[5:0];
545 
      prev_test_2_oe_sigs <= test_observe_2_oe_sigs[5:0];
546 
      prev_test_3_oe_sigs <= test_observe_3_oe_sigs[5:0];
547 
    end
548 
  end
549 
 
550 
  always @(posedge pci_ext_clk)
551 
  begin
552 
    if (($time > 0) & (pci_ext_reset_l == 1'b1))
553 
    begin
554 
      Watch_For_X_On_OE_Sigs (`Test_Master_Real, test_observe_r_oe_sigs[5:0]);
555 
      Watch_For_X_On_OE_Sigs (3'h0, test_observe_0_oe_sigs[5:0]);
556 
      Watch_For_X_On_OE_Sigs (3'h1, test_observe_1_oe_sigs[5:0]);
557 
      Watch_For_X_On_OE_Sigs (3'h2, test_observe_2_oe_sigs[5:0]);
558 
      Watch_For_X_On_OE_Sigs (3'h3, test_observe_3_oe_sigs[5:0]);
559 
 
560 
      Watch_For_Simultaneous_Drive_Of_OE_Sigs (`Test_Master_Real, 3'h0,
561 
                     test_observe_r_oe_sigs[5:0], test_observe_0_oe_sigs[5:0]);
562 
      Watch_For_Simultaneous_Drive_Of_OE_Sigs (`Test_Master_Real, 3'h1,
563 
                     test_observe_r_oe_sigs[5:0], test_observe_1_oe_sigs[5:0]);
564 
      Watch_For_Simultaneous_Drive_Of_OE_Sigs (`Test_Master_Real, 3'h2,
565 
                     test_observe_r_oe_sigs[5:0], test_observe_2_oe_sigs[5:0]);
566 
      Watch_For_Simultaneous_Drive_Of_OE_Sigs (`Test_Master_Real, 3'h3,
567 
                     test_observe_r_oe_sigs[5:0], test_observe_3_oe_sigs[5:0]);
568 
 
569 
      Watch_For_Simultaneous_Drive_Of_OE_Sigs (3'h0, 3'h1,
570 
                     test_observe_0_oe_sigs[5:0], test_observe_1_oe_sigs[5:0]);
571 
      Watch_For_Simultaneous_Drive_Of_OE_Sigs (3'h0, 3'h2,
572 
                     test_observe_0_oe_sigs[5:0], test_observe_2_oe_sigs[5:0]);
573 
      Watch_For_Simultaneous_Drive_Of_OE_Sigs (3'h0, 3'h3,
574 
                     test_observe_0_oe_sigs[5:0], test_observe_3_oe_sigs[5:0]);
575 
 
576 
      Watch_For_Simultaneous_Drive_Of_OE_Sigs (3'h1, 3'h2,
577 
                     test_observe_1_oe_sigs[5:0], test_observe_2_oe_sigs[5:0]);
578 
      Watch_For_Simultaneous_Drive_Of_OE_Sigs (3'h1, 3'h3,
579 
                     test_observe_1_oe_sigs[5:0], test_observe_3_oe_sigs[5:0]);
580 
 
581 
      Watch_For_Simultaneous_Drive_Of_OE_Sigs (3'h2, 3'h3,
582 
                     test_observe_2_oe_sigs[5:0], test_observe_3_oe_sigs[5:0]);
583 
 
584 
      Watch_For_Back_To_Back_Drive_Of_OE_Sigs (`Test_Master_Real, 3'h0,
585 
                     test_observe_r_oe_sigs[5:0], prev_test_0_oe_sigs[5:0]);
586 
      Watch_For_Back_To_Back_Drive_Of_OE_Sigs (`Test_Master_Real, 3'h1,
587 
                     test_observe_r_oe_sigs[5:0], prev_test_1_oe_sigs[5:0]);
588 
      Watch_For_Back_To_Back_Drive_Of_OE_Sigs (`Test_Master_Real, 3'h2,
589 
                     test_observe_r_oe_sigs[5:0], prev_test_2_oe_sigs[5:0]);
590 
      Watch_For_Back_To_Back_Drive_Of_OE_Sigs (`Test_Master_Real, 3'h3,
591 
                     test_observe_r_oe_sigs[5:0], prev_test_3_oe_sigs[5:0]);
592 
 
593 
      Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h0, `Test_Master_Real,
594 
                     test_observe_0_oe_sigs[5:0], prev_real_oe_sigs[5:0]);
595 
      Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h0, 3'h1,
596 
                     test_observe_0_oe_sigs[5:0], prev_test_1_oe_sigs[5:0]);
597 
      Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h0, 3'h2,
598 
                     test_observe_0_oe_sigs[5:0], prev_test_2_oe_sigs[5:0]);
599 
      Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h0, 3'h3,
600 
                     test_observe_0_oe_sigs[5:0], prev_test_3_oe_sigs[5:0]);
601 
 
602 
      Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h1, 3'h0,
603 
                     test_observe_1_oe_sigs[5:0], prev_test_0_oe_sigs[5:0]);
604 
      Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h1, `Test_Master_Real,
605 
                     test_observe_1_oe_sigs[5:0], prev_real_oe_sigs[5:0]);
606 
      Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h1, 3'h2,
607 
                     test_observe_1_oe_sigs[5:0], prev_test_2_oe_sigs[5:0]);
608 
      Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h1, 3'h3,
609 
                     test_observe_1_oe_sigs[5:0], prev_test_3_oe_sigs[5:0]);
610 
 
611 
      Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h2, 3'h0,
612 
                     test_observe_2_oe_sigs[5:0], prev_test_0_oe_sigs[5:0]);
613 
      Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h2, 3'h1,
614 
                     test_observe_2_oe_sigs[5:0], prev_test_1_oe_sigs[5:0]);
615 
      Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h2, `Test_Master_Real,
616 
                     test_observe_2_oe_sigs[5:0], prev_real_oe_sigs[5:0]);
617 
      Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h2, 3'h3,
618 
                     test_observe_2_oe_sigs[5:0], prev_test_3_oe_sigs[5:0]);
619 
 
620 
      Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h3, 3'h0,
621 
                     test_observe_3_oe_sigs[5:0], prev_test_0_oe_sigs[5:0]);
622 
      Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h3, 3'h1,
623 
                     test_observe_3_oe_sigs[5:0], prev_test_1_oe_sigs[5:0]);
624 
      Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h3, 3'h2,
625 
                     test_observe_3_oe_sigs[5:0], prev_test_2_oe_sigs[5:0]);
626 
      Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h3, `Test_Master_Real,
627 
                     test_observe_3_oe_sigs[5:0], prev_real_oe_sigs[5:0]);
628 
 
629 
      Watch_For_Deassert_Before_Tristate(`Test_Master_Real, prev_real_oe_sigs, test_observe_r_oe_sigs, perr_prev, frame_prev, irdy_prev, trdy_prev, stop_prev, devsel_prev) ;
630 
      Watch_For_Deassert_Before_Tristate(3'h0, prev_test_0_oe_sigs, test_observe_0_oe_sigs, perr_prev, frame_prev, irdy_prev, trdy_prev, stop_prev, devsel_prev) ;
631 
      Watch_For_Deassert_Before_Tristate(3'h1, prev_test_1_oe_sigs, test_observe_1_oe_sigs, perr_prev, frame_prev, irdy_prev, trdy_prev, stop_prev, devsel_prev) ;
632 
      Watch_For_Deassert_Before_Tristate(3'h2, prev_test_2_oe_sigs, test_observe_2_oe_sigs, perr_prev, frame_prev, irdy_prev, trdy_prev, stop_prev, devsel_prev) ;
633 
      Watch_For_Deassert_Before_Tristate(3'h3, prev_test_3_oe_sigs, test_observe_3_oe_sigs, perr_prev, frame_prev, irdy_prev, trdy_prev, stop_prev, devsel_prev) ;
634 
 
635 
    end
636 
    `NO_ELSE;
637 
  end
638 
 
639 
  always @(posedge pci_ext_clk or negedge pci_ext_reset_l)
640 
  begin
641 
    if (pci_ext_reset_l == 1'b0)
642 
    begin
643 
      grant_prev <= 5'h00;
644 
      ad_prev[PCI_BUS_DATA_RANGE:0] <= `PCI_BUS_DATA_X;
645 
      cbe_l_prev[PCI_BUS_CBE_RANGE:0] <= `PCI_BUS_CBE_X;
646 
      frame_prev <= 1'b0;
647 
      irdy_prev <= 1'b0;
648 
      devsel_prev <= 1'b0;
649 
      trdy_prev <= 1'b0;
650 
      stop_prev <= 1'b0;
651 
      address_phase_prev <= 1'b0;
652 
      read_operation_prev <= 1'b0;
653 
    end
654 
    else
655 
    begin
656 
      grant_prev <= {pci_ext_gnt_l[3:0], pci_real_gnt_l};
657 
      ad_prev[PCI_BUS_DATA_RANGE:0] <= pci_ext_ad[PCI_BUS_DATA_RANGE:0];
658 
      cbe_l_prev[PCI_BUS_CBE_RANGE:0] <= pci_ext_cbe_l[PCI_BUS_CBE_RANGE:0];
659 
      frame_prev <= frame_now;
660 
      irdy_prev <= irdy_now;
661 
      devsel_prev <= devsel_now;
662 
      trdy_prev <= trdy_now;
663 
      stop_prev <= stop_now;
664 
      perr_prev <= perr_now ;
665 
 
666 
      if (frame_now & ~frame_prev
667 
                && (pci_ext_cbe_l[PCI_BUS_CBE_RANGE:0] != PCI_COMMAND_DUAL_ADDRESS_CYCLE))
668 
      begin
669 
        address_phase_prev <= 1'b1;
670 
        read_operation_prev <= ~pci_ext_cbe_l[0];  // reads have LSB == 0;
671 
      end
672 
      else
673 
      begin
674 
        address_phase_prev <= 1'b0;
675 
        read_operation_prev <= read_operation_prev;
676 
      end
677 
    end
678 
  end
679 
 
680 
// Track the behavior of the PCI Arbiter.  Rules:
681 
// 1) No grant during reset
682 
// 2) At most 1 grant at any time
683 
// 3) One non-grant cycle on any grant transition when the bus is idle
684 
// See the PCI Local Bus Spec Revision 2.2 Appendix C.
685 
  always @(posedge pci_ext_clk)
686 
  begin
687 
    if ($time > 0)
688 
    begin
689 
      if ((^{pci_ext_gnt_l[3:0], pci_real_gnt_l}) === 1'bX)
690 
      begin
691 
        $display ("*** monitor - PCI GNT_L unknown 'h%x, at %t",
692 
                    {pci_ext_gnt_l[3:0], pci_real_gnt_l}, $time);
693 
        $fdisplay (log_file_desc, "*** monitor - PCI GNT_L unknown 'h%x, at %t",
694 
                    {pci_ext_gnt_l[3:0], pci_real_gnt_l}, $time);
695 
        error_detected <= ~error_detected;
696 
      end
697 
      `NO_ELSE;
698 
      if ((pci_ext_reset_l == 1'b0)
699 
           && ({pci_ext_gnt_l[3:0], pci_real_gnt_l} != 5'h1F))
700 
      begin
701 
        $display ("*** monitor - PCI GNT_L not deasserted during Reset 'h%x, at %t",
702 
                    {pci_ext_gnt_l[3:0], pci_real_gnt_l}, $time);
703 
        $fdisplay (log_file_desc, "*** monitor - PCI GNT_L not deasserted during Reset 'h%x, at %t",
704 
                    {pci_ext_gnt_l[3:0], pci_real_gnt_l}, $time);
705 
        error_detected <= ~error_detected;
706 
      end
707 
      `NO_ELSE;
708 
      if (   (~pci_ext_gnt_l[3] & ~pci_ext_gnt_l[2])
709 
          || (~pci_ext_gnt_l[3] & ~pci_ext_gnt_l[1])
710 
          || (~pci_ext_gnt_l[3] & ~pci_ext_gnt_l[0])
711 
          || (~pci_ext_gnt_l[3] & ~pci_real_gnt_l)
712 
          || (~pci_ext_gnt_l[2] & ~pci_ext_gnt_l[1])
713 
          || (~pci_ext_gnt_l[2] & ~pci_ext_gnt_l[0])
714 
          || (~pci_ext_gnt_l[2] & ~pci_real_gnt_l)
715 
          || (~pci_ext_gnt_l[1] & ~pci_ext_gnt_l[0])
716 
          || (~pci_ext_gnt_l[1] & ~pci_real_gnt_l)
717 
          || (~pci_ext_gnt_l[0] & ~pci_real_gnt_l) )
718 
      begin
719 
        $display ("*** monitor - More than 1 PCI GNT_L asserted 'h%x, at %t",
720 
                    {pci_ext_gnt_l[3:0], pci_real_gnt_l}, $time);
721 
        $fdisplay (log_file_desc, "*** monitor - More than 1 PCI GNT_L asserted 'h%x, at %t",
722 
                    {pci_ext_gnt_l[3:0], pci_real_gnt_l}, $time);
723 
        error_detected <= ~error_detected;
724 
      end
725 
      `NO_ELSE;
726 
      if  (  (pci_ext_reset_l == 1'b1)
727 
          && (~frame_prev & ~irdy_prev)  // bus idle
728 
          && (grant_prev != 5'h1F) && ({pci_ext_gnt_l[3:0], pci_real_gnt_l} != 5'h1F)
729 
          && ({pci_ext_gnt_l[3:0], pci_real_gnt_l} != grant_prev))
730 
      begin
731 
        $display ("*** monitor - Changed from one Grant to another when bus idle 'h%x to 'h%x, at %t",
732 
                    grant_prev, {pci_ext_gnt_l[3:0], pci_real_gnt_l}, $time);
733 
        $fdisplay (log_file_desc, "*** monitor - Changed from one Grant to another when bus idle 'h%x to 'h%x, at %t",
734 
                    grant_prev, {pci_ext_gnt_l[3:0], pci_real_gnt_l}, $time);
735 
        error_detected <= ~error_detected;
736 
      end
737 
      `NO_ELSE;
738 
    end
739 
    `NO_ELSE;
740 
  end
741 
 
742 
// Classify bus activity and notice slow or dead devices.
743 
// See the PCI Local Bus Spec Revision 2.2 section 3.5
744 
  reg     master_activity_seen, target_activity_seen, target_subsequently_seen;
745 
  reg    [2:0] master_initial_latency_counter;
746 
  reg    [3:0] target_initial_latency_counter;
747 
  reg    [2:0] target_subsequent_latency_counter;
748 
  reg    [3:0] master_abort_timer;
749 
  reg     master_abort;
750 
 
751 
  always @(posedge pci_ext_clk or negedge pci_ext_reset_l)
752 
  begin
753 
    if (pci_ext_reset_l == 1'b0)
754 
    begin
755 
      master_activity_seen <= 1'b0;
756 
      master_initial_latency_counter <= 3'h0;
757 
      target_activity_seen <= 1'b0;
758 
      target_initial_latency_counter <= 4'h0;
759 
      target_subsequently_seen <= 1'b0;
760 
      target_subsequent_latency_counter <= 3'h0;
761 
      master_abort_timer <= 4'h0;
762 
      master_abort <= 1'b0;
763 
    end
764 
    else
765 
    begin
766 
      if ((address_phase_prev) | (~frame_prev & ~irdy_prev))  // address or idle
767 
      begin
768 
        master_abort_timer <= 4'h0;
769 
        master_abort <= 1'b0;
770 
        master_activity_seen <= 1'b0;
771 
        master_initial_latency_counter <= 3'h0;
772 
        target_activity_seen <= 1'b0;
773 
        target_initial_latency_counter <= 4'h0;
774 
        target_subsequently_seen <= 1'b0;
775 
        target_subsequent_latency_counter <= 3'h0;
776 
      end
777 
      else
778 
      begin
779 
// NOTE WORKING not debugged yet.
780 
        master_initial_latency_counter <= master_initial_latency_counter + 3'h1;
781 
        master_activity_seen <= master_activity_seen | irdy_now;
782 
        if ((master_initial_latency_counter == 3'h7) & ~master_activity_seen)
783 
        begin
784 
          $display ("*** monitor - Master didn't assert IRDY within 8 clocks of FRAME, at %t",
785 
                    $time);
786 
          $fdisplay (log_file_desc, "*** monitor - Master didn't assert IRDY within 8 clocks of FRAME, at %t",
787 
                    $time);
788 
          error_detected <= ~error_detected;
789 
          master_activity_seen <= 1'b1;
790 
        end
791 
        `NO_ELSE;
792 
 
793 
        target_initial_latency_counter <= target_initial_latency_counter
794 
                              + (devsel_now ? 4'h1 : 4'h0);
795 
        target_activity_seen <= target_activity_seen | trdy_now;
796 
        if ((target_initial_latency_counter == 4'hF) & ~target_activity_seen)
797 
        begin
798 
          $display ("*** monitor - Target didn't assert TRDY within 16 clocks of DEVSEL, at %t",
799 
                    $time);
800 
          $fdisplay (log_file_desc, "*** monitor - Target didn't assert TRDY within 16 clocks of DEVSEL, at %t",
801 
                    $time);
802 
          error_detected <= ~error_detected;
803 
          target_activity_seen <= 1'b1;
804 
        end
805 
        `NO_ELSE;
806 
 
807 
// NOTE This only detects Target misbehavior on the FIRST subsequent transfer!!!
808 
        target_subsequent_latency_counter <= target_subsequent_latency_counter
809 
                              + (target_activity_seen ? 3'h1 : 3'h0);
810 
        target_subsequently_seen <= target_subsequently_seen
811 
                                  | (target_activity_seen & trdy_now);
812 
        if ((target_subsequent_latency_counter == 3'h7) & ~target_subsequently_seen)
813 
        begin
814 
          $display ("*** monitor - Target didn't assert TRDY within 8 clocks of first TRDY, at %t",
815 
                    $time);
816 
          $fdisplay (log_file_desc, "*** monitor - Target didn't assert TRDY within 8 clocks of first TRDY, at %t",
817 
                    $time);
818 
          error_detected <= ~error_detected;
819 
          target_subsequently_seen <= 1'b1;
820 
        end
821 
        `NO_ELSE;
822 
 
823 
        master_abort_timer <= master_abort_timer + 4'h1;
824 
        master_abort <= (master_abort_timer >= 4'h2) ? 1'b1 : master_abort;
825 
      end
826 
    end
827 
  end
828 
 
829 
// Track the parity bit status on the bus.  The rules are:
830 
// 1) parity has to be correct whenever FRAME is asserted to be a valid address
831 
// 2) parity has to be correct whenever IRDY is asserted on writes
832 
// 3) parity has to be correct whenever TRDY is asserted on reads
833 
// parity covers the ad bus, and the cbe wires.  The PCI bus is even parity.
834 
// The number of bits set to 1 in AD plus CBE plus PAR is an EVEN number.
835 
// This code will notice an error, but will only complain if the PERR and SERR
836 
// bits don't match,
837 
  reg     prev_calculated_ad_cbe_parity;
838 
  reg     prev_prev_calculated_ad_cbe_parity, read_operation_prev_prev;
839 
  reg     prev_prev_devsel, prev_prev_trdy, prev_prev_irdy, prev_pci_ext_par;
840 
  reg     ad_prev_address_phase;
841 
  reg    [PCI_BUS_DATA_RANGE:0] ad_prev_prev;
842 
  reg    [PCI_BUS_CBE_RANGE:0] cbe_l_prev_prev;
843 
  always @(posedge pci_ext_clk)
844 
  begin
845 
// calculate 1 if an odd number of bits is set, 0 if an even number is set
846 
    prev_calculated_ad_cbe_parity <= (^pci_ext_ad[PCI_BUS_DATA_RANGE:0])
847 
                                   ^ (^pci_ext_cbe_l[PCI_BUS_CBE_RANGE:0]);
848 
    prev_prev_calculated_ad_cbe_parity <= prev_calculated_ad_cbe_parity;
849 
    read_operation_prev_prev <= read_operation_prev;
850 
    ad_prev_address_phase <= address_phase_prev;
851 
    prev_prev_devsel <= devsel_prev;
852 
    prev_prev_trdy <= trdy_prev;
853 
    prev_prev_irdy <= irdy_prev;
854 
    prev_pci_ext_par <= pci_ext_par;
855 
    ad_prev_prev[PCI_BUS_DATA_RANGE:0] <= ad_prev[PCI_BUS_DATA_RANGE:0];
856 
    cbe_l_prev_prev[PCI_BUS_CBE_RANGE:0] <= cbe_l_prev[PCI_BUS_CBE_RANGE:0];
857 
    if (($time > 0) && (pci_ext_reset_l !== 1'b0))
858 
    begin
859 
      if (ad_prev_address_phase)
860 
      begin
861 
        if (((prev_prev_calculated_ad_cbe_parity ^ prev_prev_calculated_ad_cbe_parity) === 1'bX)
862 
             | ((prev_pci_ext_par ^ prev_pci_ext_par) === 1'bX)
863 
             | ((prev_prev_calculated_ad_cbe_parity !== prev_pci_ext_par) & pci_ext_serr_l))
864 
        begin
865 
          $display ("*** monitor - Undetected Address Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
866 
                      ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
867 
          $fdisplay (log_file_desc, "*** monitor - Undetected Address Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
868 
                      ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
869 
          error_detected <= ~error_detected;
870 
        end
871 
        `NO_ELSE;
872 
        if (((prev_prev_calculated_ad_cbe_parity ^ prev_prev_calculated_ad_cbe_parity) === 1'bX)
873 
             | ((prev_pci_ext_par ^ prev_pci_ext_par) === 1'bX)
874 
             | ((prev_prev_calculated_ad_cbe_parity === prev_pci_ext_par) & ~pci_ext_serr_l))
875 
        begin
876 
          $display ("*** monitor - Invalid Address Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
877 
                      ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
878 
          $fdisplay (log_file_desc, "*** monitor - Invalid Address Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
879 
                      ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
880 
          error_detected <= ~error_detected;
881 
        end
882 
        `NO_ELSE;
883 
      end
884 
      `NO_ELSE;
885 
      if (read_operation_prev_prev & prev_prev_trdy)
886 
      begin
887 
        if (((prev_prev_calculated_ad_cbe_parity ^ prev_prev_calculated_ad_cbe_parity) === 1'bX)
888 
             | ((prev_pci_ext_par ^ prev_pci_ext_par) === 1'bX)
889 
             | ((prev_prev_calculated_ad_cbe_parity !== prev_pci_ext_par) & pci_ext_perr_l))
890 
        begin
891 
          $display ("*** monitor - Undetected Read Data Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
892 
                      ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
893 
          $fdisplay (log_file_desc, "*** monitor - Undetected Read Data Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
894 
                      ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
895 
          error_detected <= ~error_detected;
896 
        end
897 
        `NO_ELSE;
898 
        if (((prev_prev_calculated_ad_cbe_parity ^ prev_prev_calculated_ad_cbe_parity) === 1'bX)
899 
             | ((prev_pci_ext_par ^ prev_pci_ext_par) === 1'bX)
900 
             | ((prev_prev_calculated_ad_cbe_parity === prev_pci_ext_par) & ~pci_ext_perr_l))
901 
        begin
902 
          $display ("*** monitor - Invalid Read Data Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
903 
                      ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
904 
          $fdisplay (log_file_desc, "*** monitor - Invalid Read Data Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
905 
                      ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
906 
          error_detected <= ~error_detected;
907 
        end
908 
        `NO_ELSE;
909 
      end
910 
      `NO_ELSE;
911 
      if (~read_operation_prev_prev & prev_prev_irdy & prev_prev_devsel)
912 
      begin
913 
        if (((prev_prev_calculated_ad_cbe_parity ^ prev_prev_calculated_ad_cbe_parity) === 1'bX)
914 
             | ((prev_pci_ext_par ^ prev_pci_ext_par) === 1'bX)
915 
             | ((prev_prev_calculated_ad_cbe_parity !== prev_pci_ext_par) & pci_ext_perr_l))
916 
        begin
917 
          $display ("*** monitor - Undetected Write Data Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
918 
                      ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
919 
          $fdisplay (log_file_desc, "*** monitor - Undetected Write Data Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
920 
                      ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
921 
          error_detected <= ~error_detected;
922 
        end
923 
        `NO_ELSE;
924 
        if (((prev_prev_calculated_ad_cbe_parity ^ prev_prev_calculated_ad_cbe_parity) === 1'bX)
925 
             | ((prev_pci_ext_par ^ prev_pci_ext_par) === 1'bX)
926 
             | ((prev_prev_calculated_ad_cbe_parity === prev_pci_ext_par) & ~pci_ext_perr_l))
927 
        begin
928 
          $display ("*** monitor - Invalid Write Data Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
929 
                      ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
930 
          $fdisplay (log_file_desc, "*** monitor - Invalid Write Data Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
931 
                      ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
932 
          error_detected <= ~error_detected;
933 
        end
934 
        `NO_ELSE;
935 
      end
936 
      `NO_ELSE;
937 
    end
938 
  end
939 
 
940 
// Verify some of the state transitions observed on the bus.
941 
// See the PCI Local Bus Spec Revision 2.2 Appendix C.
942 
// In general, transition tests should look at one present signal, and
943 
//   a bunch of previous signals.
944 
// In general, simultaneous transition tests should look at two present
945 
//   signals, and a bunch of previous signals.
946 
  always @(posedge pci_ext_clk)
947 
  begin
948 
    if (($time > 0) && (pci_ext_reset_l !== 1'b0))
949 
    begin
950 
      if (irdy_prev & ~read_operation_prev & ~(trdy_prev | stop_prev) & (pci_ext_ad != ad_prev))
951 
      begin  // Appendix C line 2C
952 
        $display ("*** monitor - AD Bus Changed when Writing with IRDY Asserted and TRDY Deasserted, at %t",
953 
                    $time);
954 
        $fdisplay (log_file_desc, "*** monitor - AD Bus Changed when Writing with IRDY Asserted and TRDY Deasserted, at %t",
955 
                    $time);
956 
        error_detected <= ~error_detected;
957 
      end
958 
      `NO_ELSE;
959 
      if (trdy_prev & read_operation_prev & ~irdy_prev & (pci_ext_ad != ad_prev))
960 
      begin  // Appendix C line 2C
961 
        $display ("*** monitor - AD Bus Changed when Reading with TRDY Asserted and IRDY Deasserted, at %t",
962 
                    $time);
963 
        $fdisplay (log_file_desc, "*** monitor - AD Bus Changed when Reading with TRDY Asserted and IRDY Deasserted, at %t",
964 
                    $time);
965 
        error_detected <= ~error_detected;
966 
      end
967 
      `NO_ELSE;
968 
      if (frame_prev & (frame_now | irdy_now) & ~address_phase_prev & ~trdy_now
969 
                                                 & (pci_ext_cbe_l != cbe_l_prev))
970 
      begin  // Appendix C line 3B
971 
        $display ("*** monitor - CBE Bus Changed when TRDY Desserted, at %t",
972 
                    $time);
973 
        $fdisplay (log_file_desc, "*** monitor - CBE Bus Changed when TRDY Desserted, at %t",
974 
                    $time);
975 
        error_detected <= ~error_detected;
976 
      end
977 
      `NO_ELSE;
978 
      if (~frame_prev & frame_now & irdy_now)
979 
      begin  // Section 3.3.3.1 rule 2, Appendix C line 7B
980 
        $display ("*** monitor - FRAME Asserted while IRDY still Asserted, at %t",
981 
                    $time);
982 
        $fdisplay (log_file_desc, "*** monitor - FRAME Asserted while IRDY still Asserted, at %t",
983 
                    $time);
984 
        error_detected <= ~error_detected;
985 
      end
986 
      `NO_ELSE;
987 
      if (~irdy_prev & irdy_now & ~frame_prev)
988 
      begin  // Appendix C line ?  not in there!
989 
        $display ("*** monitor - IRDY Asserted when FRAME Deasserted, at %t",
990 
                    $time);
991 
        $fdisplay (log_file_desc, "*** monitor - IRDY Asserted when FRAME Deasserted, at %t",
992 
                    $time);
993 
        error_detected <= ~error_detected;
994 
      end
995 
      `NO_ELSE;
996 
      if (frame_prev & ~frame_now & ~irdy_now)
997 
      begin  // Section 3.3.3.1 rule 3, Appendix C line 7C
998 
        $display ("*** monitor - FRAME Desserted without IRDY being Asserted, at %t",
999 
                    $time);
1000 
        $fdisplay (log_file_desc, "*** monitor - FRAME Desserted without IRDY being Asserted, at %t",
1001 
                    $time);
1002 
        error_detected <= ~error_detected;
1003 
      end
1004 
      `NO_ELSE;
1005 
      if (irdy_prev & ~(trdy_prev | stop_prev | master_abort)
1006 
                                             & (frame_now != frame_prev))
1007 
      begin  // Section 3.3.3.1 rule 4, Appendix C line 7D
1008 
        $display ("*** monitor - FRAME changed while IRDY Asserted when not end of reference, at %t",
1009 
                    $time);
1010 
        $fdisplay (log_file_desc, "*** monitor - FRAME changed while IRDY Asserted when not end of reference, at %t",
1011 
                    $time);
1012 
        error_detected <= ~error_detected;
1013 
      end
1014 
      `NO_ELSE;
1015 
      if (irdy_prev & ~(trdy_prev | stop_prev | master_abort) & ~irdy_now)
1016 
      begin  // Section 3.3.3.1 rule 5, Appendix C line 7E
1017 
        $display ("*** monitor - IRDY Deasserted after being Asserted when not end of reference, at %t",
1018 
                    $time);
1019 
        $fdisplay (log_file_desc, "*** monitor - IRDY Deasserted after being Asserted when not end of reference, at %t",
1020 
                    $time);
1021 
        error_detected <= ~error_detected;
1022 
      end
1023 
      `NO_ELSE;
1024 
// NOTE WORKING section 3.3.3.2.2, Appendix C line 10, REQ must be removed for
1025 
// NOTE WORKING IDLE and one clock on either side of IDLE upon retry or disconnect
1026 
      if (stop_prev & frame_prev & frame_now & ~stop_now)
1027 
      begin  // Section 3.3.3.2.1 rule 3, Appendix C line 12C
1028 
        $display ("*** monitor - STOP Deasserted while FRAME Asserted, at %t",
1029 
                    $time);
1030 
        $fdisplay (log_file_desc, "*** monitor - STOP Deasserted while FRAME Asserted, at %t",
1031 
                    $time);
1032 
        error_detected <= ~error_detected;
1033 
      end
1034 
      `NO_ELSE;
1035 
      if (stop_prev & ~frame_prev & frame_now & stop_now)
1036 
      begin  // Section 3.3.3.2.1 rule 3, Appendix C line 12C, author addition
1037 
        $display ("*** monitor - STOP didn't Deassert while FRAME Deasserted in fast back-to-back, at %t",
1038 
                    $time);
1039 
        $fdisplay (log_file_desc, "*** monitor - STOP didn't Deassert while FRAME Deasserted in fast back-to-back, at %t",
1040 
                    $time);
1041 
        error_detected <= ~error_detected;
1042 
      end
1043 
      `NO_ELSE;
1044 
      if ((trdy_prev | stop_prev) & ~irdy_prev & (devsel_prev != devsel_now))
1045 
      begin  // Section 3.3.3.2.1 rule 4, Appendix C line 12D
1046 
        $display ("*** monitor - DEVSEL changed while TRDY or STOP Asserted when not end of data phase, at %t",
1047 
                    $time);
1048 
        $fdisplay (log_file_desc, "*** monitor - DEVSEL changed while TRDY or STOP Asserted when not end of data phase, at %t",
1049 
                    $time);
1050 
        error_detected <= ~error_detected;
1051 
      end
1052 
      `NO_ELSE;
1053 
      if ((trdy_prev | stop_prev) & ~irdy_prev & (trdy_prev != trdy_now))
1054 
      begin  // Section 3.3.3.2.1 rule 4, Appendix C line 12D
1055 
        $display ("*** monitor - TRDY changed while TRDY or STOP Asserted when not end of data phase, at %t",
1056 
                    $time);
1057 
        $fdisplay (log_file_desc, "*** monitor - TRDY changed while TRDY or STOP Asserted when not end of data phase, at %t",
1058 
                    $time);
1059 
        error_detected <= ~error_detected;
1060 
      end
1061 
      `NO_ELSE;
1062 
      if ((trdy_prev | stop_prev) & ~irdy_prev & (stop_prev != stop_now))
1063 
      begin  // Section 3.3.3.2.1 rule 4, Appendix C line 12D
1064 
        $display ("*** monitor - STOP changed while TRDY or STOP Asserted when not end of data phase, at %t",
1065 
                    $time);
1066 
        $fdisplay (log_file_desc, "*** monitor - STOP changed while TRDY or STOP Asserted when not end of data phase, at %t",
1067 
                    $time);
1068 
        error_detected <= ~error_detected;
1069 
      end
1070 
      `NO_ELSE;
1071 
      if (~trdy_prev & trdy_now & ~devsel_now)
1072 
      begin  // Appendix C line 14
1073 
        $display ("*** monitor - TRDY Asserted when DEVSEL Deasserted, at %t",
1074 
                    $time);
1075 
        $fdisplay (log_file_desc, "*** monitor - TRDY Asserted when DEVSEL Deasserted, at %t",
1076 
                    $time);
1077 
        error_detected <= ~error_detected;
1078 
      end
1079 
      `NO_ELSE;
1080 
      if (~stop_prev & stop_now & ~(devsel_prev | devsel_now))
1081 
      begin  // Appendix C line 14
1082 
        $display ("*** monitor - STOP Asserted when DEVSEL Deasserted, at %t",
1083 
                    $time);
1084 
        $fdisplay (log_file_desc, "*** monitor - STOP Asserted when DEVSEL Deasserted, at %t",
1085 
                    $time);
1086 
        error_detected <= ~error_detected;
1087 
      end
1088 
      `NO_ELSE;
1089 
      if (~frame_prev & frame_now & (grant_prev == 5'h1F))
1090 
      begin  // Appendix C line 21
1091 
        $display ("*** monitor - FRAME Asserted when no GNT Asserted, at %t",
1092 
                    $time);
1093 
        $fdisplay (log_file_desc, "*** monitor - FRAME Asserted when no GNT Asserted, at %t",
1094 
                    $time);
1095 
        error_detected <= ~error_detected;
1096 
      end
1097 
      `NO_ELSE;
1098 
      if (devsel_prev & ~devsel_now & frame_prev & ~(stop_now & ~trdy_now))
1099 
      begin  // Appendix C line 30
1100 
        $display ("*** monitor - DEVSEL Deasserted when FRAME Asserted, and no Target Abort, at %t",
1101 
                    $time);
1102 
        $fdisplay (log_file_desc, "*** monitor - DEVSEL Deasserted when FRAME Asserted, and no Target Abort, at %t",
1103 
                    $time);
1104 
        error_detected <= ~error_detected;
1105 
      end
1106 
      `NO_ELSE;
1107 
    end
1108 
    `NO_ELSE;
1109 
  end
1110 
 
1111 
// Verify some of the state transitions observed on the bus. See the
1112 
// PCI Local Bus Spec Revision 2.2 section 3.2.1, plus Appendix C.
1113 
`ifdef VERBOSE_MONITOR_DEVICE
1114 
  reg     prev_pci_ext_reset_l;
1115 
  always @(pci_ext_reset_l)
1116 
  begin
1117 
    prev_pci_ext_reset_l <= pci_ext_reset_l;
1118 
 
1119 
    if (($time > 0) && (pci_ext_reset_l !== prev_pci_ext_reset_l))
1120 
    begin
1121 
      if (pci_ext_reset_l == 1'b0)
1122 
      begin
1123 
        $display (" monitor - PCI External RESET_L asserted LOW at %t", $time);
1124 
      end
1125 
      `NO_ELSE;
1126 
 
1127 
      if (pci_ext_reset_l == 1'b1)
1128 
      begin
1129 
        $display (" monitor - PCI External RESET_L deasserted HIGH at %t", $time);
1130 
      end
1131 
      `NO_ELSE;
1132 
    end
1133 
  end
1134 
 
1135 
  always @(posedge pci_ext_clk)
1136 
  begin
1137 
    if (($time > 0) && (pci_ext_reset_l !== 1'b0))
1138 
    begin
1139 
// report a Master Abort, which is not an error
1140 
      if ((irdy_prev & ~irdy_now) & (~trdy_prev & ~stop_prev & master_abort))
1141 
      begin
1142 
        $display (" monitor - IRDY Deasserted due to Master Abort, at %t", $time);
1143 
      end
1144 
      `NO_ELSE;
1145 
 
1146 
      if (~frame_prev & frame_now & irdy_prev & ~irdy_now)
1147 
      begin
1148 
        $display (" Fast Back-to-Back reference with no Idle cycle started at %t",
1149 
                  $time);
1150 
      end
1151 
      `NO_ELSE;
1152 
    end
1153 
    `NO_ELSE;
1154 
  end
1155 
`endif // VERBOSE_MONITOR_DEVICE
1156 
 
1157 
`ifdef VERBOSE_MONITOR_DEVICE
1158 
  always @(posedge pci_ext_clk)
1159 
  begin
1160 
    if (($time > 0) && (pci_ext_reset_l !== 1'b0) && address_phase_prev)
1161 
    begin
1162 
// command list taken from PCI Local Bus Spec Revision 2.2 section 3.1.1.
1163 
      case (cbe_l_prev[PCI_BUS_CBE_RANGE:0])
1164 
      PCI_COMMAND_INTERRUPT_ACKNOWLEDGE:
1165 
        $display (" monitor - Interrupt Acknowledge started, AD: 'h%x, CBE: 'h%x, at time %t",
1166 
                    ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);,
1167 
      PCI_COMMAND_SPECIAL_CYCLE:
1168 
        $display (" monitor - Special Cycle started, AD: 'h%x, CBE: 'h%x, at time %t",
1169 
                    ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
1170 
      PCI_COMMAND_IO_READ:
1171 
        $display (" monitor - IO Read started, AD: 'h%x, CBE: 'h%x, at time %t",
1172 
                    ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
1173 
      PCI_COMMAND_IO_WRITE:
1174 
        $display (" monitor - IO Write started, AD: 'h%x, CBE: 'h%x, at time %t",
1175 
                    ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
1176 
      PCI_COMMAND_RESERVED_READ_4:
1177 
        $display (" monitor - Reserved started, AD: 'h%x, CBE: 'h%x, at time %t",
1178 
                    ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
1179 
      PCI_COMMAND_RESERVED_WRITE_5:
1180 
        $display (" monitor - Reserved started, AD: 'h%x, CBE: 'h%x, at time %t",
1181 
                    ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
1182 
      PCI_COMMAND_MEMORY_READ:
1183 
        $display (" monitor - Memory Read started, AD: 'h%x, CBE: 'h%x, at time %t",
1184 
                    ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
1185 
      PCI_COMMAND_MEMORY_WRITE:
1186 
        $display (" monitor - Memory Write started, AD: 'h%x, CBE: 'h%x, at time %t",
1187 
                    ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
1188 
      PCI_COMMAND_RESERVED_READ_8:
1189 
        $display (" monitor - Reserved started, AD: 'h%x, CBE: 'h%x, at time %t",
1190 
                    ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
1191 
      PCI_COMMAND_RESERVED_WRITE_9:
1192 
        $display (" monitor - Reserved started, AD: 'h%x, CBE: 'h%x, at time %t",
1193 
                    ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
1194 
      PCI_COMMAND_CONFIG_READ:
1195 
        $display (" monitor - Configuration Read started, AD: 'h%x, CBE: 'h%x, at time %t",
1196 
                    ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
1197 
      PCI_COMMAND_CONFIG_WRITE:
1198 
        $display (" monitor - Configuration Write started, AD: 'h%x, CBE: 'h%x, at time %t",
1199 
                    ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
1200 
      PCI_COMMAND_MEMORY_READ_MULTIPLE:
1201 
        $display (" monitor - Memory Read Multiple started, AD: 'h%x, CBE: 'h%x, at time %t",
1202 
                    ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
1203 
      PCI_COMMAND_DUAL_ADDRESS_CYCLE:
1204 
        $display (" monitor - Dual Address Cycle started, AD: 'h%x, CBE: 'h%x, at time %t",
1205 
                    ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
1206 
      PCI_COMMAND_MEMORY_READ_LINE:
1207 
        $display (" monitor - Memory Read Line started, AD: 'h%x, CBE: 'h%x, at time %t",
1208 
                    ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
1209 
      PCI_COMMAND_MEMORY_WRITE_INVALIDATE:
1210 
        $display (" monitor - Memory Write and Invalidate started, AD: 'h%x, CBE: 'h%x, at time %t",
1211 
                    ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
1212 
      default:
1213 
        begin
1214 
          $display ("*** monitor - Unknown operation started, AD: 'h%x, CBE: 'h%x, at time %t",
1215 
                      ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
1216 
          $fdisplay (log_file_desc,
1217 
          error_detected <= ~error_detected;
1218 
        end
1219 
      endcase
1220 
    end
1221 
    `NO_ELSE;
1222 
  end
1223 
`endif // VERBOSE_MONITOR_DEVICE
1224 
endmodule
1225 
 

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