1 |
15 |
mihad |
//===========================================================================
|
2 |
|
|
// $Id: pci_blue_constants.vh,v 1.1 2002-02-01 13:39:43 mihad Exp $
|
3 |
|
|
//
|
4 |
|
|
// Copyright 2001 Blue Beaver. All Rights Reserved.
|
5 |
|
|
//
|
6 |
|
|
// Summary: Constants used throughout the pci_blue_interface. Some of these
|
7 |
|
|
// constants will be used in the Host Interface, so will be known
|
8 |
|
|
// by the user of this IP. These constants are not expected to
|
9 |
|
|
// change from design to design.
|
10 |
|
|
//
|
11 |
|
|
// This library is free software; you can distribute it and/or modify it
|
12 |
|
|
// under the terms of the GNU Lesser General Public License as published
|
13 |
|
|
// by the Free Software Foundation; either version 2.1 of the License, or
|
14 |
|
|
// (at your option) any later version.
|
15 |
|
|
//
|
16 |
|
|
// This library is distributed in the hope that it will be useful, but
|
17 |
|
|
// WITHOUT ANY WARRANTY; without even the implied warranty of
|
18 |
|
|
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
|
19 |
|
|
// See the GNU Lesser General Public License for more details.
|
20 |
|
|
//
|
21 |
|
|
// You should have received a copy of the GNU Lesser General Public License
|
22 |
|
|
// along with this library. If not, write to
|
23 |
|
|
// Free Software Foundation, Inc.
|
24 |
|
|
// 59 Temple Place, Suite 330
|
25 |
|
|
// Boston, MA 02111-1307 USA
|
26 |
|
|
//
|
27 |
|
|
// Author's note about this license: The intention of the Author and of
|
28 |
|
|
// the Gnu Lesser General Public License is that users should be able to
|
29 |
|
|
// use this code for any purpose, including combining it with other source
|
30 |
|
|
// code, combining it with other logic, translated it into a gate-level
|
31 |
|
|
// representation, or projected it into gates in a programmable or
|
32 |
|
|
// hardwired chip, as long as the users of the resulting source, compiled
|
33 |
|
|
// source, or chip are given the means to get a copy of this source code
|
34 |
|
|
// with no new restrictions on redistribution of this source.
|
35 |
|
|
//
|
36 |
|
|
// If you make changes, even substantial changes, to this code, or use
|
37 |
|
|
// substantial parts of this code as an inseparable part of another work
|
38 |
|
|
// of authorship, the users of the resulting IP must be given the means
|
39 |
|
|
// to get a copy of the modified or combined source code, with no new
|
40 |
|
|
// restrictions on redistribution of the resulting source.
|
41 |
|
|
//
|
42 |
|
|
// Seperate parts of the combined source code, compiled code, or chip,
|
43 |
|
|
// which are NOT derived from this source code do NOT need to be offered
|
44 |
|
|
// to the final user of the chip merely because they are used in
|
45 |
|
|
// combination with this code. Other code is not forced to fall under
|
46 |
|
|
// the GNU Lesser General Public License when it is linked to this code.
|
47 |
|
|
// The license terms of other source code linked to this code might require
|
48 |
|
|
// that it NOT be made available to users. The GNU Lesser General Public
|
49 |
|
|
// License does not prevent this code from being used in such a situation,
|
50 |
|
|
// as long as the user of the resulting IP is given the means to get a
|
51 |
|
|
// copy of this component of the IP with no new restrictions on
|
52 |
|
|
// redistribution of this source.
|
53 |
|
|
//
|
54 |
|
|
// This code was developed using VeriLogger Pro, by Synapticad.
|
55 |
|
|
// Their support is greatly appreciated.
|
56 |
|
|
//
|
57 |
|
|
//===========================================================================
|
58 |
|
|
|
59 |
|
|
// define the PCI BUS Command Values so that they can be referred to symbolically
|
60 |
|
|
parameter PCI_COMMAND_INTERRUPT_ACKNOWLEDGE = 4'b0000;
|
61 |
|
|
parameter PCI_COMMAND_SPECIAL_CYCLE = 4'b0001;
|
62 |
|
|
parameter PCI_COMMAND_IO_READ = 4'b0010;
|
63 |
|
|
parameter PCI_COMMAND_IO_WRITE = 4'b0011;
|
64 |
|
|
parameter PCI_COMMAND_RESERVED_READ_4 = 4'b0100;
|
65 |
|
|
parameter PCI_COMMAND_RESERVED_WRITE_5 = 4'b0101;
|
66 |
|
|
parameter PCI_COMMAND_MEMORY_READ = 4'b0110;
|
67 |
|
|
parameter PCI_COMMAND_MEMORY_WRITE = 4'b0111;
|
68 |
|
|
parameter PCI_COMMAND_RESERVED_READ_8 = 4'b1000;
|
69 |
|
|
parameter PCI_COMMAND_RESERVED_WRITE_9 = 4'b1001;
|
70 |
|
|
parameter PCI_COMMAND_CONFIG_READ = 4'b1010;
|
71 |
|
|
parameter PCI_COMMAND_CONFIG_WRITE = 4'b1011;
|
72 |
|
|
parameter PCI_COMMAND_MEMORY_READ_MULTIPLE = 4'b1100;
|
73 |
|
|
parameter PCI_COMMAND_DUAL_ADDRESS_CYCLE = 4'b1101;
|
74 |
|
|
parameter PCI_COMMAND_MEMORY_READ_LINE = 4'b1110;
|
75 |
|
|
parameter PCI_COMMAND_MEMORY_WRITE_INVALIDATE = 4'b1111;
|
76 |
|
|
parameter PCI_COMMAND_ANY_WRITE_MASK = 4'b0001;
|
77 |
|
|
|
78 |
|
|
|
79 |
|
|
// Config Register Area consists of:
|
80 |
|
|
// 31 24 23 16 15 8 7 0
|
81 |
|
|
// | Device ID | Vendor ID | 0x00
|
82 |
|
|
// | Status | Command | 0x04
|
83 |
|
|
// | Class Code | Rev | 0x08
|
84 |
|
|
// | BIST | HEAD | LTCY | CSize| 0x0A
|
85 |
|
|
// | Base Address 0 | 0x10
|
86 |
|
|
// | Base Address 1 | 0x14
|
87 |
|
|
// | Unused | 0x18
|
88 |
|
|
// | Unused | 0x1C
|
89 |
|
|
// | Unused | 0x20
|
90 |
|
|
// | Unused | 0x24
|
91 |
|
|
// | Cardbus Pointer | 0x28
|
92 |
|
|
// | SubSys ID | SubVnd ID | 0x2C
|
93 |
|
|
// | Expansion ROM Pointer | 0x30
|
94 |
|
|
// | Reserved | Cap | 0x34
|
95 |
|
|
// | Reserved | 0x38
|
96 |
|
|
// | MLat | MGnt | IPin | ILine| 0x3C
|
97 |
|
|
//
|
98 |
|
|
// Command resets to 0 or maybe 0x80. It consists of:
|
99 |
|
|
// {6'h00, FB2B_En, SERR_En,
|
100 |
|
|
// Step_En, Par_Err_En, VGA_En, Mem_Write_Inv_En,
|
101 |
|
|
// Special_En, Master_En, Target_En, IO_En}
|
102 |
|
|
//
|
103 |
|
|
// Status consists of:
|
104 |
|
|
// {Detected_Perr, Signaled_Serr, Got_Master_Abort, Got_Target_Abort,
|
105 |
|
|
// Signaled_Target_Abort, Devsel_Timing[1:0], Master_Got_Perr,
|
106 |
|
|
// FB2B_Capable, 1'b0, 66MHz_Capable, New_Capabilities,
|
107 |
|
|
// 4'h0}
|
108 |
|
|
//
|
109 |
|
|
// Got_Master_Abort is not set for Special Cycles.
|
110 |
|
|
// Devsel_Timing will be 2'h01 in this design. New_Capabilities is 1'b0.
|
111 |
|
|
// All clearable bits in this register are cleared whenever the
|
112 |
|
|
// register is written with the corresponding bit being 1'b1.
|
113 |
|
|
// See the PCI Local Bus Spec Revision 2.2 section 6.2.3.
|
114 |
|
|
parameter CONFIG_CMD_FB2B_EN = 32'h00000200;
|
115 |
|
|
parameter CONFIG_CMD_SERR_EN = 32'h00000100;
|
116 |
|
|
parameter CONFIG_CMD_PAR_ERR_EN = 32'h00000040;
|
117 |
|
|
parameter CONFIG_CMD_MASTER_EN = 32'h00000004;
|
118 |
|
|
parameter CONFIG_CMD_TARGET_EN = 32'h00000002;
|
119 |
|
|
|
120 |
|
|
parameter CONFIG_STAT_DETECTED_PERR = 32'h80000000;
|
121 |
|
|
parameter CONFIG_STAT_DETECTED_SERR = 32'h40000000;
|
122 |
|
|
parameter CONFIG_STAT_GOT_MABORT = 32'h20000000;
|
123 |
|
|
parameter CONFIG_STAT_GOT_TABORT = 32'h10000000;
|
124 |
|
|
parameter CONFIG_STAT_CAUSED_TABORT = 32'h08000000;
|
125 |
|
|
parameter CONFIG_STAT_CAUSED_PERR = 32'h01000000;
|
126 |
|
|
parameter CONFIG_STAT_CLEAR_ALL = 32'hF9000000;
|
127 |
|
|
|
128 |
|
|
parameter CONFIG_REG_CMD_STAT_CONSTANTS = 32'h02A00080;
|
129 |
|
|
|
130 |
|
|
|
131 |
|
|
// The Host sends Requests over the Host Request Bus to initiate PCI activity.
|
132 |
|
|
// The Host Interface is required to send Requests in this order:
|
133 |
|
|
// Address, optionally several Data's, Data_Last. Sequences of Address-Address,
|
134 |
|
|
// Data-Address, Data_Last-Data, or Data_Last-Data_Last are all illegal.
|
135 |
|
|
// First, the Request which indicates that nothing should be put in the FIFO.
|
136 |
|
|
parameter PCI_HOST_REQUEST_SPARE = 3'h0;
|
137 |
|
|
// Second, a Request used during Delayed Reads to mark the Write Command FIFO empty.
|
138 |
|
|
// This Request must be issued with Data Bits 16 and 17 both set to 1'b0.
|
139 |
|
|
parameter PCI_HOST_REQUEST_INSERT_WRITE_FENCE = 3'h1;
|
140 |
|
|
// Third, a Request used to read and write the local PCI Controller's Config Registers.
|
141 |
|
|
// This Request shares it's tags with the WRITE_FENCE Command. Config References
|
142 |
|
|
// can be identified by noticing that Bits 16 or 17 are non-zero.
|
143 |
|
|
// Data Bits [7:0] are the Byte Address of the Config Register being accessed.
|
144 |
|
|
// Data Bits [15:8] are the single-byte Write Data used in writing the Config Register.
|
145 |
|
|
// Data Bit [16] indicates that a Config Write should be done.
|
146 |
|
|
// Data Bit [17] indicates that a Config Read should be done.
|
147 |
|
|
// Data Bits [20:18] are used to select individual function register sets in the
|
148 |
|
|
// case that a multi-function PCI interface is created.
|
149 |
|
|
// This Request must be issued with either Data Bits 16 or 17 set to 1'b1.
|
150 |
|
|
// `define PCI_HOST_REQUEST_READ_WRITE_CONFIG_REGISTER (3'h1)
|
151 |
|
|
// Fourth, the Requests which start a Read or a Write. Writes can be started
|
152 |
|
|
// before previous Writes complete, but only one Read can be issued at a time.
|
153 |
|
|
parameter PCI_HOST_REQUEST_ADDRESS_COMMAND = 3'h2;
|
154 |
|
|
parameter PCI_HOST_REQUEST_ADDRESS_COMMAND_SERR = 3'h3;
|
155 |
|
|
// Fifth, Requests saying Write Data, Read or Write Byte Masks, and End Burst.
|
156 |
|
|
parameter PCI_HOST_REQUEST_W_DATA_RW_MASK = 3'h4;
|
157 |
|
|
parameter PCI_HOST_REQUEST_W_DATA_RW_MASK_PERR = 3'h5;
|
158 |
|
|
parameter PCI_HOST_REQUEST_W_DATA_RW_MASK_LAST = 3'h6;
|
159 |
|
|
parameter PCI_HOST_REQUEST_W_DATA_RW_MASK_LAST_PERR = 3'h7;
|
160 |
|
|
// These Address and Data Requests always are acknowledged by either a Master Abort,
|
161 |
|
|
// a Target Abort, or a Status Data Last. Each data item which is delivered over
|
162 |
|
|
// the PCI Bus gets acknowledged by the PCI interface, and each data item not used
|
163 |
|
|
// gets flushed silently after the Master Abort or Target Abort is announced.
|
164 |
|
|
|
165 |
|
|
|
166 |
|
|
// Responses the PCI Controller sends over the Host Response Bus to indicate that
|
167 |
|
|
// progress has been made on transfers initiated over the Request Bus by the Host.
|
168 |
|
|
// First, the Response which indicates that nothing should be put in the FIFO.
|
169 |
|
|
parameter PCI_HOST_RESPONSE_SPARE = 4'h0;
|
170 |
|
|
// Second, a Response saying when the Write Fence has been disposed of. After this
|
171 |
|
|
// is received, and the Delayed Read done, it is OK to queue more Write Requests.
|
172 |
|
|
// This command will be returned in response to a Request issued with Data
|
173 |
|
|
// Bits 16 and 17 both set to 1'b0.
|
174 |
|
|
parameter PCI_HOST_RESPONSE_UNLOADING_WRITE_FENCE = 4'h1;
|
175 |
|
|
// Third, a Response repeating the Host Request the PCI Bus is presently servicing.
|
176 |
|
|
parameter PCI_HOST_RESPONSE_EXECUTED_ADDRESS_COMMAND = 4'h2;
|
177 |
|
|
// Fourth, a Response which gives commentary about what is happening on the PCI bus.
|
178 |
|
|
// These bits follow the layout of the PCI Config Register Status Half-word.
|
179 |
|
|
// When this Response is received, bits in the data field indicate the following:
|
180 |
|
|
// Bit 31: PERR Detected (sent if a Parity Error occurred on the Last Data Phase)
|
181 |
|
|
// Bit 30: SERR Detected
|
182 |
|
|
// Bit 29: Master Abort received
|
183 |
|
|
// Bit 28: Target Abort received
|
184 |
|
|
// Bit 27: Caused Target Abort
|
185 |
|
|
// Bit 24: Caused PERR
|
186 |
|
|
// Bit 19: Data Flushed by Master due to Master Abort or Target Abort
|
187 |
|
|
// Bit 18: Discarded a Delayed Read due to timeout
|
188 |
|
|
// Bit 17: Target Retry or Disconnect (document that a Master Retry is requested)
|
189 |
|
|
// Bit 16: Got Illegal sequence of commands over Host Request Bus.
|
190 |
|
|
parameter PCI_HOST_RESPONSE_REPORT_SERR_PERR_M_T_ABORT = 4'h3;
|
191 |
|
|
// Fifth, a Response used to read and write the local PCI Controller's Config Registers.
|
192 |
|
|
// This Response shares it's tags with the WRITE_FENCE Command. Config References
|
193 |
|
|
// can be identified by noticing that Bits 16 or 17 are non-zero.
|
194 |
|
|
// Data Bits [7:0] are the Byte Address of the Config Register being accessed.
|
195 |
|
|
// Data Bits [15:8] are the single-byte Read Data returned when writing the Config Register.
|
196 |
|
|
// Data Bit [16] indicates that a Config Write has been done.
|
197 |
|
|
// Data Bit [17] indicates that a Config Read has been done.
|
198 |
|
|
// This Response will be issued with either Data Bits 16 or 17 set to 1'b1.
|
199 |
|
|
// parameter PCI_HOST_RESPONSE_READ_WRITE_CONFIG_REGISTER = 4'h3;
|
200 |
|
|
// Sixth, Responses indicating that Write Data was delivered, Read Data is available,
|
201 |
|
|
// End Of Burst, and that a Parity Error occurred the previous data cycle.
|
202 |
|
|
// NOTE: If a Master or Target Abort happens, the contents of the Request
|
203 |
|
|
// FIFO will be flushed until the DATA_LAST is removed. The Response FIFO
|
204 |
|
|
// will have a FLUSH entry for each data item flushed by the Master.
|
205 |
|
|
parameter PCI_HOST_RESPONSE_R_DATA_W_SENT = 4'h4;
|
206 |
|
|
parameter PCI_HOST_RESPONSE_R_DATA_W_SENT_PERR = 4'h6;
|
207 |
|
|
parameter PCI_HOST_RESPONSE_R_DATA_W_SENT_LAST = 4'h5;
|
208 |
|
|
parameter PCI_HOST_RESPONSE_R_DATA_W_SENT_LAST_PERR = 4'h7;
|
209 |
|
|
|
210 |
|
|
|
211 |
|
|
// Responses the PCI Controller sends over the Host Response Bus to indicate
|
212 |
|
|
// that an external PCI Master has started a reference.
|
213 |
|
|
// The PCI Controller will do a Target Disconnect on each data phase of a Read
|
214 |
|
|
// in which the Byte Strobes command less than a full 4-byte read.
|
215 |
|
|
// First, the Response which indicates that a Delayed Read must be restarted
|
216 |
|
|
// because a Write by an external PCI Master overlapped the read window.
|
217 |
|
|
parameter PCI_HOST_RESPONSE_EXT_DELAYED_READ_RESTART = 4'h8;
|
218 |
|
|
// Second, the Response which says that all Writes are finished, and the
|
219 |
|
|
// Delayed Read is finally being serviced on the PCI Bus.
|
220 |
|
|
parameter PCI_HOST_RESPONSE_EXT_READ_UNSUSPENDING = 4'h9;
|
221 |
|
|
// Third, the Responses which indicate that an External PCI Master has requested
|
222 |
|
|
// a Read or a Write, depending on the Command.
|
223 |
|
|
parameter PCI_HOST_RESPONSE_EXTERNAL_ADDRESS_COMMAND_READ_WRITE = 4'hA;
|
224 |
|
|
parameter PCI_HOST_RESPONSE_EXTERNAL_ADDRESS_COMMAND_READ_WRITE_SERR = 4'hB;
|
225 |
|
|
// Fourth, the Responses saying Write Data, Read or Write Byte Masks, and End Burst.
|
226 |
|
|
parameter PCI_HOST_RESPONSE_EXT_W_DATA_RW_MASK = 4'hC;
|
227 |
|
|
parameter PCI_HOST_RESPONSE_EXT_W_DATA_RW_MASK_PERR = 4'hD;
|
228 |
|
|
parameter PCI_HOST_RESPONSE_EXT_W_DATA_RW_MASK_LAST = 4'hE;
|
229 |
|
|
parameter PCI_HOST_RESPONSE_EXT_W_DATA_RW_MASK_LAST_PERR = 4'hF;
|
230 |
|
|
|
231 |
|
|
|
232 |
|
|
// Writes from an External PCI Master can be completed immediately based on
|
233 |
|
|
// information available on the Host Response Bus.
|
234 |
|
|
// Reads from an External PCI Master need to be completed in several steps.
|
235 |
|
|
// First, the Address, Command, and one word containing a Read Mask are received.
|
236 |
|
|
// Second, upon receiving a Response indicating that Read is being started, the Host
|
237 |
|
|
// controller must either issue a Write Fence onto the Host Request Bus.
|
238 |
|
|
// Third the Host Controller must start putting Read Data into the Delayed_Read_Data
|
239 |
|
|
// FIFO. The Host Controller can indicate End Of Burst or Target Abort there too.
|
240 |
|
|
// The Host Controller must continue to service Write Requests while the Delayed Read
|
241 |
|
|
// is being acted on. See the PCI Local Bus Spec Revision 2.2 section 3.3.3.3.4
|
242 |
|
|
// If Bus Writes are done while the Delayed Read Data is being fetched, the PCI
|
243 |
|
|
// Bus Interface will watch to see if any writes overlap the Read address region.
|
244 |
|
|
// If a Write overlaps the Read address region, the PCI Interface will ask that the
|
245 |
|
|
// Read be re-issued. The PCI Interface will also start flushing data out of
|
246 |
|
|
// the Delayed_Read_Data FIFO until a DATA_LAST entry is found. The Host Intrface
|
247 |
|
|
// is REQUIRED to put one DATA_LAST or TARGET_ABORT entry into the Delayed_Read_Data
|
248 |
|
|
// FIFO after being instructed to reissue a Delayed Read. All data up to and
|
249 |
|
|
// including that last entry will be flushed, and data following that point will
|
250 |
|
|
// be waited for to satisfy the Delayed Read Request.
|
251 |
|
|
// Tags the Host Controller sends across the Delayed_Read_Data FIFO to indicate
|
252 |
|
|
// progress made on transfers initiated by the external PCI Bus Master.
|
253 |
|
|
parameter PCI_HOST_DELAYED_READ_DATA_SPARE = 3'b000;
|
254 |
|
|
parameter PCI_HOST_DELAYED_READ_DATA_TARGET_ABORT = 3'b001;
|
255 |
|
|
parameter PCI_HOST_DELAYED_READ_DATA_SPARE_2 = 3'b010;
|
256 |
|
|
parameter PCI_HOST_DELAYED_READ_DATA_FAST_RETRY = 3'b011;
|
257 |
|
|
parameter PCI_HOST_DELAYED_READ_DATA_VALID = 3'b100;
|
258 |
|
|
parameter PCI_HOST_DELAYED_READ_DATA_VALID_PERR = 3'b101;
|
259 |
|
|
parameter PCI_HOST_DELAYED_READ_DATA_VALID_LAST = 3'b110;
|
260 |
|
|
parameter PCI_HOST_DELAYED_READ_DATA_VALID_LAST_PERR = 3'b111;
|
261 |
|
|
|
262 |
|
|
|
263 |
|
|
// Macros which are used as paramaters in the Test Device code
|
264 |
|
|
// The Test Device behaves in different ways depending on the Address it is responding to.
|
265 |
|
|
// Select master
|
266 |
|
|
`define Test_Master_0 (3'h0)
|
267 |
|
|
`define Test_Master_1 (3'h1)
|
268 |
|
|
`define Test_Master_2 (3'h2)
|
269 |
|
|
`define Test_Master_3 (3'h3)
|
270 |
|
|
`define Test_Master_Real (3'h7)
|
271 |
|
|
|
272 |
|
|
// Byte Masks
|
273 |
|
|
`define Test_Byte_0 (4'b1110)
|
274 |
|
|
`define Test_Byte_1 (4'b1101)
|
275 |
|
|
`define Test_Byte_2 (4'b1011)
|
276 |
|
|
`define Test_Byte_3 (4'b0111)
|
277 |
|
|
`define Test_Half_0 (4'b1100)
|
278 |
|
|
`define Test_Half_1 (4'b0011)
|
279 |
|
|
`define Test_All_Bytes (4'b0000)
|
280 |
|
|
|
281 |
|
|
// Document that a retry is due to a pending Delayed Read. Master transfers 1 word.
|
282 |
|
|
`define Test_Expect_Delayed_Read_Retry (4'h0)
|
283 |
|
|
// Sizeof the transfer from the Master perspective
|
284 |
|
|
`define Test_One_Word (4'h1)
|
285 |
|
|
`define Test_Two_Words (4'h2)
|
286 |
|
|
`define Test_Three_Words (4'h3)
|
287 |
|
|
`define Test_Four_Words (4'h4)
|
288 |
|
|
`define Test_Eight_Words (4'h8)
|
289 |
|
|
|
290 |
|
|
// Address Parity Error
|
291 |
|
|
`define Test_No_Addr_Perr (1'b0)
|
292 |
|
|
`define Test_Addr_Perr (1'b1)
|
293 |
|
|
|
294 |
|
|
// Data Parity Error
|
295 |
|
|
`define Test_No_Data_Perr (1'b0)
|
296 |
|
|
`define Test_Data_Perr (1'b1)
|
297 |
|
|
|
298 |
|
|
// Master Wait States {[7:4] wait before first data, [3:0] wait between subsequent{
|
299 |
|
|
`define Test_No_Master_WS (8'h00)
|
300 |
|
|
`define Test_One_Master_WS (8'h11)
|
301 |
|
|
// #####################################
|
302 |
|
|
// ADDED on 20.11.2001 by Tadej Markovic
|
303 |
|
|
`define Test_One_Zero_Master_WS (8'h10)
|
304 |
|
|
// #####################################
|
305 |
|
|
|
306 |
|
|
// Target Wait States {[7:4] wait before first data, [3:0] wait between subsequent}
|
307 |
|
|
`define Test_No_Target_WS (8'h00)
|
308 |
|
|
`define Test_One_Target_WS (8'h11)
|
309 |
|
|
// #####################################
|
310 |
|
|
// ADDED on 20.11.2001 by Tadej Markovic
|
311 |
|
|
`define Test_One_Zero_Target_WS (8'h10)
|
312 |
|
|
// #####################################
|
313 |
|
|
|
314 |
|
|
// Target Devsel Speed
|
315 |
|
|
`define Test_Devsel_Fast (2'b00)
|
316 |
|
|
`define Test_Devsel_Medium (2'b01)
|
317 |
|
|
`define Test_Devsel_Slow (2'b10)
|
318 |
|
|
`define Test_Devsel_Subtractive (2'b11)
|
319 |
|
|
|
320 |
|
|
// enable/disable fast back-to-back (until done in controller)
|
321 |
|
|
`define Test_No_Fast_B2B (1'b0)
|
322 |
|
|
`define Test_Fast_B2B (1'b1)
|
323 |
|
|
|
324 |
|
|
// Target Disconnect:
|
325 |
|
|
// None, Before First Data, With First Data,
|
326 |
|
|
// Before Second Data, With Second Data
|
327 |
|
|
`define Test_Target_Normal_Completion (3'h0)
|
328 |
|
|
`define Test_Target_Retry_Before_First (3'h1)
|
329 |
|
|
`define Test_Target_Retry_Before (3'h1)
|
330 |
|
|
`define Test_Target_Disc_With_First (3'h2)
|
331 |
|
|
`define Test_Target_Disc_With (3'h2)
|
332 |
|
|
`define Test_Target_Disc_Before (3'h2)
|
333 |
|
|
`define Test_Target_Retry_Before_Second (3'h3)
|
334 |
|
|
`define Test_Target_Retry_On (3'h3)
|
335 |
|
|
`define Test_Target_Disc_With_Second (3'h4)
|
336 |
|
|
`define Test_Target_Disc_On (3'h4)
|
337 |
|
|
|
338 |
|
|
// Make a Target Retry while starting a Delayed Read
|
339 |
|
|
`define Test_Target_Start_Delayed_Read (3'h5)
|
340 |
|
|
|
341 |
|
|
// Target Abort: Before First Data, Before Second Data
|
342 |
|
|
`define Test_Target_Abort_Before_First (3'h6)
|
343 |
|
|
`define Test_Target_Abort_Before_Second (3'h7)
|
344 |
|
|
`define Test_Target_Abort (3'h7)
|
345 |
|
|
`define Test_Target_Abort_Before (3'h7)
|
346 |
|
|
`define Test_Target_Abort_On (3'h6)
|
347 |
|
|
|
348 |
|
|
// Expect Master Abort
|
349 |
|
|
`define Test_Expect_No_Master_Abort (1'b0)
|
350 |
|
|
`define Test_Expect_Master_Abort (1'b1)
|
351 |
|
|
|
352 |
|
|
// The following defines are used to encode the previous paramaters from
|
353 |
|
|
// the Master to the Target over the PCI Address Bus during testbench references
|
354 |
|
|
/*
|
355 |
|
|
// changed by miha dolenc - added input for target response to device and target models!
|
356 |
|
|
*/
|
357 |
|
|
`define TARGET_ENCODED_TERMINATE_ON 24:15
|
358 |
|
|
`define TARGET_ENCODED_PARAMATERS_ENABLE 25
|
359 |
|
|
`define TARGET_ENCODED_INIT_WAITSTATES 14:11
|
360 |
|
|
`define TARGET_ENCODED_SUBS_WAITSTATES 10:7
|
361 |
|
|
`define TARGET_ENCODED_TERMINATION 6:4
|
362 |
|
|
`define TARGET_ENCODED_DEVSEL_SPEED 3:2
|
363 |
|
|
`define TARGET_ENCODED_DATA_PAR_ERR 1
|
364 |
|
|
`define TARGET_ENCODED_ADDR_PAR_ERR 0
|
365 |
|
|
|
366 |
|
|
|
367 |
|
|
// Value on the AD bus when the bus is Parked, in a wait state, or undriven
|
368 |
|
|
`define BUS_PARK_VALUE (32'hA5A5A5A5)
|
369 |
|
|
`define BUS_WAIT_STATE_VALUE (32'h2BAD2BAD)
|
370 |
|
|
`define BUS_IMPOSSIBLE_VALUE (32'hDEADBEAF)
|
371 |
|
|
|
372 |
|
|
// variables used for debugging and development. These have easy-to-find names
|
373 |
|
|
`define DEBUG_TRUE (1'b1)
|
374 |
|
|
`define DEBUG_FALSE (1'b0)
|
375 |
|
|
|
376 |
|
|
// macro used for documentation purposes when an "if" really should have no "else"
|
377 |
|
|
`define NO_ELSE else
|
378 |
|
|
|
379 |
|
|
// macro used for documentation purposes when an "case" really should have no "default"
|
380 |
|
|
`define NO_DEFAULT default
|
381 |
|
|
|
382 |
|
|
|
383 |
|
|
|