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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  File name "wb_bus_mon.v"                                    ////
////                                                              ////
////  This file is part of the "PCI bridge" project               ////
////  http://www.opencores.org/cores/pci/                         ////
////                                                              ////
////  Author(s):                                                  ////
////      - mihad@opencores.org                                   ////
////      - Miha Dolenc                                           ////
////                                                              ////
////  All additional information is avaliable in the README.pdf   ////
////  file.                                                       ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3  2003/08/03 18:04:44  mihad
// Added limited WISHBONE B3 support for WISHBONE Slave Unit.
// Doesn't support full speed bursts yet.
//
// Revision 1.2  2002/08/13 11:03:51  mihad
// Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image
//
// Revision 1.1  2002/02/01 13:39:43  mihad
// Initial testbench import. Still under development
//
// Revision 1.1  2001/08/06 18:12:58  mihad
// Pocasi delamo kompletno zadevo
//
//
 
`include "pci_testbench_defines.v"
// WISHBONE bus monitor module - it connects to WISHBONE master signals and
// monitors for any illegal combinations appearing on the bus.
module WB_BUS_MON(
                    CLK_I,
                    RST_I,
                            ACK_I,
                    ADDR_O,
                    CYC_O,
                    DAT_I,
                    DAT_O,
                    ERR_I,
                    RTY_I,
                    SEL_O,
                    STB_O,
                    WE_O,
                    TAG_I,
                    TAG_O,
                    CAB_O,
                    check_CTI,
                    log_file_desc
                  ) ;
 
input                           CLK_I  ;
input                           RST_I  ;
input                           ACK_I  ;
input   [(`WB_ADDR_WIDTH-1):0]  ADDR_O ;
input                           CYC_O  ;
input   [(`WB_DATA_WIDTH-1):0]  DAT_I  ;
input   [(`WB_DATA_WIDTH-1):0]  DAT_O  ;
input                           ERR_I  ;
input                           RTY_I  ;
input   [(`WB_SEL_WIDTH-1):0]   SEL_O  ;
input                           STB_O  ;
input                           WE_O   ;
input   [(`WB_TAG_WIDTH-1):0] TAG_I  ;
input   [(`WB_TAG_WIDTH-1):0] TAG_O  ;
input                           CAB_O  ;
input                           check_CTI ;
input [31:0] log_file_desc ;
 
always@(posedge CLK_I)
begin
    if (RST_I !== 1'b0)
    begin
        // when reset is applied, all control signals must be low
        if (CYC_O !== 1'b0)
        begin
            message_out("CYC_O active under reset") ;
        end
 
        if (STB_O !== 1'b0)
        begin
            message_out("STB_O active under reset") ;
        end
 
        if (ACK_I !== 1'b0)
            message_out("ACK_I active under reset") ;
 
        if (ERR_I !== 1'b0)
        begin
            message_out("ERR_I active under reset") ;
        end
 
        if (RTY_I !== 1'b0)
        begin
            message_out("RTY_I active under reset") ;
        end
 
    end // reset
    else
    if (CYC_O !== 1'b1)
    begin
        // when cycle indicator is low, all control signals must be low
        if (STB_O !== 1'b0)
        begin
            message_out("STB_O active without CYC_O being active") ;
        end
 
        if (ACK_I !== 1'b0)
        begin
            message_out("ACK_I active without CYC_O being active") ;
        end
 
        if (ERR_I !== 1'b0)
        begin
            message_out("ERR_I active without CYC_O being active") ;
        end
 
        if (RTY_I !== 1'b0)
        begin
            message_out("RTY_I active without CYC_O being active") ;
        end
 
    end // ~CYC_O
end
 
reg [`WB_DATA_WIDTH-1:0] previous_data_o ;
reg [`WB_DATA_WIDTH-1:0] previous_data_i ;
reg [`WB_ADDR_WIDTH-1:0] previous_address ;
reg [`WB_SEL_WIDTH-1:0] previous_sel ;
reg [`WB_TAG_WIDTH-1:0] previous_tag ;
reg                     previous_stb ;
reg                     previous_ack ;
reg                     previous_err ;
reg                     previous_rty ;
reg                     previous_cyc ;
reg                     previous_we  ;
 
always@(posedge CLK_I or posedge RST_I)
begin
    if (RST_I)
    begin
        previous_stb        <= 1'b0 ;
        previous_ack        <= 1'b0 ;
        previous_err        <= 1'b0 ;
        previous_rty        <= 1'b0 ;
        previous_cyc        <= 1'b0 ;
        previous_tag        <= 'd0  ;
        previous_we         <= 1'b0 ;
        previous_data_o     <= 0    ;
        previous_data_i     <= 0    ;
        previous_address    <= 0    ;
        previous_sel        <= 0    ;
    end
    else
    begin
        previous_stb        <= STB_O    ;
        previous_ack        <= ACK_I    ;
        previous_err        <= ERR_I    ;
        previous_rty        <= RTY_I    ;
        previous_cyc        <= CYC_O    ;
        previous_tag        <= TAG_O    ;
        previous_we         <= WE_O     ;
        previous_data_o     <= DAT_O    ;
        previous_data_i     <= DAT_I    ;
        previous_address    <= ADDR_O   ;
        previous_sel        <= SEL_O    ;
    end
end
 
// cycle monitor
always@(posedge CLK_I)
begin:cycle_monitor_blk
    reg master_can_change ;
    reg slave_can_change  ;
 
    if ((CYC_O !== 1'b0) & (RST_I !== 1'b1)) // cycle in progress
    begin
        // check for two control signals active at same edge
        if ( (ACK_I !== 1'b0) & (RTY_I !== 1'b0) )
        begin
            message_out("ACK_I and RTY_I asserted at the same time during cycle") ;
        end
 
        if ( (ACK_I !== 1'b0) & (ERR_I !== 1'b0) )
        begin
            message_out("ACK_I and ERR_I asserted at the same time during cycle") ;
        end
 
        if ( (RTY_I !== 1'b0) & (ERR_I !== 1'b0) )
        begin
            message_out("RTY_I and ERR_I asserted at the same time during cycle") ;
        end
 
        if (previous_cyc === 1'b1)
        begin
            if (previous_stb === 1'b1)
            begin
                if ((previous_ack === 1'b1) | (previous_rty === 1'b1) | (previous_err === 1'b1))
                    master_can_change = 1'b1 ;
                else
                    master_can_change = 1'b0 ;
            end
            else
            begin
                master_can_change = 1'b1 ;
            end
 
            if ((previous_ack === 1'b1) | (previous_err === 1'b1) | (previous_rty === 1'b1))
            begin
                if (previous_stb === 1'b1)
                    slave_can_change = 1'b1 ;
                else
                    slave_can_change = 1'b0 ;
            end
            else
            begin
                slave_can_change = 1'b1 ;
            end
        end
        else
        begin
            master_can_change = 1'b1 ;
            slave_can_change  = 1'b1 ;
        end
    end
    else
    begin
        master_can_change = 1'b1 ;
        slave_can_change  = 1'b1 ;
    end
 
    if (master_can_change !== 1'b1)
    begin
        if (CYC_O !== previous_cyc)
        begin
            message_out("Master violated WISHBONE protocol by changing the value of CYC_O signal at inappropriate time!") ;
        end
 
        if (STB_O !== previous_stb)
        begin
            message_out("Master violated WISHBONE protocol by changing the value of STB_O signal at inappropriate time!") ;
        end
 
        if (TAG_O !== previous_tag)
        begin
            message_out("Master violated WISHBONE protocol by changing the value of TAG_O signals at inappropriate time!") ;
        end
 
        if (ADDR_O !== previous_address)
        begin
            message_out("Master violated WISHBONE protocol by changing the value of ADR_O signals at inappropriate time!") ;
        end
 
        if (SEL_O !== previous_sel)
        begin
            message_out("Master violated WISHBONE protocol by changing the value of SEL_O signals at inappropriate time!") ;
        end
 
        if (WE_O !== previous_we)
        begin
            message_out("Master violated WISHBONE protocol by changing the value of WE_O signal at inappropriate time!") ;
        end
 
        if (WE_O !== 1'b0)
        begin
            if (DAT_O !== previous_data_o)
            begin
                message_out("Master violated WISHBONE protocol by changing the value of DAT_O signals at inappropriate time!") ;
            end
        end
    end
 
    if (slave_can_change !== 1'b1)
    begin
        if (previous_ack !== ACK_I)
        begin
            message_out("Slave violated WISHBONE protocol by changing the value of ACK_O signal at inappropriate time!") ;
        end
 
        if (previous_rty !== RTY_I)
        begin
            message_out("Slave violated WISHBONE protocol by changing the value of RTY_O signal at inappropriate time!") ;
        end
 
        if (previous_err !== ERR_I)
        begin
            message_out("Slave violated WISHBONE protocol by changing the value of ERR_O signal at inappropriate time!") ;
        end
 
        if (previous_data_i !== DAT_I)
        begin
            message_out("Slave violated WISHBONE protocol by changing the value of DAT_O signals at inappropriate time!") ;
        end
    end
end // cycle monitor
 
// CAB_O monitor - CAB_O musn't change during one cycle
reg [1:0] first_cab_val ;
always@(posedge CLK_I or RST_I)
begin
    if ((CYC_O === 0) || RST_I)
        first_cab_val <= 2'b00 ;
    else
    begin
        // cycle in progress - is this first clock edge in a cycle ?
        if (first_cab_val[1] === 1'b0)
            first_cab_val <= {1'b1, CAB_O} ;
        else if ( first_cab_val[0] !== CAB_O )
        begin
            $display("CAB_O value changed during cycle") ;
            $fdisplay(log_file_desc, "CAB_O value changed during cycle") ;
        end
    end
end // CAB_O monitor
 
// CTI_O[2:0] (TAG_O[4:2]) monitor for bursts
reg [2:0] first_cti_val ;
always@(posedge CLK_I or posedge RST_I)
begin
    if (RST_I)
        first_cti_val <= 3'b000 ;
    // logging for burst cycle
    else if ( check_CTI && ((CYC_O === 0) && (first_cti_val == 3'b011) && ~(previous_rty || previous_err)))
    begin
        message_out("Master violated WISHBONE protocol by NOT changing the CTI_O signals to '111' when end of burst!") ;
        $display("CTI_O didn't change to '111' when end of burst") ;
        $fdisplay(log_file_desc, "CTI_O didn't change to '111' when end of burst") ;
        first_cti_val <= 3'b000 ;
    end
    else if (CYC_O === 0)
        first_cti_val <= 3'b000 ;
    else
    begin
        if ((first_cti_val == 3'b000) && (TAG_O[4:2] === 3'b000) && (ACK_I || ERR_I || RTY_I))
            first_cti_val <= 3'b001 ;
        else if ((first_cti_val == 3'b000) && (TAG_O[4:2] === 3'b111) && (ACK_I || ERR_I || RTY_I))
            first_cti_val <= 3'b010 ;
        else if ((first_cti_val == 3'b000) && (TAG_O[4:2] === 3'b010) && (ACK_I || ERR_I || RTY_I))
            first_cti_val <= 3'b011 ;
        else if ((first_cti_val == 3'b011) && (TAG_O[4:2] === 3'b111) && (ACK_I || ERR_I || RTY_I))
            first_cti_val <= 3'b010 ;
        // logging for clasic cycles
        else if (check_CTI && ((first_cti_val == 3'b001) && (TAG_O[4:2] !== 3'b000)))
        begin
            message_out("Master violated WISHBONE protocol by changing the CTI_O signals during CYC_O when clasic cycle!") ;
            $display("CTI_O change during CYC_O when clasic cycle") ;
            $fdisplay(log_file_desc, "CTI_O change during CYC_O when clasic cycle") ;
        end
        // logging for end of burs cycle
        else if (check_CTI && (first_cti_val == 3'b010))
        begin
            message_out("Master violated WISHBONE protocol by changing the CTI_O signals to '111' before end of burst!") ;
            $display("CTI_O change to '111' before end of burst") ;
            $fdisplay(log_file_desc, "CTI_O change to '111' before end of burst") ;
        end
    end
end
 
// WE_O monitor for consecutive address bursts
reg [1:0] first_we_val ;
always@(posedge CLK_I or posedge RST_I)
begin
    if (~CYC_O || ~CAB_O || RST_I)
        first_we_val <= 2'b00 ;
    else
    if (STB_O)
    begin
        // cycle in progress - is this first clock edge in a cycle ?
        if (first_we_val[1] == 1'b0)
            first_we_val <= {1'b1, WE_O} ;
        else if ( first_we_val[0] != WE_O )
        begin
            $display("WE_O value changed during CAB cycle") ;
            $fdisplay(log_file_desc, "WE_O value changed during CAB cycle") ;
        end
    end
end // CAB_O monitor
 
// address monitor for consecutive address bursts
reg [`WB_ADDR_WIDTH:0] address ;
always@(posedge CLK_I or posedge RST_I)
begin
    if (~CYC_O || ~CAB_O || RST_I)
        address <= {(`WB_ADDR_WIDTH + 1){1'b0}} ;
    else
    begin
        if (STB_O && ACK_I)
        begin
            if (address[`WB_ADDR_WIDTH] == 1'b0)
            begin
                address <= (ADDR_O + `WB_SEL_WIDTH) | { 1'b1, {`WB_ADDR_WIDTH{1'b0}} } ;
            end
            else
            begin
                if ( address[(`WB_ADDR_WIDTH-1):0] != ADDR_O)
                begin
                    $display("Expected ADR_O = 0x%h, Actual = 0x%h", address[(`WB_ADDR_WIDTH-1):0], ADDR_O) ;
                    message_out("Consecutive address burst address incrementing incorrect") ;
                end
                else
                    address <= (ADDR_O + `WB_SEL_WIDTH) | { 1'b1, {`WB_ADDR_WIDTH{1'b0}} } ;
            end
        end
    end
end // address monitor
 
// data monitor
always@(posedge CLK_I or posedge RST_I)
begin:data_monitor_blk
    reg                       last_valid_we     ;
    reg [`WB_SEL_WIDTH - 1:0] last_valid_sel    ;
 
    if ((CYC_O !== 1'b0) & (RST_I !== 1'b1))
    begin
        if (STB_O !== 1'b0)
        begin
            last_valid_we   = WE_O  ;
            last_valid_sel  = SEL_O ;
 
            if ( (ADDR_O ^ ADDR_O) !== 0 )
            begin
                message_out("Master provided invalid ADR_O and qualified it with STB_O") ;
            end
 
            if ( (SEL_O ^ SEL_O) !== 0 )
            begin
                message_out("Master provided invalid SEL_O and qualified it with STB_O") ;
            end
 
            if ( WE_O )
            begin
                if (
                    ( SEL_O[0] & ((DAT_O[ 7:0 ] ^ DAT_O[ 7:0 ]) !== 0) ) |
                    ( SEL_O[1] & ((DAT_O[15:8 ] ^ DAT_O[15:8 ]) !== 0) ) |
                    ( SEL_O[2] & ((DAT_O[23:16] ^ DAT_O[23:16]) !== 0) ) |
                    ( SEL_O[3] & ((DAT_O[31:24] ^ DAT_O[31:24]) !== 0) )
                   )
                begin
                    message_out("Master provided invalid data during write and qualified it with STB_O") ;
                    $display("Byte select value: SEL_O = %b, Data bus value: DAT_O =  %h ", SEL_O, DAT_O) ;
                    $fdisplay(log_file_desc, "Byte select value: SEL_O = %b, Data bus value: DAT_O =  %h ", SEL_O, DAT_O) ;
                end
            end
 
            if ((TAG_O ^ TAG_O) !== 0)
            begin
                message_out("Master provided invalid TAG_O and qualified it with STB_O!") ;
            end
        end
 
        if ((last_valid_we !== 1'b1) & (ACK_I !== 1'b0))
        begin
            if (
                ( SEL_O[0] & ((DAT_I[ 7:0 ] ^ DAT_I[ 7:0 ]) !== 0) ) |
                ( SEL_O[1] & ((DAT_I[15:8 ] ^ DAT_I[15:8 ]) !== 0) ) |
                ( SEL_O[2] & ((DAT_I[23:16] ^ DAT_I[23:16]) !== 0) ) |
                ( SEL_O[3] & ((DAT_I[31:24] ^ DAT_I[31:24]) !== 0) )
               )
            begin
                message_out("Slave provided invalid data during read and qualified it with ACK_I") ;
                $display("Byte select value: SEL_O = %b, Data bus value: DAT_I =  %h ", last_valid_sel, DAT_I) ;
                $fdisplay(log_file_desc, "Byte select value: SEL_O = %b, Data bus value: DAT_I =  %h ", last_valid_sel, DAT_I) ;
            end
        end
    end
    else
    begin
        last_valid_sel = {`WB_SEL_WIDTH{1'bx}} ;
        last_valid_we  = 1'bx ;
    end
end
 
task message_out ;
    input [7999:0] message_i ;
begin
    $display("Time: %t", $time) ;
    $display("%m, %0s", message_i) ;
    $fdisplay(log_file_desc, "Time: %t", $time) ;
    $fdisplay(log_file_desc, "%m, %0s", message_i) ;
end
endtask // display message
 
endmodule // BUS_MON

Line No.	Rev	Author	Line
1	15	mihad	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// File name "wb_bus_mon.v" ////`
4			`//// ////`
5			`//// This file is part of the "PCI bridge" project ////`
6			`//// http://www.opencores.org/cores/pci/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - mihad@opencores.org ////`
10			`//// - Miha Dolenc ////`
11			`//// ////`
12			`//// All additional information is avaliable in the README.pdf ////`
13			`//// file. ////`
14			`//// ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42			`//`
43			`// CVS Revision History`
44			`//`
45			`// $Log: not supported by cvs2svn $`
46	119	tadejm	`// Revision 1.3 2003/08/03 18:04:44 mihad`
47			`// Added limited WISHBONE B3 support for WISHBONE Slave Unit.`
48			`// Doesn't support full speed bursts yet.`
49			`//`
50	106	mihad	`// Revision 1.2 2002/08/13 11:03:51 mihad`
51			`// Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image`
52			`//`
53	45	mihad	`// Revision 1.1 2002/02/01 13:39:43 mihad`
54			`// Initial testbench import. Still under development`
55			`//`
56	15	mihad	`// Revision 1.1 2001/08/06 18:12:58 mihad`
57			`// Pocasi delamo kompletno zadevo`
58			`//`
59			`//`
60
61			`include "pci_testbench_defines.v"
62			`// WISHBONE bus monitor module - it connects to WISHBONE master signals and`
63			`// monitors for any illegal combinations appearing on the bus.`
64			`module WB_BUS_MON(`
65			`CLK_I,`
66			`RST_I,`
67			`ACK_I,`
68			`ADDR_O,`
69			`CYC_O,`
70			`DAT_I,`
71			`DAT_O,`
72			`ERR_I,`
73			`RTY_I,`
74			`SEL_O,`
75			`STB_O,`
76			`WE_O,`
77			`TAG_I,`
78			`TAG_O,`
79			`CAB_O,`
80	119	tadejm	`check_CTI,`
81	15	mihad	`log_file_desc`
82			`) ;`
83
84			`input CLK_I ;`
85			`input RST_I ;`
86			`input ACK_I ;`
87			input [(`WB_ADDR_WIDTH-1):0] ADDR_O ;
88			`input CYC_O ;`
89			input [(`WB_DATA_WIDTH-1):0] DAT_I ;
90			input [(`WB_DATA_WIDTH-1):0] DAT_O ;
91			`input ERR_I ;`
92			`input RTY_I ;`
93			input [(`WB_SEL_WIDTH-1):0] SEL_O ;
94			`input STB_O ;`
95			`input WE_O ;`
96			input [(`WB_TAG_WIDTH-1):0] TAG_I ;
97			input [(`WB_TAG_WIDTH-1):0] TAG_O ;
98			`input CAB_O ;`
99	119	tadejm	`input check_CTI ;`
100	15	mihad	`input [31:0] log_file_desc ;`
101
102	106	mihad	`always@(posedge CLK_I)`
103	15	mihad	`begin`
104	106	mihad	`if (RST_I !== 1'b0)`
105	15	mihad	`begin`
106			`// when reset is applied, all control signals must be low`
107	106	mihad	`if (CYC_O !== 1'b0)`
108	15	mihad	`begin`
109	106	mihad	`message_out("CYC_O active under reset") ;`
110	15	mihad	`end`
111	106	mihad
112			`if (STB_O !== 1'b0)`
113	15	mihad	`begin`
114	106	mihad	`message_out("STB_O active under reset") ;`
115	15	mihad	`end`
116	106	mihad
117			`if (ACK_I !== 1'b0)`
118			`message_out("ACK_I active under reset") ;`
119
120			`if (ERR_I !== 1'b0)`
121	15	mihad	`begin`
122	106	mihad	`message_out("ERR_I active under reset") ;`
123	15	mihad	`end`
124	106	mihad
125			`if (RTY_I !== 1'b0)`
126	15	mihad	`begin`
127	106	mihad	`message_out("RTY_I active under reset") ;`
128	15	mihad	`end`
129	106	mihad
130	15	mihad	`end // reset`
131			`else`
132	106	mihad	`if (CYC_O !== 1'b1)`
133	15	mihad	`begin`
134			`// when cycle indicator is low, all control signals must be low`
135	106	mihad	`if (STB_O !== 1'b0)`
136	15	mihad	`begin`
137	106	mihad	`message_out("STB_O active without CYC_O being active") ;`
138	15	mihad	`end`
139	106	mihad
140			`if (ACK_I !== 1'b0)`
141	15	mihad	`begin`
142	106	mihad	`message_out("ACK_I active without CYC_O being active") ;`
143	15	mihad	`end`
144	106	mihad
145			`if (ERR_I !== 1'b0)`
146	15	mihad	`begin`
147	106	mihad	`message_out("ERR_I active without CYC_O being active") ;`
148	15	mihad	`end`
149	106	mihad
150			`if (RTY_I !== 1'b0)`
151	15	mihad	`begin`
152	106	mihad	`message_out("RTY_I active without CYC_O being active") ;`
153	15	mihad	`end`
154	106	mihad
155	15	mihad	`end // ~CYC_O`
156			`end`
157
158	106	mihad	reg [`WB_DATA_WIDTH-1:0] previous_data_o ;
159			reg [`WB_DATA_WIDTH-1:0] previous_data_i ;
160	15	mihad	reg [`WB_ADDR_WIDTH-1:0] previous_address ;
161			reg [`WB_SEL_WIDTH-1:0] previous_sel ;
162	106	mihad	reg [`WB_TAG_WIDTH-1:0] previous_tag ;
163	45	mihad	`reg previous_stb ;`
164			`reg previous_ack ;`
165			`reg previous_err ;`
166			`reg previous_rty ;`
167			`reg previous_cyc ;`
168	106	mihad	`reg previous_we ;`
169	15	mihad
170			`always@(posedge CLK_I or posedge RST_I)`
171			`begin`
172	45	mihad	`if (RST_I)`
173			`begin`
174	106	mihad	`previous_stb <= 1'b0 ;`
175			`previous_ack <= 1'b0 ;`
176			`previous_err <= 1'b0 ;`
177			`previous_rty <= 1'b0 ;`
178			`previous_cyc <= 1'b0 ;`
179			`previous_tag <= 'd0 ;`
180			`previous_we <= 1'b0 ;`
181			`previous_data_o <= 0 ;`
182			`previous_data_i <= 0 ;`
183			`previous_address <= 0 ;`
184			`previous_sel <= 0 ;`
185	45	mihad	`end`
186			`else`
187			`begin`
188	106	mihad	`previous_stb <= STB_O ;`
189			`previous_ack <= ACK_I ;`
190			`previous_err <= ERR_I ;`
191			`previous_rty <= RTY_I ;`
192			`previous_cyc <= CYC_O ;`
193			`previous_tag <= TAG_O ;`
194			`previous_we <= WE_O ;`
195			`previous_data_o <= DAT_O ;`
196			`previous_data_i <= DAT_I ;`
197			`previous_address <= ADDR_O ;`
198			`previous_sel <= SEL_O ;`
199	45	mihad	`end`
200			`end`
201
202			`// cycle monitor`
203			`always@(posedge CLK_I)`
204	106	mihad	`begin:cycle_monitor_blk`
205			`reg master_can_change ;`
206			`reg slave_can_change ;`
207
208			`if ((CYC_O !== 1'b0) & (RST_I !== 1'b1)) // cycle in progress`
209	15	mihad	`begin`
210	106	mihad	`// check for two control signals active at same edge`
211			`if ( (ACK_I !== 1'b0) & (RTY_I !== 1'b0) )`
212	15	mihad	`begin`
213	106	mihad	`message_out("ACK_I and RTY_I asserted at the same time during cycle") ;`
214			`end`
215	15	mihad
216	106	mihad	`if ( (ACK_I !== 1'b0) & (ERR_I !== 1'b0) )`
217			`begin`
218			`message_out("ACK_I and ERR_I asserted at the same time during cycle") ;`
219			`end`
220	15	mihad
221	106	mihad	`if ( (RTY_I !== 1'b0) & (ERR_I !== 1'b0) )`
222			`begin`
223			`message_out("RTY_I and ERR_I asserted at the same time during cycle") ;`
224			`end`
225	15	mihad
226	106	mihad	`if (previous_cyc === 1'b1)`
227			`begin`
228			`if (previous_stb === 1'b1)`
229			`begin`
230			`if ((previous_ack === 1'b1) \| (previous_rty === 1'b1) \| (previous_err === 1'b1))`
231			`master_can_change = 1'b1 ;`
232			`else`
233			`master_can_change = 1'b0 ;`
234	15	mihad	`end`
235			`else`
236			`begin`
237	106	mihad	`master_can_change = 1'b1 ;`
238	15	mihad	`end`
239
240	106	mihad	`if ((previous_ack === 1'b1) \| (previous_err === 1'b1) \| (previous_rty === 1'b1))`
241	15	mihad	`begin`
242	106	mihad	`if (previous_stb === 1'b1)`
243			`slave_can_change = 1'b1 ;`
244			`else`
245			`slave_can_change = 1'b0 ;`
246	15	mihad	`end`
247	106	mihad	`else`
248	15	mihad	`begin`
249	106	mihad	`slave_can_change = 1'b1 ;`
250	15	mihad	`end`
251	106	mihad	`end`
252			`else`
253			`begin`
254			`master_can_change = 1'b1 ;`
255			`slave_can_change = 1'b1 ;`
256			`end`
257			`end`
258			`else`
259			`begin`
260			`master_can_change = 1'b1 ;`
261			`slave_can_change = 1'b1 ;`
262			`end`
263	15	mihad
264	106	mihad	`if (master_can_change !== 1'b1)`
265			`begin`
266			`if (CYC_O !== previous_cyc)`
267			`begin`
268			`message_out("Master violated WISHBONE protocol by changing the value of CYC_O signal at inappropriate time!") ;`
269			`end`
270
271			`if (STB_O !== previous_stb)`
272			`begin`
273			`message_out("Master violated WISHBONE protocol by changing the value of STB_O signal at inappropriate time!") ;`
274			`end`
275
276			`if (TAG_O !== previous_tag)`
277			`begin`
278			`message_out("Master violated WISHBONE protocol by changing the value of TAG_O signals at inappropriate time!") ;`
279			`end`
280
281			`if (ADDR_O !== previous_address)`
282			`begin`
283			`message_out("Master violated WISHBONE protocol by changing the value of ADR_O signals at inappropriate time!") ;`
284			`end`
285
286			`if (SEL_O !== previous_sel)`
287			`begin`
288			`message_out("Master violated WISHBONE protocol by changing the value of SEL_O signals at inappropriate time!") ;`
289			`end`
290
291			`if (WE_O !== previous_we)`
292			`begin`
293			`message_out("Master violated WISHBONE protocol by changing the value of WE_O signal at inappropriate time!") ;`
294			`end`
295
296			`if (WE_O !== 1'b0)`
297			`begin`
298			`if (DAT_O !== previous_data_o)`
299	45	mihad	`begin`
300	106	mihad	`message_out("Master violated WISHBONE protocol by changing the value of DAT_O signals at inappropriate time!") ;`
301	45	mihad	`end`
302	106	mihad	`end`
303			`end`
304	45	mihad
305	106	mihad	`if (slave_can_change !== 1'b1)`
306	45	mihad	`begin`
307	106	mihad	`if (previous_ack !== ACK_I)`
308	45	mihad	`begin`
309	106	mihad	`message_out("Slave violated WISHBONE protocol by changing the value of ACK_O signal at inappropriate time!") ;`
310	45	mihad	`end`
311	106	mihad
312			`if (previous_rty !== RTY_I)`
313			`begin`
314			`message_out("Slave violated WISHBONE protocol by changing the value of RTY_O signal at inappropriate time!") ;`
315			`end`
316
317			`if (previous_err !== ERR_I)`
318			`begin`
319			`message_out("Slave violated WISHBONE protocol by changing the value of ERR_O signal at inappropriate time!") ;`
320			`end`
321
322			`if (previous_data_i !== DAT_I)`
323			`begin`
324			`message_out("Slave violated WISHBONE protocol by changing the value of DAT_O signals at inappropriate time!") ;`
325			`end`
326	45	mihad	`end`
327	15	mihad	`end // cycle monitor`
328
329			`// CAB_O monitor - CAB_O musn't change during one cycle`
330			`reg [1:0] first_cab_val ;`
331			`always@(posedge CLK_I or RST_I)`
332			`begin`
333			`if ((CYC_O === 0) \|\| RST_I)`
334			`first_cab_val <= 2'b00 ;`
335			`else`
336			`begin`
337			`// cycle in progress - is this first clock edge in a cycle ?`
338			`if (first_cab_val[1] === 1'b0)`
339			`first_cab_val <= {1'b1, CAB_O} ;`
340			`else if ( first_cab_val[0] !== CAB_O )`
341			`begin`
342			`$display("CAB_O value changed during cycle") ;`
343			`$fdisplay(log_file_desc, "CAB_O value changed during cycle") ;`
344			`end`
345			`end`
346			`end // CAB_O monitor`
347
348	119	tadejm	`// CTI_O[2:0] (TAG_O[4:2]) monitor for bursts`
349			`reg [2:0] first_cti_val ;`
350			`always@(posedge CLK_I or posedge RST_I)`
351			`begin`
352			`if (RST_I)`
353			`first_cti_val <= 3'b000 ;`
354			`// logging for burst cycle`
355			`else if ( check_CTI && ((CYC_O === 0) && (first_cti_val == 3'b011) && ~(previous_rty \|\| previous_err)))`
356			`begin`
357			`message_out("Master violated WISHBONE protocol by NOT changing the CTI_O signals to '111' when end of burst!") ;`
358			`$display("CTI_O didn't change to '111' when end of burst") ;`
359			`$fdisplay(log_file_desc, "CTI_O didn't change to '111' when end of burst") ;`
360			`first_cti_val <= 3'b000 ;`
361			`end`
362			`else if (CYC_O === 0)`
363			`first_cti_val <= 3'b000 ;`
364			`else`
365			`begin`
366			`if ((first_cti_val == 3'b000) && (TAG_O[4:2] === 3'b000) && (ACK_I \|\| ERR_I \|\| RTY_I))`
367			`first_cti_val <= 3'b001 ;`
368			`else if ((first_cti_val == 3'b000) && (TAG_O[4:2] === 3'b111) && (ACK_I \|\| ERR_I \|\| RTY_I))`
369			`first_cti_val <= 3'b010 ;`
370			`else if ((first_cti_val == 3'b000) && (TAG_O[4:2] === 3'b010) && (ACK_I \|\| ERR_I \|\| RTY_I))`
371			`first_cti_val <= 3'b011 ;`
372			`else if ((first_cti_val == 3'b011) && (TAG_O[4:2] === 3'b111) && (ACK_I \|\| ERR_I \|\| RTY_I))`
373			`first_cti_val <= 3'b010 ;`
374			`// logging for clasic cycles`
375			`else if (check_CTI && ((first_cti_val == 3'b001) && (TAG_O[4:2] !== 3'b000)))`
376			`begin`
377			`message_out("Master violated WISHBONE protocol by changing the CTI_O signals during CYC_O when clasic cycle!") ;`
378			`$display("CTI_O change during CYC_O when clasic cycle") ;`
379			`$fdisplay(log_file_desc, "CTI_O change during CYC_O when clasic cycle") ;`
380			`end`
381			`// logging for end of burs cycle`
382			`else if (check_CTI && (first_cti_val == 3'b010))`
383			`begin`
384			`message_out("Master violated WISHBONE protocol by changing the CTI_O signals to '111' before end of burst!") ;`
385			`$display("CTI_O change to '111' before end of burst") ;`
386			`$fdisplay(log_file_desc, "CTI_O change to '111' before end of burst") ;`
387			`end`
388			`end`
389			`end`
390
391	15	mihad	`// WE_O monitor for consecutive address bursts`
392			`reg [1:0] first_we_val ;`
393			`always@(posedge CLK_I or posedge RST_I)`
394			`begin`
395			`if (~CYC_O \|\| ~CAB_O \|\| RST_I)`
396			`first_we_val <= 2'b00 ;`
397			`else`
398			`if (STB_O)`
399			`begin`
400			`// cycle in progress - is this first clock edge in a cycle ?`
401			`if (first_we_val[1] == 1'b0)`
402			`first_we_val <= {1'b1, WE_O} ;`
403			`else if ( first_we_val[0] != WE_O )`
404			`begin`
405			`$display("WE_O value changed during CAB cycle") ;`
406			`$fdisplay(log_file_desc, "WE_O value changed during CAB cycle") ;`
407			`end`
408			`end`
409			`end // CAB_O monitor`
410
411			`// address monitor for consecutive address bursts`
412			reg [`WB_ADDR_WIDTH:0] address ;
413			`always@(posedge CLK_I or posedge RST_I)`
414			`begin`
415			`if (~CYC_O \|\| ~CAB_O \|\| RST_I)`
416			address <= {(`WB_ADDR_WIDTH + 1){1'b0}} ;
417			`else`
418			`begin`
419			`if (STB_O && ACK_I)`
420			`begin`
421			if (address[`WB_ADDR_WIDTH] == 1'b0)
422	106	mihad	`begin`
423			address <= (ADDR_O + `WB_SEL_WIDTH) \| { 1'b1, {`WB_ADDR_WIDTH{1'b0}} } ;
424			`end`
425	15	mihad	`else`
426			`begin`
427			if ( address[(`WB_ADDR_WIDTH-1):0] != ADDR_O)
428			`begin`
429	106	mihad	$display("Expected ADR_O = 0x%h, Actual = 0x%h", address[(`WB_ADDR_WIDTH-1):0], ADDR_O) ;
430			`message_out("Consecutive address burst address incrementing incorrect") ;`
431	15	mihad	`end`
432			`else`
433	106	mihad	address <= (ADDR_O + `WB_SEL_WIDTH) \| { 1'b1, {`WB_ADDR_WIDTH{1'b0}} } ;
434	15	mihad	`end`
435			`end`
436			`end`
437			`end // address monitor`
438
439			`// data monitor`
440			`always@(posedge CLK_I or posedge RST_I)`
441	106	mihad	`begin:data_monitor_blk`
442			`reg last_valid_we ;`
443			reg [`WB_SEL_WIDTH - 1:0] last_valid_sel ;
444
445			`if ((CYC_O !== 1'b0) & (RST_I !== 1'b1))`
446	15	mihad	`begin`
447	106	mihad	`if (STB_O !== 1'b0)`
448	15	mihad	`begin`
449	106	mihad	`last_valid_we = WE_O ;`
450			`last_valid_sel = SEL_O ;`
451
452			`if ( (ADDR_O ^ ADDR_O) !== 0 )`
453	15	mihad	`begin`
454	106	mihad	`message_out("Master provided invalid ADR_O and qualified it with STB_O") ;`
455	15	mihad	`end`
456	106	mihad
457			`if ( (SEL_O ^ SEL_O) !== 0 )`
458			`begin`
459			`message_out("Master provided invalid SEL_O and qualified it with STB_O") ;`
460			`end`
461	15	mihad
462	106	mihad	`if ( WE_O )`
463			`begin`
464			`if (`
465			`( SEL_O[0] & ((DAT_O[ 7:0 ] ^ DAT_O[ 7:0 ]) !== 0) ) \|`
466			`( SEL_O[1] & ((DAT_O[15:8 ] ^ DAT_O[15:8 ]) !== 0) ) \|`
467			`( SEL_O[2] & ((DAT_O[23:16] ^ DAT_O[23:16]) !== 0) ) \|`
468			`( SEL_O[3] & ((DAT_O[31:24] ^ DAT_O[31:24]) !== 0) )`
469			`)`
470			`begin`
471			`message_out("Master provided invalid data during write and qualified it with STB_O") ;`
472			`$display("Byte select value: SEL_O = %b, Data bus value: DAT_O = %h ", SEL_O, DAT_O) ;`
473			`$fdisplay(log_file_desc, "Byte select value: SEL_O = %b, Data bus value: DAT_O = %h ", SEL_O, DAT_O) ;`
474			`end`
475			`end`
476
477			`if ((TAG_O ^ TAG_O) !== 0)`
478			`begin`
479			`message_out("Master provided invalid TAG_O and qualified it with STB_O!") ;`
480			`end`
481	15	mihad	`end`
482	106	mihad
483			`if ((last_valid_we !== 1'b1) & (ACK_I !== 1'b0))`
484	15	mihad	`begin`
485			`if (`
486	106	mihad	`( SEL_O[0] & ((DAT_I[ 7:0 ] ^ DAT_I[ 7:0 ]) !== 0) ) \|`
487			`( SEL_O[1] & ((DAT_I[15:8 ] ^ DAT_I[15:8 ]) !== 0) ) \|`
488			`( SEL_O[2] & ((DAT_I[23:16] ^ DAT_I[23:16]) !== 0) ) \|`
489			`( SEL_O[3] & ((DAT_I[31:24] ^ DAT_I[31:24]) !== 0) )`
490	15	mihad	`)`
491			`begin`
492	106	mihad	`message_out("Slave provided invalid data during read and qualified it with ACK_I") ;`
493			`$display("Byte select value: SEL_O = %b, Data bus value: DAT_I = %h ", last_valid_sel, DAT_I) ;`
494			`$fdisplay(log_file_desc, "Byte select value: SEL_O = %b, Data bus value: DAT_I = %h ", last_valid_sel, DAT_I) ;`
495	15	mihad	`end`
496			`end`
497			`end`
498	106	mihad	`else`
499			`begin`
500			last_valid_sel = {`WB_SEL_WIDTH{1'bx}} ;

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[/] [pci/] [tags/] [rel_WB_B3/] [bench/] [verilog/] [wb_bus_mon.v] - Blame information for rev 154