URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_WB_B3/] [sim/] [rtl_sim/] [log/] [example_pci_tb.log] - Blame information for rev 154

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Line No.	Rev	Author	Line
1	30	mihad	`********************** PCI IP Core Testbench Test results **********************`
2
3			`*****************************************************************************************`
4			`At time 98835000`
5			`Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCI`
6			`reported SUCCESSFULL!`
7			`*****************************************************************************************`
8
9			`*****************************************************************************************`
10			`At time 99300000`
11			`Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCI`
12			`reported SUCCESSFULL!`
13			`*****************************************************************************************`
14
15			`*****************************************************************************************`
16			`At time 99735000`
17			`Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCI`
18			`reported SUCCESSFULL!`
19			`*****************************************************************************************`
20
21			`*****************************************************************************************`
22			`At time 100200000`
23			`Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCI`
24			`reported SUCCESSFULL!`
25			`*****************************************************************************************`
26
27			`*****************************************************************************************`
28			`At time 101595000`
29			`Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCI`
30			`reported SUCCESSFULL!`
31			`*****************************************************************************************`
32
33			`*****************************************************************************************`
34			`At time 102165000`
35			`Test CAB MEMORY READ THROUGH WB SLAVE FROM PCI`
36			`reported SUCCESSFULL!`
37			`*****************************************************************************************`
38
39			`*****************************************************************************************`
40			`At time 102825000`
41			`Test CAB MEMORY READ THROUGH WB SLAVE FROM PCI`
42			`reported SUCCESSFULL!`
43			`*****************************************************************************************`
44
45			`*****************************************************************************************`
46			`At time 103515000`
47			`Test CAB MEMORY READ THROUGH WB SLAVE FROM PCI`
48			`reported SUCCESSFULL!`
49			`*****************************************************************************************`
50
51			`*****************************************************************************************`
52			`At time 104175000`
53			`Test CAB MEMORY READ THROUGH WB SLAVE FROM PCI`
54			`reported SUCCESSFULL!`
55			`*****************************************************************************************`
56
57			`*****************************************************************************************`
58			`At time 105700000`
59			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
60			`reported SUCCESSFULL!`
61			`*****************************************************************************************`
62
63			`*****************************************************************************************`
64			`At time 105700000`
65			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
66			`reported SUCCESSFULL!`
67			`*****************************************************************************************`
68
69			`*****************************************************************************************`
70			`At time 105700000`
71			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
72			`reported SUCCESSFULL!`
73			`*****************************************************************************************`
74
75			`*****************************************************************************************`
76			`At time 105700000`
77			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
78			`reported SUCCESSFULL!`
79			`*****************************************************************************************`
80
81			`*****************************************************************************************`
82			`At time 106300000`
83			`Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
84			`reported SUCCESSFULL!`
85			`*****************************************************************************************`
86
87			`*****************************************************************************************`
88			`At time 107700000`
89			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
90			`reported SUCCESSFULL!`
91			`*****************************************************************************************`
92
93			`*****************************************************************************************`
94			`At time 107700000`
95			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
96			`reported SUCCESSFULL!`
97			`*****************************************************************************************`
98
99			`*****************************************************************************************`
100			`At time 107700000`
101			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
102			`reported SUCCESSFULL!`
103			`*****************************************************************************************`
104
105			`*****************************************************************************************`
106			`At time 107700000`
107			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
108			`reported SUCCESSFULL!`
109			`*****************************************************************************************`
110
111			`*****************************************************************************************`
112			`At time 108300000`
113			`Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
114			`reported SUCCESSFULL!`
115			`*****************************************************************************************`
116
117			`*****************************************************************************************`
118			`At time 111300000`
119			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
120			`reported SUCCESSFULL!`
121			`*****************************************************************************************`
122
123			`*****************************************************************************************`
124			`At time 111300000`
125			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
126			`reported SUCCESSFULL!`
127			`*****************************************************************************************`
128
129			`*****************************************************************************************`
130			`At time 111300000`
131			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
132			`reported SUCCESSFULL!`
133			`*****************************************************************************************`
134
135			`*****************************************************************************************`
136			`At time 111300000`
137			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
138			`reported SUCCESSFULL!`
139			`*****************************************************************************************`
140
141			`*****************************************************************************************`
142			`At time 112000000`
143			`Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
144			`reported SUCCESSFULL!`
145			`*****************************************************************************************`
146
147			`*****************************************************************************************`
148			`At time 112635000`
149			`Test I/O WRITE TRANSACTION FROM WB TO PCI TEST`
150			`reported SUCCESSFULL!`
151			`*****************************************************************************************`
152
153			`*****************************************************************************************`
154			`At time 113220000`
155			`Test I/O READ TRANSACTION FROM WB TO PCI TEST`
156			`reported SUCCESSFULL!`
157			`*****************************************************************************************`
158
159			`*****************************************************************************************`
160			`At time 113820000`
161			`Test I/O READ TRANSACTION FROM WB TO PCI TEST`
162			`reported SUCCESSFULL!`
163			`*****************************************************************************************`
164
165			`*****************************************************************************************`
166			`At time 114825000`
167			`Test CHECK MAXIMUM IMAGE SIZE`
168			`reported SUCCESSFULL!`
169			`*****************************************************************************************`
170
171			`*****************************************************************************************`
172			`At time 115420000`
173			`Test CHECK MAXIMUM IMAGE SIZE`
174			`reported SUCCESSFULL!`
175			`*****************************************************************************************`
176
177			`*****************************************************************************************`
178			`At time 117105000`
179			`Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCI`
180			`reported SUCCESSFULL!`
181			`*****************************************************************************************`
182
183			`*****************************************************************************************`
184			`At time 117580000`
185			`Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCI`
186			`reported SUCCESSFULL!`
187			`*****************************************************************************************`
188
189			`*****************************************************************************************`
190			`At time 118005000`
191			`Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCI`
192			`reported SUCCESSFULL!`
193			`*****************************************************************************************`
194
195			`*****************************************************************************************`
196			`At time 118480000`
197			`Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCI`
198			`reported SUCCESSFULL!`
199			`*****************************************************************************************`
200
201			`*****************************************************************************************`
202			`At time 119895000`
203			`Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCI`
204			`reported SUCCESSFULL!`
205			`*****************************************************************************************`
206
207			`*****************************************************************************************`
208			`At time 120465000`
209			`Test CAB MEMORY READ THROUGH WB SLAVE FROM PCI`
210			`reported SUCCESSFULL!`
211			`*****************************************************************************************`
212
213			`*****************************************************************************************`
214			`At time 121125000`
215			`Test CAB MEMORY READ THROUGH WB SLAVE FROM PCI`
216			`reported SUCCESSFULL!`
217			`*****************************************************************************************`
218
219			`*****************************************************************************************`
220			`At time 121815000`
221			`Test CAB MEMORY READ THROUGH WB SLAVE FROM PCI`
222			`reported SUCCESSFULL!`
223			`*****************************************************************************************`
224
225			`*****************************************************************************************`
226			`At time 122475000`
227			`Test CAB MEMORY READ THROUGH WB SLAVE FROM PCI`
228			`reported SUCCESSFULL!`
229			`*****************************************************************************************`
230
231			`*****************************************************************************************`
232			`At time 124000000`
233			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
234			`reported SUCCESSFULL!`
235			`*****************************************************************************************`
236
237			`*****************************************************************************************`
238			`At time 124000000`
239			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
240			`reported SUCCESSFULL!`
241			`*****************************************************************************************`
242
243			`*****************************************************************************************`
244			`At time 124000000`
245			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
246			`reported SUCCESSFULL!`
247			`*****************************************************************************************`
248
249			`*****************************************************************************************`
250			`At time 124000000`
251			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
252			`reported SUCCESSFULL!`
253			`*****************************************************************************************`
254
255			`*****************************************************************************************`
256			`At time 124600000`
257			`Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
258			`reported SUCCESSFULL!`
259			`*****************************************************************************************`
260
261			`*****************************************************************************************`
262			`At time 126000000`
263			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
264			`reported SUCCESSFULL!`
265			`*****************************************************************************************`
266
267			`*****************************************************************************************`
268			`At time 126000000`
269			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
270			`reported SUCCESSFULL!`
271			`*****************************************************************************************`
272
273			`*****************************************************************************************`
274			`At time 126000000`
275			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
276			`reported SUCCESSFULL!`
277			`*****************************************************************************************`
278
279			`*****************************************************************************************`
280			`At time 126000000`
281			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
282			`reported SUCCESSFULL!`
283			`*****************************************************************************************`
284
285			`*****************************************************************************************`
286			`At time 126600000`
287			`Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
288			`reported SUCCESSFULL!`
289			`*****************************************************************************************`
290
291			`*****************************************************************************************`
292			`At time 129600000`
293			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
294			`reported SUCCESSFULL!`
295			`*****************************************************************************************`
296
297			`*****************************************************************************************`
298			`At time 129600000`
299			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
300			`reported SUCCESSFULL!`
301			`*****************************************************************************************`
302
303			`*****************************************************************************************`
304			`At time 129600000`
305			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
306			`reported SUCCESSFULL!`
307			`*****************************************************************************************`
308
309			`*****************************************************************************************`
310			`At time 129600000`
311			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
312			`reported SUCCESSFULL!`
313			`*****************************************************************************************`
314
315			`*****************************************************************************************`
316			`At time 130300000`
317			`Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
318			`reported SUCCESSFULL!`
319			`*****************************************************************************************`
320
321			`*****************************************************************************************`
322			`At time 130935000`
323			`Test I/O WRITE TRANSACTION FROM WB TO PCI TEST`
324			`reported SUCCESSFULL!`
325			`*****************************************************************************************`
326
327			`*****************************************************************************************`
328			`At time 131520000`
329			`Test I/O READ TRANSACTION FROM WB TO PCI TEST`
330			`reported SUCCESSFULL!`
331			`*****************************************************************************************`
332
333			`*****************************************************************************************`
334			`At time 132120000`
335			`Test I/O READ TRANSACTION FROM WB TO PCI TEST`
336			`reported SUCCESSFULL!`
337			`*****************************************************************************************`
338
339			`*****************************************************************************************`
340			`At time 133125000`
341			`Test CHECK MAXIMUM IMAGE SIZE`
342			`reported SUCCESSFULL!`
343			`*****************************************************************************************`
344
345			`*****************************************************************************************`
346			`At time 133720000`
347			`Test CHECK MAXIMUM IMAGE SIZE`
348			`reported SUCCESSFULL!`
349			`*****************************************************************************************`
350
351			`*****************************************************************************************`
352			`At time 135405000`
353			`Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCI`
354			`reported SUCCESSFULL!`
355			`*****************************************************************************************`
356
357			`*****************************************************************************************`
358			`At time 135880000`
359			`Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCI`
360			`reported SUCCESSFULL!`
361			`*****************************************************************************************`
362
363			`*****************************************************************************************`
364			`At time 136305000`
365			`Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCI`
366			`reported SUCCESSFULL!`
367			`*****************************************************************************************`
368
369			`*****************************************************************************************`
370			`At time 136780000`
371			`Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCI`
372			`reported SUCCESSFULL!`
373			`*****************************************************************************************`
374
375			`*****************************************************************************************`
376			`At time 138195000`
377			`Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCI`
378			`reported SUCCESSFULL!`
379			`*****************************************************************************************`
380
381			`*****************************************************************************************`
382			`At time 138765000`
383			`Test CAB MEMORY READ THROUGH WB SLAVE FROM PCI`
384			`reported SUCCESSFULL!`
385			`*****************************************************************************************`
386
387			`*****************************************************************************************`
388			`At time 139425000`
389			`Test CAB MEMORY READ THROUGH WB SLAVE FROM PCI`
390			`reported SUCCESSFULL!`
391			`*****************************************************************************************`
392
393			`*****************************************************************************************`
394			`At time 140115000`
395			`Test CAB MEMORY READ THROUGH WB SLAVE FROM PCI`
396			`reported SUCCESSFULL!`
397			`*****************************************************************************************`
398
399			`*****************************************************************************************`
400			`At time 140775000`
401			`Test CAB MEMORY READ THROUGH WB SLAVE FROM PCI`
402			`reported SUCCESSFULL!`
403			`*****************************************************************************************`
404
405			`*****************************************************************************************`
406			`At time 142300000`
407			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
408			`reported SUCCESSFULL!`
409			`*****************************************************************************************`
410
411			`*****************************************************************************************`
412			`At time 142300000`
413			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
414			`reported SUCCESSFULL!`
415			`*****************************************************************************************`
416
417			`*****************************************************************************************`
418			`At time 142300000`
419			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
420			`reported SUCCESSFULL!`
421			`*****************************************************************************************`
422
423			`*****************************************************************************************`
424			`At time 142300000`
425			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
426			`reported SUCCESSFULL!`
427			`*****************************************************************************************`
428
429			`*****************************************************************************************`
430			`At time 142900000`
431			`Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
432			`reported SUCCESSFULL!`
433			`*****************************************************************************************`
434
435			`*****************************************************************************************`
436			`At time 144300000`
437			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
438			`reported SUCCESSFULL!`
439			`*****************************************************************************************`
440
441			`*****************************************************************************************`
442			`At time 144300000`
443			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
444			`reported SUCCESSFULL!`
445			`*****************************************************************************************`
446
447			`*****************************************************************************************`
448			`At time 144300000`
449			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
450			`reported SUCCESSFULL!`
451			`*****************************************************************************************`
452
453			`*****************************************************************************************`
454			`At time 144300000`
455			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
456			`reported SUCCESSFULL!`
457			`*****************************************************************************************`
458
459			`*****************************************************************************************`
460			`At time 144900000`
461			`Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
462			`reported SUCCESSFULL!`
463			`*****************************************************************************************`
464
465			`*****************************************************************************************`
466			`At time 147900000`
467			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
468			`reported SUCCESSFULL!`
469			`*****************************************************************************************`
470
471			`*****************************************************************************************`
472			`At time 147900000`
473			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
474			`reported SUCCESSFULL!`
475			`*****************************************************************************************`
476
477			`*****************************************************************************************`
478			`At time 147900000`
479			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
480			`reported SUCCESSFULL!`
481			`*****************************************************************************************`
482
483			`*****************************************************************************************`
484			`At time 147900000`
485			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
486			`reported SUCCESSFULL!`
487			`*****************************************************************************************`
488
489			`*****************************************************************************************`
490			`At time 148600000`
491			`Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
492			`reported SUCCESSFULL!`
493			`*****************************************************************************************`
494
495			`*****************************************************************************************`
496			`At time 149235000`
497			`Test I/O WRITE TRANSACTION FROM WB TO PCI TEST`
498			`reported SUCCESSFULL!`
499			`*****************************************************************************************`
500
501			`*****************************************************************************************`
502			`At time 149820000`
503			`Test I/O READ TRANSACTION FROM WB TO PCI TEST`
504			`reported SUCCESSFULL!`
505			`*****************************************************************************************`
506
507			`*****************************************************************************************`
508			`At time 150420000`
509			`Test I/O READ TRANSACTION FROM WB TO PCI TEST`
510			`reported SUCCESSFULL!`
511			`*****************************************************************************************`
512
513			`*****************************************************************************************`
514			`At time 151425000`
515			`Test CHECK MAXIMUM IMAGE SIZE`
516			`reported SUCCESSFULL!`
517			`*****************************************************************************************`
518
519			`*****************************************************************************************`
520			`At time 152020000`
521			`Test CHECK MAXIMUM IMAGE SIZE`
522			`reported SUCCESSFULL!`
523			`*****************************************************************************************`
524
525			`*****************************************************************************************`
526			`At time 153400000`
527			`Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVE`
528			`reported SUCCESSFULL!`
529			`*****************************************************************************************`
530
531			`*****************************************************************************************`
532			`At time 153500000`
533			`Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVE`
534			`reported SUCCESSFULL!`
535			`*****************************************************************************************`
536
537			`*****************************************************************************************`
538			`At time 153700000`
539			`Test ERRONEOUS CAB MEMORY READ TO WB SLAVE`
540			`reported SUCCESSFULL!`
541			`*****************************************************************************************`
542
543			`*****************************************************************************************`
544			`At time 154580000`
545			`Test ERRONEOUS I/O WRITE TO WB SLAVE`
546			`reported SUCCESSFULL!`
547			`*****************************************************************************************`
548
549			`*****************************************************************************************`
550			`At time 154680000`
551			`Test ERRONEOUS I/O READ TO WB SLAVE`
552			`reported SUCCESSFULL!`
553			`*****************************************************************************************`
554
555			`*****************************************************************************************`
556			`At time 154780000`
557			`Test CAB I/O WRITE TO WB SLAVE`
558			`reported SUCCESSFULL!`
559			`*****************************************************************************************`
560
561			`*****************************************************************************************`
562			`At time 154880000`
563			`Test CAB I/O READ TO WB SLAVE`
564			`reported SUCCESSFULL!`
565			`*****************************************************************************************`
566
567			`*****************************************************************************************`
568			`At time 155240000`
569			`Test ERRONEOUS WB CONFIGURATION WRITE ACCESS`
570			`reported SUCCESSFULL!`
571			`*****************************************************************************************`
572
573			`*****************************************************************************************`
574			`At time 155360000`
575			`Test ERRONEOUS WB CONFIGURATION READ ACCESS`
576			`reported SUCCESSFULL!`
577			`*****************************************************************************************`
578
579			`*****************************************************************************************`
580			`At time 155480000`
581			`Test WB CAB CONFIGURATION WRITE ACCESS`
582			`reported SUCCESSFULL!`
583			`*****************************************************************************************`
584
585			`*****************************************************************************************`
586			`At time 155600000`
587			`Test WB CAB CONFIGURATION READ ACCESS`
588			`reported SUCCESSFULL!`
589			`*****************************************************************************************`
590
591			`*****************************************************************************************`
592			`At time 158145000`
593			`Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITES`
594			`reported SUCCESSFULL!`
595			`*****************************************************************************************`
596
597			`*****************************************************************************************`
598			`At time 158460000`
599			`Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERROR`
600			`reported SUCCESSFULL!`
601			`*****************************************************************************************`
602
603			`*****************************************************************************************`
604			`At time 158540000`
605			`Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERROR`
606			`reported SUCCESSFULL!`
607			`*****************************************************************************************`
608
609			`*****************************************************************************************`
610			`At time 158820000`
611			`Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORT`
612			`reported SUCCESSFULL!`
613			`*****************************************************************************************`
614
615			`*****************************************************************************************`
616			`At time 159945000`
617			`Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITE`
618			`reported SUCCESSFULL!`
619			`*****************************************************************************************`
620
621			`*****************************************************************************************`
622			`At time 161080000`
623			`Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERROR`
624			`reported SUCCESSFULL!`
625			`*****************************************************************************************`
626
627			`*****************************************************************************************`
628			`At time 161800000`
629			`Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERROR`
630			`reported SUCCESSFULL!`
631			`*****************************************************************************************`
632
633			`*****************************************************************************************`
634			`At time 162060000`
635			`Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEM`
636			`reported SUCCESSFULL!`
637			`*****************************************************************************************`
638
639			`*****************************************************************************************`
640			`At time 166180000`
641			`Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READS`
642			`reported SUCCESSFULL!`
643			`*****************************************************************************************`
644
645			`*****************************************************************************************`
646			`At time 166440000`
647			`Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READ`
648			`reported SUCCESSFULL!`
649			`*****************************************************************************************`
650
651			`*****************************************************************************************`
652			`At time 167880000`
653			`Test CHECK NORMAL READ AFTER ERROR TERMINATED READ`
654			`reported SUCCESSFULL!`
655			`*****************************************************************************************`
656
657			`*****************************************************************************************`
658			`At time 168160000`
659			`Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READ`
660			`reported SUCCESSFULL!`
661			`*****************************************************************************************`
662
663			`*****************************************************************************************`
664			`At time 169780000`
665			`Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCI`
666			`reported SUCCESSFULL!`
667			`*****************************************************************************************`
668
669			`*****************************************************************************************`
670			`At time 170040000`
671			`Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORT`
672			`reported SUCCESSFULL!`
673			`*****************************************************************************************`
674
675			`*****************************************************************************************`
676			`At time 171855000`
677			`Test TARGET ABORT ERROR ON SINGLE WRITE`
678			`reported SUCCESSFULL!`
679			`*****************************************************************************************`
680
681			`*****************************************************************************************`
682			`At time 172185000`
683			`Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORT`
684			`reported SUCCESSFULL!`
685			`*****************************************************************************************`
686
687			`*****************************************************************************************`
688			`At time 172700000`
689			`Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORT`
690			`reported SUCCESSFULL!`
691			`*****************************************************************************************`
692
693			`*****************************************************************************************`
694			`At time 172980000`
695			`Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORT`
696			`reported SUCCESSFULL!`
697			`*****************************************************************************************`
698
699			`*****************************************************************************************`
700			`At time 173260000`
701			`Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORT`
702			`reported SUCCESSFULL!`
703			`*****************************************************************************************`
704
705			`*****************************************************************************************`
706			`At time 173520000`
707			`Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORT`
708			`reported SUCCESSFULL!`
709			`*****************************************************************************************`
710
711			`*****************************************************************************************`
712			`At time 174435000`
713			`Test TARGET ABORT ERROR ON CAB MEMORY WRITE`
714			`reported SUCCESSFULL!`
715			`*****************************************************************************************`
716
717			`*****************************************************************************************`
718			`At time 174720000`
719			`Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORT`
720			`reported SUCCESSFULL!`
721			`*****************************************************************************************`
722
723			`*****************************************************************************************`
724			`At time 175260000`
725			`Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORT`
726			`reported SUCCESSFULL!`
727			`*****************************************************************************************`
728
729			`*****************************************************************************************`
730			`At time 175540000`
731			`Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORT`
732			`reported SUCCESSFULL!`
733			`*****************************************************************************************`
734
735			`*****************************************************************************************`
736			`At time 177645000`
737			`Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITE`
738			`reported SUCCESSFULL!`
739			`*****************************************************************************************`
740
741			`*****************************************************************************************`
742			`At time 177940000`
743			`Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORT`
744			`reported SUCCESSFULL!`
745			`*****************************************************************************************`
746
747			`*****************************************************************************************`
748			`At time 178480000`
749			`Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORT`
750			`reported SUCCESSFULL!`
751			`*****************************************************************************************`
752
753			`*****************************************************************************************`
754			`At time 178560000`
755			`Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGER`
756			`reported SUCCESSFULL!`
757			`*****************************************************************************************`
758
759			`*****************************************************************************************`
760			`At time 179320000`
761			`Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITE`
762			`reported SUCCESSFULL!`
763			`*****************************************************************************************`
764
765			`*****************************************************************************************`
766			`At time 180060000`
767			`Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITS`
768			`reported SUCCESSFULL!`
769			`*****************************************************************************************`
770
771			`*****************************************************************************************`
772			`At time 180940000`
773			`Test TARGET ABORT DURING SINGLE MEMORY READ`
774			`reported SUCCESSFULL!`
775			`*****************************************************************************************`
776
777			`*****************************************************************************************`
778			`At time 181200000`
779			`Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORT`
780			`reported SUCCESSFULL!`
781			`*****************************************************************************************`
782
783			`*****************************************************************************************`
784			`At time 181480000`
785			`Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORT`
786			`reported SUCCESSFULL!`
787			`*****************************************************************************************`
788
789			`*****************************************************************************************`
790			`At time 181960000`
791			`Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORT`
792			`reported SUCCESSFULL!`
793			`*****************************************************************************************`
794
795			`*****************************************************************************************`
796			`At time 182800000`
797			`Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READ`
798			`reported SUCCESSFULL!`
799			`*****************************************************************************************`
800
801			`*****************************************************************************************`
802			`At time 183060000`
803			`Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORT`
804			`reported SUCCESSFULL!`
805			`*****************************************************************************************`
806
807			`*****************************************************************************************`
808			`At time 184320000`
809			`Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READ`
810			`reported SUCCESSFULL!`
811			`*****************************************************************************************`
812
813			`*****************************************************************************************`
814			`At time 185540000`
815			`Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READ`
816			`reported SUCCESSFULL!`
817			`*****************************************************************************************`
818
819			`*****************************************************************************************`
820			`At time 185820000`
821			`Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORT`
822			`reported SUCCESSFULL!`
823			`*****************************************************************************************`
824
825			`*****************************************************************************************`
826			`At time 187080000`
827			`Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READ`
828			`reported SUCCESSFULL!`
829			`*****************************************************************************************`
830
831			`*****************************************************************************************`
832			`At time 187725000`
833			`Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITE`
834			`reported SUCCESSFULL!`
835			`*****************************************************************************************`
836
837			`*****************************************************************************************`
838			`At time 188020000`
839			`Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITE`
840			`reported SUCCESSFULL!`
841			`*****************************************************************************************`
842
843			`*****************************************************************************************`
844			`At time 188560000`
845			`Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITE`
846			`reported SUCCESSFULL!`
847			`*****************************************************************************************`
848
849			`*****************************************************************************************`
850			`At time 188820000`
851			`Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITE`
852			`reported SUCCESSFULL!`
853			`*****************************************************************************************`
854
855			`*****************************************************************************************`
856			`At time 189480000`
857			`Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITE`
858			`reported SUCCESSFULL!`
859			`*****************************************************************************************`
860
861			`*****************************************************************************************`
862			`At time 192945000`
863			`Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE`
864			`reported SUCCESSFULL!`
865			`*****************************************************************************************`
866
867			`*****************************************************************************************`
868			`At time 193300000`
869			`Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE`
870			`reported SUCCESSFULL!`
871			`*****************************************************************************************`
872
873			`*****************************************************************************************`
874			`At time 193995000`
875			`Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLED`
876			`reported SUCCESSFULL!`
877			`*****************************************************************************************`
878
879			`*****************************************************************************************`
880			`At time 194340000`
881			`Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLED`
882			`reported SUCCESSFULL!`
883			`*****************************************************************************************`
884
885			`*****************************************************************************************`
886			`At time 194955000`
887			`Test MASTER WRITE WITH NO PARITY ERRORS`
888			`reported SUCCESSFULL!`
889			`*****************************************************************************************`
890
891			`*****************************************************************************************`
892			`At time 195400000`
893			`Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITE`
894			`reported SUCCESSFULL!`
895			`*****************************************************************************************`
896
897			`*****************************************************************************************`
898			`At time 196360000`
899			`Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READS`
900			`reported SUCCESSFULL!`
901			`*****************************************************************************************`
902
903			`*****************************************************************************************`
904			`At time 196520000`
905			`Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERROR`
906			`reported SUCCESSFULL!`
907			`*****************************************************************************************`
908
909			`*****************************************************************************************`
910			`At time 196800000`
911			`Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR`
912			`reported SUCCESSFULL!`
913			`*****************************************************************************************`
914
915			`*****************************************************************************************`
916			`At time 197280000`
917			`Test INTERRUPT STATUS REGISTER AFTER MASTER READ PARITY ERROR`
918			`reported SUCCESSFULL!`
919			`*****************************************************************************************`
920
921			`*****************************************************************************************`
922			`At time 197660000`
923			`Test CLEARANCE OF PARITY INTERRUPT STATUSES`
924			`reported SUCCESSFULL!`
925			`*****************************************************************************************`
926
927			`*****************************************************************************************`
928			`At time 198240000`
929			`Test NO PERR ASSERTION ON MASTER READ WITH PAR. ERR. RESPONSE DISABLED`
930			`reported SUCCESSFULL!`
931			`*****************************************************************************************`
932
933			`*****************************************************************************************`
934			`At time 198420000`
935			`Test INTERRUPT REQUEST CHECK AFTER READ PARITY ERROR WITH PARITY ERROR RESPONSE DISABLED`
936			`reported SUCCESSFULL!`
937			`*****************************************************************************************`
938
939			`*****************************************************************************************`
940			`At time 198700000`
941			`Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR`
942			`reported SUCCESSFULL!`
943			`*****************************************************************************************`
944
945			`*****************************************************************************************`
946			`At time 199180000`
947			`Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER READ PARITY ERROR WITH PAR. ERR. RESPONSE DISABLED`
948			`reported SUCCESSFULL!`
949			`*****************************************************************************************`
950
951			`*****************************************************************************************`
952			`At time 200140000`
953			`Test MASTER READ TRANSACTION WITH NO PARITY ERRORS`
954			`reported SUCCESSFULL!`
955			`*****************************************************************************************`
956
957			`*****************************************************************************************`
958			`At time 200400000`
959			`Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL READ`
960			`reported SUCCESSFULL!`
961			`*****************************************************************************************`
962
963			`*****************************************************************************************`
964			`At time 200680000`
965			`Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL READ`
966			`reported SUCCESSFULL!`
967			`*****************************************************************************************`
968
969			`*****************************************************************************************`
970			`At time 201375000`
971			`Test NO SERR ASSERTION AFTER ADDRESS PARITY ERROR, SERR DISABLED AND PAR. ERR. RESPONSE ENABLED`
972			`reported SUCCESSFULL!`
973			`*****************************************************************************************`
974
975			`*****************************************************************************************`
976			`At time 201660000`
977			`Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLED`
978			`reported SUCCESSFULL!`
979			`*****************************************************************************************`
980
981			`*****************************************************************************************`
982			`At time 202275000`
983			`Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLED`
984			`reported SUCCESSFULL!`
985			`*****************************************************************************************`
986
987			`*****************************************************************************************`
988			`At time 202605000`
989			`Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLED`
990			`reported SUCCESSFULL!`
991			`*****************************************************************************************`
992
993			`*****************************************************************************************`
994			`At time 202900000`
995			`Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLED`
996			`reported SUCCESSFULL!`
997			`*****************************************************************************************`
998
999			`*****************************************************************************************`
1000			`At time 203385000`
1001			`Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR DISABLED, PAR. RESP. ENABLED`
1002			`reported SUCCESSFULL!`
1003			`*****************************************************************************************`
1004
1005			`*****************************************************************************************`
1006			`At time 203580000`
1007			`Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR`
1008			`reported SUCCESSFULL!`
1009			`*****************************************************************************************`
1010
1011			`*****************************************************************************************`
1012			`At time 203860000`
1013			`Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLED`
1014			`reported SUCCESSFULL!`
1015			`*****************************************************************************************`
1016
1017			`*****************************************************************************************`
1018			`At time 204340000`
1019			`Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND SERR DISABLED`
1020			`reported SUCCESSFULL!`
1021			`*****************************************************************************************`
1022
1023			`*****************************************************************************************`
1024			`At time 204887000`
1025			`Test ADDRESS PARITY ERROR RESPONSE WITH SERR AND PARITY ERROR RESPONSE ENABLED`
1026			`reported SUCCESSFULL!`
1027			`*****************************************************************************************`
1028
1029			`*****************************************************************************************`
1030			`At time 205080000`
1031			`Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCI`
1032			`reported SUCCESSFULL!`
1033			`*****************************************************************************************`
1034
1035			`*****************************************************************************************`
1036			`At time 205360000`
1037			`Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCI`
1038			`reported SUCCESSFULL!`
1039			`*****************************************************************************************`
1040
1041			`*****************************************************************************************`
1042			`At time 205840000`
1043			`Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCI`
1044			`reported SUCCESSFULL!`
1045			`*****************************************************************************************`
1046
1047			`*****************************************************************************************`
1048			`At time 206445000`
1049			`Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLED`
1050			`reported SUCCESSFULL!`
1051			`*****************************************************************************************`
1052
1053			`*****************************************************************************************`
1054			`At time 206640000`
1055			`Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCI`
1056			`reported SUCCESSFULL!`
1057			`*****************************************************************************************`
1058
1059			`*****************************************************************************************`
1060			`At time 206920000`
1061			`Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCI`
1062			`reported SUCCESSFULL!`
1063			`*****************************************************************************************`
1064
1065			`*****************************************************************************************`
1066			`At time 207400000`
1067			`Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCI`
1068			`reported SUCCESSFULL!`
1069			`*****************************************************************************************`
1070
1071			`*****************************************************************************************`
1072			`At time 207885000`
1073			`Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLED`
1074			`reported SUCCESSFULL!`
1075			`*****************************************************************************************`
1076
1077			`*****************************************************************************************`
1078			`At time 208080000`
1079			`Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCI`
1080			`reported SUCCESSFULL!`
1081			`*****************************************************************************************`
1082
1083			`*****************************************************************************************`
1084			`At time 208360000`
1085			`Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCI`
1086			`reported SUCCESSFULL!`
1087			`*****************************************************************************************`
1088
1089			`*****************************************************************************************`
1090			`At time 208840000`
1091			`Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCI`
1092			`reported SUCCESSFULL!`
1093			`*****************************************************************************************`
1094
1095			`*****************************************************************************************`
1096			`At time 209325000`
1097			`Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. ENABLED`
1098			`reported SUCCESSFULL!`
1099			`*****************************************************************************************`
1100
1101			`*****************************************************************************************`
1102			`At time 209520000`
1103			`Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR WAS PRESENTED ON PCI`
1104			`reported SUCCESSFULL!`
1105			`*****************************************************************************************`
1106
1107			`*****************************************************************************************`
1108			`At time 209800000`
1109			`Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCI`
1110			`reported SUCCESSFULL!`
1111			`*****************************************************************************************`
1112
1113			`*****************************************************************************************`
1114			`At time 210280000`
1115			`Test INTERRUPT STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR ON PCI`
1116			`reported SUCCESSFULL!`
1117			`*****************************************************************************************`
1118
1119			`*****************************************************************************************`
1120			`At time 210975000`
1121			`Test NO SERR ASSERTION ON ADDRESS PARITY ERROR WITH SERR ENABLED AND PAR. ERR. RESPONSE DISABLED`
1122			`reported SUCCESSFULL!`
1123			`*****************************************************************************************`
1124
1125			`*****************************************************************************************`
1126			`At time 211160000`
1127			`Test INTERRUPT REQUEST AFTER ADDR. PARITY ERROR WITH PERR RESPONSE DISABLED`
1128			`reported SUCCESSFULL!`
1129			`*****************************************************************************************`
1130
1131			`*****************************************************************************************`
1132			`At time 211440000`
1133			`Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLED`
1134			`reported SUCCESSFULL!`
1135			`*****************************************************************************************`
1136
1137			`*****************************************************************************************`
1138			`At time 211920000`
1139			`Test INTERRUPT STATUS REGISTER VALUE AFTER ADDR PERR WITH PERR RESPONSE DISABLED`
1140			`reported SUCCESSFULL!`
1141			`*****************************************************************************************`
1142
1143			`*****************************************************************************************`
1144			`At time 212535000`
1145			`Test ADDRESS PARITY ERROR ON FIRST DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLED`
1146			`reported SUCCESSFULL!`
1147			`*****************************************************************************************`
1148
1149			`*****************************************************************************************`
1150			`At time 212865000`
1151			`Test ADDRESS PARITY ERROR ON SECOND DATA PHASE OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLED`
1152			`reported SUCCESSFULL!`
1153			`*****************************************************************************************`
1154
1155			`*****************************************************************************************`
1156			`At time 213160000`
1157			`Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLED`
1158			`reported SUCCESSFULL!`
1159			`*****************************************************************************************`
1160
1161			`*****************************************************************************************`
1162			`At time 213645000`
1163			`Test ADDRESS PARITY ERROR ON BOTH DATA PHASES OF DUAL ADDRESS CYCLE - SERR ENABLED, PAR. RESP. DISABLED`
1164			`reported SUCCESSFULL!`
1165			`*****************************************************************************************`
1166
1167			`*****************************************************************************************`
1168			`At time 213840000`
1169			`Test INTERRUPT REQUEST AFTER ADDRESS PARITY ERROR`
1170			`reported SUCCESSFULL!`
1171			`*****************************************************************************************`
1172
1173			`*****************************************************************************************`
1174			`At time 214120000`
1175			`Test PCI DEVICE STATUS REGISTER VALUE AFTER ADDRESS PARITY ERROR AND PERR DISABLED`
1176			`reported SUCCESSFULL!`
1177			`*****************************************************************************************`
1178
1179			`*****************************************************************************************`
1180			`At time 214635000`
1181			`Test EXTERNAL WRITE WITH NO PARITY ERRORS`
1182			`reported SUCCESSFULL!`
1183			`*****************************************************************************************`
1184
1185			`*****************************************************************************************`
1186			`At time 214820000`
1187			`Test INTERRUPT REQUESTS AFTER NORMAL EXTERNAL MASTER WRITE`
1188			`reported SUCCESSFULL!`
1189			`*****************************************************************************************`
1190
1191			`*****************************************************************************************`
1192			`At time 215100000`
1193			`Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITE`
1194			`reported SUCCESSFULL!`
1195			`*****************************************************************************************`
1196
1197			`*****************************************************************************************`
1198			`At time 215580000`
1199			`Test INTERRUPT STATUS REGISTER VALUE AFTER NORMAL EXTERNAL MASTER WRITE`
1200			`reported SUCCESSFULL!`
1201			`*****************************************************************************************`
1202
1203			`*****************************************************************************************`
1204			`At time 217065000`
1205			`Test INVALID PAR ON WRITE REFERENCE THROUGH BRIDGE'S TARGET - PERR RESPONSE ENABLED`
1206			`reported SUCCESSFULL!`
1207			`*****************************************************************************************`
1208
1209			`*****************************************************************************************`
1210			`At time 217260000`
1211			`Test INTERRUPT REQUESTS AFTER TARGET WRITE REFERENCE PARITY ERROR`
1212			`reported SUCCESSFULL!`
1213			`*****************************************************************************************`
1214
1215			`*****************************************************************************************`
1216			`At time 217540000`
1217			`Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCE`
1218			`reported SUCCESSFULL!`
1219			`*****************************************************************************************`
1220
1221			`*****************************************************************************************`
1222			`At time 218020000`
1223			`Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET REFERENCE`
1224			`reported SUCCESSFULL!`
1225			`*****************************************************************************************`
1226
1227			`*****************************************************************************************`
1228			`At time 218925000`
1229			`Test PARITY ERROR HANDLING ON TARGET READ REFERENCE`
1230			`reported SUCCESSFULL!`
1231			`*****************************************************************************************`
1232
1233			`*****************************************************************************************`
1234			`At time 219120000`
1235			`Test INTERRUPT REQUESTS AFTER PERR ON READ REFERENCE THROUGH BRIDGE'S TARGET`
1236			`reported SUCCESSFULL!`
1237			`*****************************************************************************************`
1238
1239			`*****************************************************************************************`
1240			`At time 219400000`
1241			`Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCE`
1242			`reported SUCCESSFULL!`
1243			`*****************************************************************************************`
1244
1245			`*****************************************************************************************`
1246			`At time 219880000`
1247			`Test INTERRUPT STATUS REGISTER VALUE AFTER PARITY ERROR ON TARGET READ REFERENCE`
1248			`reported SUCCESSFULL!`
1249			`*****************************************************************************************`
1250
1251			`*****************************************************************************************`
1252			`At time 222945000`
1253			`Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED FIRST TIME`
1254			`reported SUCCESSFULL!`
1255			`*****************************************************************************************`
1256
1257			`*****************************************************************************************`
1258			`At time 223185000`
1259			`Test SINGLE POSTED WRITE FROM WISHBONE TO PCI RETRIED SECOND TIME`
1260			`reported SUCCESSFULL!`
1261			`*****************************************************************************************`
1262
1263			`*****************************************************************************************`
1264			`At time 223425000`
1265			`Test SINGLE POSTED WRITE FROM WISHBONE TO PCI DISCONNECTED`
1266			`reported SUCCESSFULL!`
1267			`*****************************************************************************************`
1268
1269			`*****************************************************************************************`
1270			`At time 223935000`
1271			`Test BURST LENGTH 2 POSTED WRITE STARTS WITH RETRY`
1272			`reported SUCCESSFULL!`
1273			`*****************************************************************************************`
1274
1275			`*****************************************************************************************`
1276			`At time 224205000`
1277			`Test BURST LENGTH 2 POSTED WRITE RETRIED SECOND TIME DISCONNECTED ON FIRST DATAPHASE`
1278			`reported SUCCESSFULL!`
1279			`*****************************************************************************************`
1280
1281			`*****************************************************************************************`
1282			`At time 224445000`
1283			`Test BURST LENGTH 2 POSTED WRITE NORMAL COMPLETION AFTER DISCONNECT`
1284			`reported SUCCESSFULL!`
1285			`*****************************************************************************************`
1286
1287			`*****************************************************************************************`
1288			`At time 225075000`
1289			`Test BURST LENGTH 2 POSTED WRITE DISCONNECTED AFTER FIRST DATAPHASE FIRST TIME`
1290			`reported SUCCESSFULL!`
1291			`*****************************************************************************************`
1292
1293			`*****************************************************************************************`
1294			`At time 225315000`
1295			`Test BURST LENGTH 2 POSTED WRITE DISCONNECTED WITH SECOND DATAPHASE SECOND TIME`
1296			`reported SUCCESSFULL!`
1297			`*****************************************************************************************`
1298
1299			`*****************************************************************************************`
1300			`At time 225945000`
1301			`Test BURST LENGTH 2 POSTED WRITE TRANSACTION PROCESSING ON PCI WITH NORMAL COMPLETION`
1302			`reported SUCCESSFULL!`
1303			`*****************************************************************************************`
1304
1305			`*****************************************************************************************`
1306			`At time 226515000`
1307			`Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON FIRST DATAPHASE FIRST TIME`
1308			`reported SUCCESSFULL!`
1309			`*****************************************************************************************`
1310
1311			`*****************************************************************************************`
1312			`At time 226905000`
1313			`Test BURST LENGTH 3 POSTED WRITE TRANSACTION DISCONNECT ON SECOND DATAPHASE SECOND TIME`
1314			`reported SUCCESSFULL!`
1315			`*****************************************************************************************`
1316
1317			`*****************************************************************************************`
1318			`At time 227625000`
1319			`Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON SECOND FIRST TIME`
1320			`reported SUCCESSFULL!`
1321			`*****************************************************************************************`
1322
1323			`*****************************************************************************************`
1324			`At time 227865000`
1325			`Test BURST LENGTH 3 POSTED WRITE DISCONNECTED ON FIRST SECOND TIME`
1326			`reported SUCCESSFULL!`
1327			`*****************************************************************************************`
1328
1329			`*****************************************************************************************`
1330			`At time 228705000`
1331			`Test BURST LENGTH 3 POSTED WRITE TRANSACTION WITH NORMAL COMPLETION`
1332			`reported SUCCESSFULL!`
1333			`*****************************************************************************************`
1334
1335			`*****************************************************************************************`
1336			`At time 231615000`
1337			`Test FULL WRITE FIFO BURST RETRIED FIRST TIME`
1338			`reported SUCCESSFULL!`
1339			`*****************************************************************************************`
1340
1341			`*****************************************************************************************`
1342			`At time 231885000`
1343			`Test FULL WRITE FIFO BURST DISCONNECT WITH FIRST SECOND TIME`
1344			`reported SUCCESSFULL!`
1345			`*****************************************************************************************`
1346
1347			`*****************************************************************************************`
1348			`At time 232305000`
1349			`Test FULL WRITE FIFO BURST DISCONNECT AFTER FIRST THIRD TIME`
1350			`reported SUCCESSFULL!`
1351			`*****************************************************************************************`
1352
1353			`*****************************************************************************************`
1354			`At time 232725000`
1355			`Test FULL WRITE FIFO BURST DISCONNECT WITH SECOND FOURTH TIME`
1356			`reported SUCCESSFULL!`
1357			`*****************************************************************************************`
1358
1359			`*****************************************************************************************`
1360			`At time 241515000`
1361			`Test REMAINDER OF FULL WRITE FIFO BURST NORMAL COMPLETION FIFTH TIME`
1362			`reported SUCCESSFULL!`
1363			`*****************************************************************************************`
1364
1365			`*****************************************************************************************`
1366			`At time 260520000`
1367			`Test READ DATA BURSTED TO TARGET BACK AND CHECK VALUES`
1368			`reported SUCCESSFULL!`
1369			`*****************************************************************************************`
1370
1371			`*****************************************************************************************`
1372			`At time 261420000`
1373			`Test SINGLE MEMORY READ DISCONNECTED WITH FIRST SECOND TIME`
1374			`reported SUCCESSFULL!`
1375			`*****************************************************************************************`
1376
1377			`*****************************************************************************************`
1378			`At time 266020000`
1379			`Test BURST READ WITH DISCONNECT ON FIRST`
1380			`reported SUCCESSFULL!`
1381			`*****************************************************************************************`
1382
1383			`*****************************************************************************************`
1384			`At time 266820000`
1385			`Test BURST READ WITH DISCONNECT AFTER FIRST`
1386			`reported SUCCESSFULL!`
1387			`*****************************************************************************************`
1388
1389			`*****************************************************************************************`
1390			`At time 267520000`
1391			`Test BURST READ WITH DISCONNECT ON SECOND - TAKE OUT ONLY ONE`
1392			`reported SUCCESSFULL!`
1393			`*****************************************************************************************`
1394
1395			`*****************************************************************************************`
1396			`At time 268660000`
1397			`Test BURST READ WITH NORMAL TERMINATION`
1398			`reported SUCCESSFULL!`
1399			`*****************************************************************************************`
1400
1401			`*****************************************************************************************`
1402			`At time 270060000`
1403			`Test NORMAL BURST READ WITH NORMAL COMPLETION, MEMORY READ LINE DISABLED, PREFETCH ENABLED, BURST SIZE 4`
1404			`reported SUCCESSFULL!`
1405			`*****************************************************************************************`
1406
1407			`*****************************************************************************************`
1408			`At time 270660000`
1409			`Test SINGLE READ WITH FUNNY BYTE ENABLE COMBINATION`
1410			`reported SUCCESSFULL!`
1411			`*****************************************************************************************`
1412
1413			`*****************************************************************************************`
1414			`At time 277840000`
1415			`Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALID`
1416			`reported SUCCESSFULL!`
1417			`*****************************************************************************************`
1418
1419			`*****************************************************************************************`
1420			`At time 278620000`
1421			`Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS INVALID`
1422			`reported SUCCESSFULL!`
1423			`*****************************************************************************************`
1424
1425			`*****************************************************************************************`
1426			`At time 279400000`
1427			`Test WB BURST READ WHEN CACHE LINE SIZE VALUE IS ZERO`
1428			`reported SUCCESSFULL!`
1429			`*****************************************************************************************`
1430
1431			`*****************************************************************************************`
1432			`At time 280395000`
1433			`Test LATENCY TIMER OPERATION ON PCI MASTER WRITE`
1434			`reported SUCCESSFULL!`
1435			`*****************************************************************************************`
1436
1437			`*****************************************************************************************`
1438			`At time 284080000`
1439			`Test BURST WRITE DATA DISCONNECTED BY LATENCY TIMEOUT`
1440			`reported SUCCESSFULL!`
1441			`*****************************************************************************************`
1442
1443			`*****************************************************************************************`
1444			`At time 284920000`
1445			`Test LATENCY TIMER OPERATION DURING MASTER READ`
1446			`reported SUCCESSFULL!`
1447			`*****************************************************************************************`
1448
1449			`*****************************************************************************************`
1450			`At time 285820000`
1451			`Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH MASTER ABORT`
1452			`reported SUCCESSFULL!`
1453			`*****************************************************************************************`
1454
1455			`*****************************************************************************************`
1456			`At time 286600000`
1457			`Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION`
1458			`reported SUCCESSFULL!`
1459			`*****************************************************************************************`
1460
1461			`*****************************************************************************************`
1462			`At time 287200000`
1463			`Test INTERRUPT ACKNOWLEDGE CYCLE GENERATION WITH NORMAL COMPLETION AND FUNNY BYTE ENABLES`
1464			`reported SUCCESSFULL!`
1465			`*****************************************************************************************`
1466
1467			`*****************************************************************************************`
1468			`At time 318495000`
1469			`Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCI`
1470			`reported SUCCESSFULL!`
1471			`*****************************************************************************************`
1472
1473			`*****************************************************************************************`
1474			`At time 319040000`
1475			`Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCI`
1476			`reported SUCCESSFULL!`
1477			`*****************************************************************************************`
1478
1479			`*****************************************************************************************`
1480			`At time 319515000`
1481			`Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCI`
1482			`reported SUCCESSFULL!`
1483			`*****************************************************************************************`
1484
1485			`*****************************************************************************************`
1486			`At time 320040000`
1487			`Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCI`
1488			`reported SUCCESSFULL!`
1489			`*****************************************************************************************`
1490
1491			`*****************************************************************************************`
1492			`At time 321465000`
1493			`Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCI`
1494			`reported SUCCESSFULL!`
1495			`*****************************************************************************************`
1496
1497			`*****************************************************************************************`
1498			`At time 322095000`
1499			`Test CAB MEMORY READ THROUGH WB SLAVE FROM PCI`
1500			`reported SUCCESSFULL!`
1501			`*****************************************************************************************`
1502
1503			`*****************************************************************************************`
1504			`At time 322725000`
1505			`Test CAB MEMORY READ THROUGH WB SLAVE FROM PCI`
1506			`reported SUCCESSFULL!`
1507			`*****************************************************************************************`
1508
1509			`*****************************************************************************************`
1510			`At time 323415000`
1511			`Test CAB MEMORY READ THROUGH WB SLAVE FROM PCI`
1512			`reported SUCCESSFULL!`
1513			`*****************************************************************************************`
1514
1515			`*****************************************************************************************`
1516			`At time 324105000`
1517			`Test CAB MEMORY READ THROUGH WB SLAVE FROM PCI`
1518			`reported SUCCESSFULL!`
1519			`*****************************************************************************************`
1520
1521			`*****************************************************************************************`
1522			`At time 325680000`
1523			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
1524			`reported SUCCESSFULL!`
1525			`*****************************************************************************************`
1526
1527			`*****************************************************************************************`
1528			`At time 325680000`
1529			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
1530			`reported SUCCESSFULL!`
1531			`*****************************************************************************************`
1532
1533			`*****************************************************************************************`
1534			`At time 325680000`
1535			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
1536			`reported SUCCESSFULL!`
1537			`*****************************************************************************************`
1538
1539			`*****************************************************************************************`
1540			`At time 325680000`
1541			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
1542			`reported SUCCESSFULL!`
1543			`*****************************************************************************************`
1544
1545			`*****************************************************************************************`
1546			`At time 326380000`
1547			`Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
1548			`reported SUCCESSFULL!`
1549			`*****************************************************************************************`
1550
1551			`*****************************************************************************************`
1552			`At time 327780000`
1553			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
1554			`reported SUCCESSFULL!`
1555			`*****************************************************************************************`
1556
1557			`*****************************************************************************************`
1558			`At time 327780000`
1559			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
1560			`reported SUCCESSFULL!`
1561			`*****************************************************************************************`
1562
1563			`*****************************************************************************************`
1564			`At time 327780000`
1565			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
1566			`reported SUCCESSFULL!`
1567			`*****************************************************************************************`
1568
1569			`*****************************************************************************************`
1570			`At time 327780000`
1571			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
1572			`reported SUCCESSFULL!`
1573			`*****************************************************************************************`
1574
1575			`*****************************************************************************************`
1576			`At time 328480000`
1577			`Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
1578			`reported SUCCESSFULL!`
1579			`*****************************************************************************************`
1580
1581			`*****************************************************************************************`
1582			`At time 331480000`
1583			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
1584			`reported SUCCESSFULL!`
1585			`*****************************************************************************************`
1586
1587			`*****************************************************************************************`
1588			`At time 331480000`
1589			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
1590			`reported SUCCESSFULL!`
1591			`*****************************************************************************************`
1592
1593			`*****************************************************************************************`
1594			`At time 331480000`
1595			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
1596			`reported SUCCESSFULL!`
1597			`*****************************************************************************************`
1598
1599			`*****************************************************************************************`
1600			`At time 331480000`
1601			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
1602			`reported SUCCESSFULL!`
1603			`*****************************************************************************************`
1604
1605			`*****************************************************************************************`
1606			`At time 332180000`
1607			`Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
1608			`reported SUCCESSFULL!`
1609			`*****************************************************************************************`
1610
1611			`*****************************************************************************************`
1612			`At time 332805000`
1613			`Test I/O WRITE TRANSACTION FROM WB TO PCI TEST`
1614			`reported SUCCESSFULL!`
1615			`*****************************************************************************************`
1616
1617			`*****************************************************************************************`
1618			`At time 333400000`
1619			`Test I/O READ TRANSACTION FROM WB TO PCI TEST`
1620			`reported SUCCESSFULL!`
1621			`*****************************************************************************************`
1622
1623			`*****************************************************************************************`
1624			`At time 334000000`
1625			`Test I/O READ TRANSACTION FROM WB TO PCI TEST`
1626			`reported SUCCESSFULL!`
1627			`*****************************************************************************************`
1628
1629			`*****************************************************************************************`
1630			`At time 334995000`
1631			`Test CHECK MAXIMUM IMAGE SIZE`
1632			`reported SUCCESSFULL!`
1633			`*****************************************************************************************`
1634
1635			`*****************************************************************************************`
1636			`At time 335580000`
1637			`Test CHECK MAXIMUM IMAGE SIZE`
1638			`reported SUCCESSFULL!`
1639			`*****************************************************************************************`
1640
1641			`*****************************************************************************************`
1642			`At time 337305000`
1643			`Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCI`
1644			`reported SUCCESSFULL!`
1645			`*****************************************************************************************`
1646
1647			`*****************************************************************************************`
1648			`At time 337840000`
1649			`Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCI`
1650			`reported SUCCESSFULL!`
1651			`*****************************************************************************************`
1652
1653			`*****************************************************************************************`
1654			`At time 338295000`
1655			`Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCI`
1656			`reported SUCCESSFULL!`
1657			`*****************************************************************************************`
1658
1659			`*****************************************************************************************`
1660			`At time 338840000`
1661			`Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCI`
1662			`reported SUCCESSFULL!`
1663			`*****************************************************************************************`
1664
1665			`*****************************************************************************************`
1666			`At time 340275000`
1667			`Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCI`
1668			`reported SUCCESSFULL!`
1669			`*****************************************************************************************`
1670
1671			`*****************************************************************************************`
1672			`At time 340875000`
1673			`Test CAB MEMORY READ THROUGH WB SLAVE FROM PCI`
1674			`reported SUCCESSFULL!`
1675			`*****************************************************************************************`
1676
1677			`*****************************************************************************************`
1678			`At time 341535000`
1679			`Test CAB MEMORY READ THROUGH WB SLAVE FROM PCI`
1680			`reported SUCCESSFULL!`
1681			`*****************************************************************************************`
1682
1683			`*****************************************************************************************`
1684			`At time 342225000`
1685			`Test CAB MEMORY READ THROUGH WB SLAVE FROM PCI`
1686			`reported SUCCESSFULL!`
1687			`*****************************************************************************************`
1688
1689			`*****************************************************************************************`
1690			`At time 342885000`
1691			`Test CAB MEMORY READ THROUGH WB SLAVE FROM PCI`
1692			`reported SUCCESSFULL!`
1693			`*****************************************************************************************`
1694
1695			`*****************************************************************************************`
1696			`At time 344480000`
1697			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
1698			`reported SUCCESSFULL!`
1699			`*****************************************************************************************`
1700
1701			`*****************************************************************************************`
1702			`At time 344480000`
1703			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
1704			`reported SUCCESSFULL!`
1705			`*****************************************************************************************`
1706
1707			`*****************************************************************************************`
1708			`At time 344480000`
1709			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
1710			`reported SUCCESSFULL!`
1711			`*****************************************************************************************`
1712
1713			`*****************************************************************************************`
1714			`At time 344480000`
1715			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
1716			`reported SUCCESSFULL!`
1717			`*****************************************************************************************`
1718
1719			`*****************************************************************************************`
1720			`At time 345180000`
1721			`Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
1722			`reported SUCCESSFULL!`
1723			`*****************************************************************************************`
1724
1725			`*****************************************************************************************`
1726			`At time 346580000`
1727			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
1728			`reported SUCCESSFULL!`
1729			`*****************************************************************************************`
1730
1731			`*****************************************************************************************`
1732			`At time 346580000`
1733			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
1734			`reported SUCCESSFULL!`
1735			`*****************************************************************************************`
1736
1737			`*****************************************************************************************`
1738			`At time 346580000`
1739			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
1740			`reported SUCCESSFULL!`
1741			`*****************************************************************************************`
1742
1743			`*****************************************************************************************`
1744			`At time 346580000`
1745			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
1746			`reported SUCCESSFULL!`
1747			`*****************************************************************************************`
1748
1749			`*****************************************************************************************`
1750			`At time 347280000`
1751			`Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
1752			`reported SUCCESSFULL!`
1753			`*****************************************************************************************`
1754
1755			`*****************************************************************************************`
1756			`At time 350280000`
1757			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
1758			`reported SUCCESSFULL!`
1759			`*****************************************************************************************`
1760
1761			`*****************************************************************************************`
1762			`At time 350280000`
1763			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
1764			`reported SUCCESSFULL!`
1765			`*****************************************************************************************`
1766
1767			`*****************************************************************************************`
1768			`At time 350280000`
1769			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
1770			`reported SUCCESSFULL!`
1771			`*****************************************************************************************`
1772
1773			`*****************************************************************************************`
1774			`At time 350280000`
1775			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
1776			`reported SUCCESSFULL!`
1777			`*****************************************************************************************`
1778
1779			`*****************************************************************************************`
1780			`At time 350980000`
1781			`Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
1782			`reported SUCCESSFULL!`
1783			`*****************************************************************************************`
1784
1785			`*****************************************************************************************`
1786			`At time 351615000`
1787			`Test I/O WRITE TRANSACTION FROM WB TO PCI TEST`
1788			`reported SUCCESSFULL!`
1789			`*****************************************************************************************`
1790
1791			`*****************************************************************************************`
1792			`At time 352200000`
1793			`Test I/O READ TRANSACTION FROM WB TO PCI TEST`
1794			`reported SUCCESSFULL!`
1795			`*****************************************************************************************`
1796
1797			`*****************************************************************************************`
1798			`At time 352800000`
1799			`Test I/O READ TRANSACTION FROM WB TO PCI TEST`
1800			`reported SUCCESSFULL!`
1801			`*****************************************************************************************`
1802
1803			`*****************************************************************************************`
1804			`At time 353805000`
1805			`Test CHECK MAXIMUM IMAGE SIZE`
1806			`reported SUCCESSFULL!`
1807			`*****************************************************************************************`
1808
1809			`*****************************************************************************************`
1810			`At time 354400000`
1811			`Test CHECK MAXIMUM IMAGE SIZE`
1812			`reported SUCCESSFULL!`
1813			`*****************************************************************************************`
1814
1815			`*****************************************************************************************`
1816			`At time 356115000`
1817			`Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCI`
1818			`reported SUCCESSFULL!`
1819			`*****************************************************************************************`
1820
1821			`*****************************************************************************************`
1822			`At time 356660000`
1823			`Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCI`
1824			`reported SUCCESSFULL!`
1825			`*****************************************************************************************`
1826
1827			`*****************************************************************************************`
1828			`At time 357135000`
1829			`Test NORMAL SINGLE MEMORY WRITE THROUGH WB IMAGE TO PCI`
1830			`reported SUCCESSFULL!`
1831			`*****************************************************************************************`
1832
1833			`*****************************************************************************************`
1834			`At time 357660000`
1835			`Test NORMAL SINGLE MEMORY READ THROUGH WB IMAGE FROM PCI`
1836			`reported SUCCESSFULL!`
1837			`*****************************************************************************************`
1838
1839			`*****************************************************************************************`
1840			`At time 359085000`
1841			`Test CAB MEMORY WRITE THROUGH WB SLAVE TO PCI`
1842			`reported SUCCESSFULL!`
1843			`*****************************************************************************************`
1844
1845			`*****************************************************************************************`
1846			`At time 359715000`
1847			`Test CAB MEMORY READ THROUGH WB SLAVE FROM PCI`
1848			`reported SUCCESSFULL!`
1849			`*****************************************************************************************`
1850
1851			`*****************************************************************************************`
1852			`At time 360345000`
1853			`Test CAB MEMORY READ THROUGH WB SLAVE FROM PCI`
1854			`reported SUCCESSFULL!`
1855			`*****************************************************************************************`
1856
1857			`*****************************************************************************************`
1858			`At time 361035000`
1859			`Test CAB MEMORY READ THROUGH WB SLAVE FROM PCI`
1860			`reported SUCCESSFULL!`
1861			`*****************************************************************************************`
1862
1863			`*****************************************************************************************`
1864			`At time 361725000`
1865			`Test CAB MEMORY READ THROUGH WB SLAVE FROM PCI`
1866			`reported SUCCESSFULL!`
1867			`*****************************************************************************************`
1868
1869			`*****************************************************************************************`
1870			`At time 363300000`
1871			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
1872			`reported SUCCESSFULL!`
1873			`*****************************************************************************************`
1874
1875			`*****************************************************************************************`
1876			`At time 363300000`
1877			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
1878			`reported SUCCESSFULL!`
1879			`*****************************************************************************************`
1880
1881			`*****************************************************************************************`
1882			`At time 363300000`
1883			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
1884			`reported SUCCESSFULL!`
1885			`*****************************************************************************************`
1886
1887			`*****************************************************************************************`
1888			`At time 363300000`
1889			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
1890			`reported SUCCESSFULL!`
1891			`*****************************************************************************************`
1892
1893			`*****************************************************************************************`
1894			`At time 364000000`
1895			`Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
1896			`reported SUCCESSFULL!`
1897			`*****************************************************************************************`
1898
1899			`*****************************************************************************************`
1900			`At time 365400000`
1901			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
1902			`reported SUCCESSFULL!`
1903			`*****************************************************************************************`
1904
1905			`*****************************************************************************************`
1906			`At time 365400000`
1907			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
1908			`reported SUCCESSFULL!`
1909			`*****************************************************************************************`
1910
1911			`*****************************************************************************************`
1912			`At time 365400000`
1913			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
1914			`reported SUCCESSFULL!`
1915			`*****************************************************************************************`
1916
1917			`*****************************************************************************************`
1918			`At time 365400000`
1919			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
1920			`reported SUCCESSFULL!`
1921			`*****************************************************************************************`
1922
1923			`*****************************************************************************************`
1924			`At time 366100000`
1925			`Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
1926			`reported SUCCESSFULL!`
1927			`*****************************************************************************************`
1928
1929			`*****************************************************************************************`
1930			`At time 369100000`
1931			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
1932			`reported SUCCESSFULL!`
1933			`*****************************************************************************************`
1934
1935			`*****************************************************************************************`
1936			`At time 369100000`
1937			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
1938			`reported SUCCESSFULL!`
1939			`*****************************************************************************************`
1940
1941			`*****************************************************************************************`
1942			`At time 369100000`
1943			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
1944			`reported SUCCESSFULL!`
1945			`*****************************************************************************************`
1946
1947			`*****************************************************************************************`
1948			`At time 369100000`
1949			`Test CAB MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
1950			`reported SUCCESSFULL!`
1951			`*****************************************************************************************`
1952
1953			`*****************************************************************************************`
1954			`At time 369800000`
1955			`Test SINGLE MEMORY READ THROUGH WB IMAGE WITH READ BURSTING ENABLED`
1956			`reported SUCCESSFULL!`
1957			`*****************************************************************************************`
1958
1959			`*****************************************************************************************`
1960			`At time 370425000`
1961			`Test I/O WRITE TRANSACTION FROM WB TO PCI TEST`
1962			`reported SUCCESSFULL!`
1963			`*****************************************************************************************`
1964
1965			`*****************************************************************************************`
1966			`At time 371020000`
1967			`Test I/O READ TRANSACTION FROM WB TO PCI TEST`
1968			`reported SUCCESSFULL!`
1969			`*****************************************************************************************`
1970
1971			`*****************************************************************************************`
1972			`At time 371620000`
1973			`Test I/O READ TRANSACTION FROM WB TO PCI TEST`
1974			`reported SUCCESSFULL!`
1975			`*****************************************************************************************`
1976
1977			`*****************************************************************************************`
1978			`At time 372615000`
1979			`Test CHECK MAXIMUM IMAGE SIZE`
1980			`reported SUCCESSFULL!`
1981			`*****************************************************************************************`
1982
1983			`*****************************************************************************************`
1984			`At time 373200000`
1985			`Test CHECK MAXIMUM IMAGE SIZE`
1986			`reported SUCCESSFULL!`
1987			`*****************************************************************************************`
1988
1989			`*****************************************************************************************`
1990			`At time 374580000`
1991			`Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVE`
1992			`reported SUCCESSFULL!`
1993			`*****************************************************************************************`
1994
1995			`*****************************************************************************************`
1996			`At time 374680000`
1997			`Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVE`
1998			`reported SUCCESSFULL!`
1999			`*****************************************************************************************`
2000
2001			`*****************************************************************************************`
2002			`At time 374880000`
2003			`Test ERRONEOUS CAB MEMORY READ TO WB SLAVE`
2004			`reported SUCCESSFULL!`
2005			`*****************************************************************************************`
2006
2007			`*****************************************************************************************`
2008			`At time 375760000`
2009			`Test ERRONEOUS I/O WRITE TO WB SLAVE`
2010			`reported SUCCESSFULL!`
2011			`*****************************************************************************************`
2012
2013			`*****************************************************************************************`
2014			`At time 375860000`
2015			`Test ERRONEOUS I/O READ TO WB SLAVE`
2016			`reported SUCCESSFULL!`
2017			`*****************************************************************************************`
2018
2019			`*****************************************************************************************`
2020			`At time 375960000`
2021			`Test CAB I/O WRITE TO WB SLAVE`
2022			`reported SUCCESSFULL!`
2023			`*****************************************************************************************`
2024
2025			`*****************************************************************************************`
2026			`At time 376060000`
2027			`Test CAB I/O READ TO WB SLAVE`
2028			`reported SUCCESSFULL!`
2029			`*****************************************************************************************`
2030
2031			`*****************************************************************************************`
2032			`At time 376420000`
2033			`Test ERRONEOUS WB CONFIGURATION WRITE ACCESS`
2034			`reported SUCCESSFULL!`
2035			`*****************************************************************************************`
2036
2037			`*****************************************************************************************`
2038			`At time 376540000`
2039			`Test ERRONEOUS WB CONFIGURATION READ ACCESS`
2040			`reported SUCCESSFULL!`
2041			`*****************************************************************************************`
2042
2043			`*****************************************************************************************`
2044			`At time 376660000`
2045			`Test WB CAB CONFIGURATION WRITE ACCESS`
2046			`reported SUCCESSFULL!`
2047			`*****************************************************************************************`
2048
2049			`*****************************************************************************************`
2050			`At time 376780000`
2051			`Test WB CAB CONFIGURATION READ ACCESS`
2052			`reported SUCCESSFULL!`
2053			`*****************************************************************************************`
2054
2055			`*****************************************************************************************`
2056			`At time 379335000`
2057			`Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITES`
2058			`reported SUCCESSFULL!`
2059			`*****************************************************************************************`
2060
2061			`*****************************************************************************************`
2062			`At time 379680000`
2063			`Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERROR`
2064			`reported SUCCESSFULL!`
2065			`*****************************************************************************************`
2066
2067			`*****************************************************************************************`
2068			`At time 379760000`
2069			`Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERROR`
2070			`reported SUCCESSFULL!`
2071			`*****************************************************************************************`
2072
2073			`*****************************************************************************************`
2074			`At time 380040000`
2075			`Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORT`
2076			`reported SUCCESSFULL!`
2077			`*****************************************************************************************`
2078
2079			`*****************************************************************************************`
2080			`At time 381165000`
2081			`Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITE`
2082			`reported SUCCESSFULL!`
2083			`*****************************************************************************************`
2084
2085			`*****************************************************************************************`
2086			`At time 382300000`
2087			`Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERROR`
2088			`reported SUCCESSFULL!`
2089			`*****************************************************************************************`
2090
2091			`*****************************************************************************************`
2092			`At time 383020000`
2093			`Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERROR`
2094			`reported SUCCESSFULL!`
2095			`*****************************************************************************************`
2096
2097			`*****************************************************************************************`
2098			`At time 383280000`
2099			`Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEM`
2100			`reported SUCCESSFULL!`
2101			`*****************************************************************************************`
2102
2103			`*****************************************************************************************`
2104			`At time 387500000`
2105			`Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READS`
2106			`reported SUCCESSFULL!`
2107			`*****************************************************************************************`
2108
2109			`*****************************************************************************************`
2110			`At time 387780000`
2111			`Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READ`
2112			`reported SUCCESSFULL!`
2113			`*****************************************************************************************`
2114
2115			`*****************************************************************************************`
2116			`At time 389320000`
2117			`Test CHECK NORMAL READ AFTER ERROR TERMINATED READ`
2118			`reported SUCCESSFULL!`
2119			`*****************************************************************************************`
2120
2121			`*****************************************************************************************`
2122			`At time 389580000`
2123			`Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READ`
2124			`reported SUCCESSFULL!`
2125			`*****************************************************************************************`
2126
2127			`*****************************************************************************************`
2128			`At time 391200000`
2129			`Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCI`
2130			`reported SUCCESSFULL!`
2131			`*****************************************************************************************`
2132
2133			`*****************************************************************************************`
2134			`At time 391480000`
2135			`Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORT`
2136			`reported SUCCESSFULL!`
2137			`*****************************************************************************************`
2138
2139			`*****************************************************************************************`
2140			`At time 393315000`
2141			`Test TARGET ABORT ERROR ON SINGLE WRITE`
2142			`reported SUCCESSFULL!`
2143			`*****************************************************************************************`
2144
2145			`*****************************************************************************************`
2146			`At time 393675000`
2147			`Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORT`
2148			`reported SUCCESSFULL!`
2149			`*****************************************************************************************`
2150
2151			`*****************************************************************************************`
2152			`At time 394140000`
2153			`Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORT`
2154			`reported SUCCESSFULL!`
2155			`*****************************************************************************************`
2156
2157			`*****************************************************************************************`
2158			`At time 394420000`
2159			`Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORT`
2160			`reported SUCCESSFULL!`
2161			`*****************************************************************************************`
2162
2163			`*****************************************************************************************`
2164			`At time 394680000`
2165			`Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORT`
2166			`reported SUCCESSFULL!`
2167			`*****************************************************************************************`
2168
2169			`*****************************************************************************************`
2170			`At time 394960000`
2171			`Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORT`
2172			`reported SUCCESSFULL!`
2173			`*****************************************************************************************`
2174
2175			`*****************************************************************************************`
2176			`At time 395925000`
2177			`Test TARGET ABORT ERROR ON CAB MEMORY WRITE`
2178			`reported SUCCESSFULL!`
2179			`*****************************************************************************************`
2180
2181			`*****************************************************************************************`
2182			`At time 396220000`
2183			`Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORT`
2184			`reported SUCCESSFULL!`
2185			`*****************************************************************************************`
2186
2187			`*****************************************************************************************`
2188			`At time 396760000`
2189			`Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORT`
2190			`reported SUCCESSFULL!`
2191			`*****************************************************************************************`
2192
2193			`*****************************************************************************************`
2194			`At time 397020000`
2195			`Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORT`
2196			`reported SUCCESSFULL!`
2197			`*****************************************************************************************`
2198
2199			`*****************************************************************************************`
2200			`At time 399195000`
2201			`Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITE`
2202			`reported SUCCESSFULL!`
2203			`*****************************************************************************************`
2204
2205			`*****************************************************************************************`
2206			`At time 399480000`
2207			`Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORT`
2208			`reported SUCCESSFULL!`
2209			`*****************************************************************************************`
2210
2211			`*****************************************************************************************`
2212			`At time 400020000`
2213			`Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORT`
2214			`reported SUCCESSFULL!`
2215			`*****************************************************************************************`
2216
2217			`*****************************************************************************************`
2218			`At time 400100000`
2219			`Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGER`
2220			`reported SUCCESSFULL!`
2221			`*****************************************************************************************`
2222
2223			`*****************************************************************************************`
2224			`At time 400860000`
2225			`Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITE`
2226			`reported SUCCESSFULL!`
2227			`*****************************************************************************************`
2228
2229			`*****************************************************************************************`
2230			`At time 401640000`
2231			`Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITS`
2232			`reported SUCCESSFULL!`
2233			`*****************************************************************************************`
2234
2235			`*****************************************************************************************`
2236			`At time 402520000`
2237			`Test TARGET ABORT DURING SINGLE MEMORY READ`
2238			`reported SUCCESSFULL!`
2239			`*****************************************************************************************`
2240
2241			`*****************************************************************************************`
2242			`At time 402780000`
2243			`Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORT`
2244			`reported SUCCESSFULL!`
2245			`*****************************************************************************************`
2246
2247			`*****************************************************************************************`
2248			`At time 403060000`
2249			`Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORT`
2250			`reported SUCCESSFULL!`
2251			`*****************************************************************************************`
2252
2253			`*****************************************************************************************`
2254			`At time 403540000`
2255			`Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORT`
2256			`reported SUCCESSFULL!`
2257			`*****************************************************************************************`
2258
2259			`*****************************************************************************************`
2260			`At time 404380000`
2261			`Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READ`
2262			`reported SUCCESSFULL!`
2263			`*****************************************************************************************`
2264
2265			`*****************************************************************************************`
2266			`At time 404640000`
2267			`Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORT`
2268			`reported SUCCESSFULL!`
2269			`*****************************************************************************************`
2270
2271			`*****************************************************************************************`
2272			`At time 406000000`
2273			`Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READ`
2274			`reported SUCCESSFULL!`
2275			`*****************************************************************************************`
2276
2277			`*****************************************************************************************`
2278			`At time 407320000`
2279			`Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READ`
2280			`reported SUCCESSFULL!`
2281			`*****************************************************************************************`
2282
2283			`*****************************************************************************************`
2284			`At time 407580000`
2285			`Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORT`
2286			`reported SUCCESSFULL!`
2287			`*****************************************************************************************`
2288
2289			`*****************************************************************************************`
2290			`At time 408940000`
2291			`Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READ`
2292			`reported SUCCESSFULL!`
2293			`*****************************************************************************************`
2294
2295			`*****************************************************************************************`
2296			`At time 409575000`
2297			`Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITE`
2298			`reported SUCCESSFULL!`
2299			`*****************************************************************************************`
2300
2301			`*****************************************************************************************`
2302			`At time 409860000`
2303			`Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITE`
2304			`reported SUCCESSFULL!`
2305			`*****************************************************************************************`
2306
2307			`*****************************************************************************************`
2308			`At time 410400000`
2309			`Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITE`
2310			`reported SUCCESSFULL!`
2311			`*****************************************************************************************`
2312
2313			`*****************************************************************************************`
2314			`At time 410680000`
2315			`Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITE`
2316			`reported SUCCESSFULL!`
2317			`*****************************************************************************************`
2318
2319			`*****************************************************************************************`
2320			`At time 411340000`
2321			`Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITE`
2322			`reported SUCCESSFULL!`
2323			`*****************************************************************************************`
2324
2325			`*****************************************************************************************`
2326			`At time 414825000`
2327			`Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE`
2328			`reported SUCCESSFULL!`
2329			`*****************************************************************************************`
2330
2331			`*****************************************************************************************`
2332			`At time 415180000`
2333			`Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE`
2334			`reported SUCCESSFULL!`
2335			`*****************************************************************************************`
2336
2337			`*****************************************************************************************`
2338			`At time 415905000`
2339			`Test RESPONSE TO TARGET ASSERTING PERR DURING MASTER WRITE WITH PARITY ERROR RESPONSE ENABLED`
2340			`reported SUCCESSFULL!`
2341			`*****************************************************************************************`
2342
2343			`*****************************************************************************************`
2344			`At time 416260000`
2345			`Test PCI DEVICE STATUS REGISTER VALUE AFTER PARITY ERROR DURING MASTER WRITE - PAR. ERR. RESPONSE ENABLED`
2346			`reported SUCCESSFULL!`
2347			`*****************************************************************************************`
2348
2349			`*****************************************************************************************`
2350			`At time 416895000`
2351			`Test MASTER WRITE WITH NO PARITY ERRORS`
2352			`reported SUCCESSFULL!`
2353			`*****************************************************************************************`
2354
2355			`*****************************************************************************************`
2356			`At time 417340000`
2357			`Test PCI DEVICE STATUS REGISTER VALUE AFTER NORMAL MEMORY WRITE`
2358			`reported SUCCESSFULL!`
2359			`*****************************************************************************************`
2360
2361			`*****************************************************************************************`
2362			`At time 418300000`
2363			`Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READS`
2364			`reported SUCCESSFULL!`
2365			`*****************************************************************************************`
2366
2367			`*****************************************************************************************`
2368			`At time 418460000`
2369			`Test INTERRUPT REQUEST ASSERTION AFTER PARITY ERROR`
2370			`reported SUCCESSFULL!`
2371			`*****************************************************************************************`
2372
2373			`.`
2374			`.`
2375			`.`
2376
2377
2378			`*****************************************************************************************`
2379			`At time 1960240000`
2380			`Test CHECK MAXIMUM IMAGE SIZE`
2381			`reported SUCCESSFULL!`
2382			`*****************************************************************************************`
2383
2384			`*****************************************************************************************`
2385			`At time 1961700000`
2386			`Test SINGLE ERRONEOUS MEMORY WRITE TO WB SLAVE`
2387			`reported SUCCESSFULL!`
2388			`*****************************************************************************************`
2389
2390			`*****************************************************************************************`
2391			`At time 1961820000`
2392			`Test SINGLE ERRONEOUS MEMORY READ TO WB SLAVE`
2393			`reported SUCCESSFULL!`
2394			`*****************************************************************************************`
2395
2396			`*****************************************************************************************`
2397			`At time 1962020000`
2398			`Test ERRONEOUS CAB MEMORY READ TO WB SLAVE`
2399			`reported SUCCESSFULL!`
2400			`*****************************************************************************************`
2401
2402			`*****************************************************************************************`
2403			`At time 1963060000`
2404			`Test ERRONEOUS I/O WRITE TO WB SLAVE`
2405			`reported SUCCESSFULL!`
2406			`*****************************************************************************************`
2407
2408			`*****************************************************************************************`
2409			`At time 1963180000`
2410			`Test ERRONEOUS I/O READ TO WB SLAVE`
2411			`reported SUCCESSFULL!`
2412			`*****************************************************************************************`
2413
2414			`*****************************************************************************************`
2415			`At time 1963280000`
2416			`Test CAB I/O WRITE TO WB SLAVE`
2417			`reported SUCCESSFULL!`
2418			`*****************************************************************************************`
2419
2420			`*****************************************************************************************`
2421			`At time 1963380000`
2422			`Test CAB I/O READ TO WB SLAVE`
2423			`reported SUCCESSFULL!`
2424			`*****************************************************************************************`
2425
2426			`*****************************************************************************************`
2427			`At time 1963800000`
2428			`Test ERRONEOUS WB CONFIGURATION WRITE ACCESS`
2429			`reported SUCCESSFULL!`
2430			`*****************************************************************************************`
2431
2432			`*****************************************************************************************`
2433			`At time 1963940000`
2434			`Test ERRONEOUS WB CONFIGURATION READ ACCESS`
2435			`reported SUCCESSFULL!`
2436			`*****************************************************************************************`
2437
2438			`*****************************************************************************************`
2439			`At time 1964060000`
2440			`Test WB CAB CONFIGURATION WRITE ACCESS`
2441			`reported SUCCESSFULL!`
2442			`*****************************************************************************************`
2443
2444			`*****************************************************************************************`
2445			`At time 1964180000`
2446			`Test WB CAB CONFIGURATION READ ACCESS`
2447			`reported SUCCESSFULL!`
2448			`*****************************************************************************************`
2449
2450			`*****************************************************************************************`
2451			`At time 1966935000`
2452			`Test MASTER ABORT ERROR HANDLING DURING WB TO PCI WRITES`
2453			`reported SUCCESSFULL!`
2454			`*****************************************************************************************`
2455
2456			`*****************************************************************************************`
2457			`At time 1967300000`
2458			`Test CHECKING ERROR REPORTING FUNCTIONS AFTER MASTER ABORT ERROR`
2459			`reported SUCCESSFULL!`
2460			`*****************************************************************************************`
2461
2462			`*****************************************************************************************`
2463			`At time 1967380000`
2464			`Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERROR`
2465			`reported SUCCESSFULL!`
2466			`*****************************************************************************************`
2467
2468			`*****************************************************************************************`
2469			`At time 1967660000`
2470			`Test CHECKING PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORT`
2471			`reported SUCCESSFULL!`
2472			`*****************************************************************************************`
2473
2474			`*****************************************************************************************`
2475			`At time 1968885000`
2476			`Test CHECKING MASTER ABORT ERROR HANDLING ON CAB MEMORY WRITE`
2477			`reported SUCCESSFULL!`
2478			`*****************************************************************************************`
2479
2480			`*****************************************************************************************`
2481			`At time 1970120000`
2482			`Test CHECKING ERROR REPORTING REGISTERS' VALUES AFTER MASTER ABORT ERROR`
2483			`reported SUCCESSFULL!`
2484			`*****************************************************************************************`
2485
2486			`*****************************************************************************************`
2487			`At time 1970900000`
2488			`Test CHECKING INTERRUPT REQUESTS AFTER MASTER ABORT ERROR`
2489			`reported SUCCESSFULL!`
2490			`*****************************************************************************************`
2491
2492			`*****************************************************************************************`
2493			`At time 1971180000`
2494			`Test CHECKING INTERRUPT REQUESTS AFTER CLEARING THEM`
2495			`reported SUCCESSFULL!`
2496			`*****************************************************************************************`
2497
2498			`*****************************************************************************************`
2499			`At time 1975460000`
2500			`Test MASTER ABORT ERROR HANDLING FOR WB TO PCI READS`
2501			`reported SUCCESSFULL!`
2502			`*****************************************************************************************`
2503
2504			`*****************************************************************************************`
2505			`At time 1975760000`
2506			`Test CHECKING ERROR STATUS AFTER MASTER ABORT ON READ`
2507			`reported SUCCESSFULL!`
2508			`*****************************************************************************************`
2509
2510			`*****************************************************************************************`
2511			`At time 1977320000`
2512			`Test CHECK NORMAL READ AFTER ERROR TERMINATED READ`
2513			`reported SUCCESSFULL!`
2514			`*****************************************************************************************`
2515
2516			`*****************************************************************************************`
2517			`At time 1977620000`
2518			`Test CHECK PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT ON DELAYED READ`
2519			`reported SUCCESSFULL!`
2520			`*****************************************************************************************`
2521
2522			`*****************************************************************************************`
2523			`At time 1979240000`
2524			`Test MASTER ABORT ERROR DURING CAB READ FROM WB TO PCI`
2525			`reported SUCCESSFULL!`
2526			`*****************************************************************************************`
2527
2528			`*****************************************************************************************`
2529			`At time 1979540000`
2530			`Test CHECK PCI DEVICE STATUS REGISTER AFTER READ TERMINATED WITH MASTER ABORT`
2531			`reported SUCCESSFULL!`
2532			`*****************************************************************************************`
2533
2534			`*****************************************************************************************`
2535			`At time 1981455000`
2536			`Test TARGET ABORT ERROR ON SINGLE WRITE`
2537			`reported SUCCESSFULL!`
2538			`*****************************************************************************************`
2539
2540			`*****************************************************************************************`
2541			`At time 1981845000`
2542			`Test NORMAL SINGLE MEMORY WRITE IMMEDIATELY AFTER ONE TERMINATED WITH TARGET ABORT`
2543			`reported SUCCESSFULL!`
2544			`*****************************************************************************************`
2545
2546			`*****************************************************************************************`
2547			`At time 1982360000`
2548			`Test NORMAL SINGLE MEMORY READ AFTER WRITE TERMINATED WITH TARGET ABORT`
2549			`reported SUCCESSFULL!`
2550			`*****************************************************************************************`
2551
2552			`*****************************************************************************************`
2553			`At time 1982660000`
2554			`Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORT`
2555			`reported SUCCESSFULL!`
2556			`*****************************************************************************************`
2557
2558			`*****************************************************************************************`
2559			`At time 1982960000`
2560			`Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORT`
2561			`reported SUCCESSFULL!`
2562			`*****************************************************************************************`
2563
2564			`*****************************************************************************************`
2565			`At time 1983260000`
2566			`Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORT`
2567			`reported SUCCESSFULL!`
2568			`*****************************************************************************************`
2569
2570			`*****************************************************************************************`
2571			`At time 1984335000`
2572			`Test TARGET ABORT ERROR ON CAB MEMORY WRITE`
2573			`reported SUCCESSFULL!`
2574			`*****************************************************************************************`
2575
2576			`*****************************************************************************************`
2577			`At time 1984640000`
2578			`Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORT`
2579			`reported SUCCESSFULL!`
2580			`*****************************************************************************************`
2581
2582			`*****************************************************************************************`
2583			`At time 1985240000`
2584			`Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORT`
2585			`reported SUCCESSFULL!`
2586			`*****************************************************************************************`
2587
2588			`*****************************************************************************************`
2589			`At time 1985540000`
2590			`Test PCI DEVICE STATUS VALUE CHECK AFTER WRITE TARGET ABORT`
2591			`reported SUCCESSFULL!`
2592			`*****************************************************************************************`
2593
2594			`*****************************************************************************************`
2595			`At time 1987755000`
2596			`Test TARGET ABORT TERMINATION ON SECOND DATA PHASE OF BURST WRITE`
2597			`reported SUCCESSFULL!`
2598			`*****************************************************************************************`
2599
2600			`*****************************************************************************************`
2601			`At time 1988060000`
2602			`Test WB ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER WRITE TARGET ABORT`
2603			`reported SUCCESSFULL!`
2604			`*****************************************************************************************`
2605
2606			`*****************************************************************************************`
2607			`At time 1988660000`
2608			`Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES CHECK AFTER WRITE TARGET ABORT`
2609			`reported SUCCESSFULL!`
2610			`*****************************************************************************************`
2611
2612			`*****************************************************************************************`
2613			`At time 1988740000`
2614			`Test INTERRUPT REQUEST ASSERTION AFTER ERROR REPORTING TRIGGER`
2615			`reported SUCCESSFULL!`
2616			`*****************************************************************************************`
2617
2618			`*****************************************************************************************`
2619			`At time 1989540000`
2620			`Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER TARGET ABORTED MEMORY WRITE`
2621			`reported SUCCESSFULL!`
2622			`*****************************************************************************************`
2623
2624			`*****************************************************************************************`
2625			`At time 1990340000`
2626			`Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER CLEARING STATUS BITS`
2627			`reported SUCCESSFULL!`
2628			`*****************************************************************************************`
2629
2630			`*****************************************************************************************`
2631			`At time 1991360000`
2632			`Test TARGET ABORT DURING SINGLE MEMORY READ`
2633			`reported SUCCESSFULL!`
2634			`*****************************************************************************************`
2635
2636			`*****************************************************************************************`
2637			`At time 1991660000`
2638			`Test WB ERROR STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORT`
2639			`reported SUCCESSFULL!`
2640			`*****************************************************************************************`
2641
2642			`*****************************************************************************************`
2643			`At time 1991960000`
2644			`Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORT`
2645			`reported SUCCESSFULL!`
2646			`*****************************************************************************************`
2647
2648			`*****************************************************************************************`
2649			`At time 1992480000`
2650			`Test INTERRUPT STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORT`
2651			`reported SUCCESSFULL!`
2652			`*****************************************************************************************`
2653
2654			`*****************************************************************************************`
2655			`At time 1993360000`
2656			`Test TARGET ABORT ERROR DURING SECOND DATAPHASE OF BURST READ`
2657			`reported SUCCESSFULL!`
2658			`*****************************************************************************************`
2659
2660			`*****************************************************************************************`
2661			`At time 1993640000`
2662			`Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORT`
2663			`reported SUCCESSFULL!`
2664			`*****************************************************************************************`
2665
2666			`*****************************************************************************************`
2667			`At time 1995020000`
2668			`Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READ`
2669			`reported SUCCESSFULL!`
2670			`*****************************************************************************************`
2671
2672			`*****************************************************************************************`
2673			`At time 1996260000`
2674			`Test TARGET ABORT ERROR DURING LAST DATAPHASE OF BURST READ`
2675			`reported SUCCESSFULL!`
2676			`*****************************************************************************************`
2677
2678			`*****************************************************************************************`
2679			`At time 1996560000`
2680			`Test PCI DEVICE STATUS REGISTER VALUE CHECK AFTER READ TERMINATED WITH TARGET ABORT`
2681			`reported SUCCESSFULL!`
2682			`*****************************************************************************************`
2683
2684			`*****************************************************************************************`
2685			`At time 1997920000`
2686			`Test CHECK NORMAL BURST READ AFTER TARGET ABORT TERMINATED BURST READ`
2687			`reported SUCCESSFULL!`
2688			`*****************************************************************************************`
2689
2690			`*****************************************************************************************`
2691			`At time 1998585000`
2692			`Test ERROR REPORTING FUNCTIONALITY FOR I/O WRITE`
2693			`reported SUCCESSFULL!`
2694			`*****************************************************************************************`
2695
2696			`*****************************************************************************************`
2697			`At time 1998900000`
2698			`Test WB ERROR STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITE`
2699			`reported SUCCESSFULL!`
2700			`*****************************************************************************************`
2701
2702			`*****************************************************************************************`
2703			`At time 1999500000`
2704			`Test WB ERRONEOUS ADDRESS AND DATA REGISTERS' VALUES AFTER MASTER ABORTED I/O WRITE`
2705			`reported SUCCESSFULL!`
2706			`*****************************************************************************************`
2707
2708			`*****************************************************************************************`
2709			`At time 1999800000`
2710			`Test INTERRUPT STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITE`
2711			`reported SUCCESSFULL!`
2712			`*****************************************************************************************`
2713
2714			`*****************************************************************************************`
2715			`At time 2000480000`
2716			`Test PCI DEVICE STATUS REGISTER VALUE AFTER MASTER ABORTED I/O WRITE`
2717			`reported SUCCESSFULL!`
2718			`*****************************************************************************************`
2719
2720			`.`
2721			`.`
2722			`.`
2723
2724
2725			`*****************************************************************************************`
2726			`At time 5175780000`
2727			`Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEARED`
2728			`reported SUCCESSFULL!`
2729			`*****************************************************************************************`
2730
2731			`*****************************************************************************************`
2732			`At time 5176900000`
2733			`Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ON LAST TRANSFER`
2734			`reported SUCCESSFULL!`
2735			`*****************************************************************************************`
2736
2737			`*****************************************************************************************`
2738			`At time 5177220000`
2739			`Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR`
2740			`reported SUCCESSFULL!`
2741			`*****************************************************************************************`
2742
2743			`*****************************************************************************************`
2744			`At time 5177640000`
2745			`Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WB`
2746			`reported SUCCESSFULL!`
2747			`*****************************************************************************************`
2748
2749			`*****************************************************************************************`
2750			`At time 5179380000`
2751			`Test POSTED WRITE THROUGH PCI TARGET ERROR TERMINATION ON WB ONE BEFORE LAST TRANSFER`
2752			`reported SUCCESSFULL!`
2753			`*****************************************************************************************`
2754
2755			`*****************************************************************************************`
2756			`At time 5179720000`
2757			`Test PCI ERROR CONTROL AND STATUS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR`
2758			`reported SUCCESSFULL!`
2759			`*****************************************************************************************`
2760
2761			`*****************************************************************************************`
2762			`At time 5180040000`
2763			`Test PCI ERRONEOUS DATA REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WB`
2764			`reported SUCCESSFULL!`
2765			`*****************************************************************************************`
2766
2767			`*****************************************************************************************`
2768			`At time 5180380000`
2769			`Test PCI ERRONEOUS ADDRESS REGISTER VALUE AFTER WRITE TERMINATED WITH ERROR ON WB`
2770			`reported SUCCESSFULL!`
2771			`*****************************************************************************************`
2772
2773			`*****************************************************************************************`
2774			`At time 5180780000`
2775			`Test INTERRUPT ASSERTION AND STATUS AFTER WRITE TERMINATED WITH ERROR ON WB`
2776			`reported SUCCESSFULL!`
2777			`*****************************************************************************************`
2778
2779			`*****************************************************************************************`
2780			`At time 5181255000`
2781			`Test CLEARING STATUS BITS AFTER WRITE TERMINATED WITH ERROR ON WB`
2782			`reported SUCCESSFULL!`
2783			`*****************************************************************************************`
2784
2785			`*****************************************************************************************`
2786			`At time 5181320000`
2787			`Test INTERRUPT REQUEST FINISHED AFTER PCI ERROR INTERRUPT STATUS IS CLEARED`
2788			`reported SUCCESSFULL!`
2789			`*****************************************************************************************`
2790
2791			`*****************************************************************************************`
2792			`At time 5184680000`
2793			`Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGE`
2794			`reported SUCCESSFULL!`
2795			`*****************************************************************************************`
2796
2797			`*****************************************************************************************`
2798			`At time 5187690000`
2799			`Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTES`
2800			`reported SUCCESSFULL!`
2801			`*****************************************************************************************`
2802
2803			`*****************************************************************************************`
2804			`At time 5190200000`
2805			`Test BYTE ADDRESSABLE WRITES THROUGH TARGET IO IMAGE`
2806			`reported SUCCESSFULL!`
2807			`*****************************************************************************************`
2808
2809			`*****************************************************************************************`
2810			`At time 5193210000`
2811			`Test READ BY WORDS IO DATA PREVIOUSLY WRITTEN BY BYTES`
2812			`reported SUCCESSFULL!`
2813			`*****************************************************************************************`
2814
2815			`*****************************************************************************************`
2816			`At time 5195160000`
2817			`Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONE`
2818			`reported SUCCESSFULL!`
2819			`*****************************************************************************************`
2820
2821			`*****************************************************************************************`
2822			`At time 5195500000`
2823			`Test INTERRUPT STATUS REGISTER VALUE AFTER ERROR TERMINATED WRITE ON WISHBONE`
2824			`reported SUCCESSFULL!`
2825			`*****************************************************************************************`
2826
2827			`*****************************************************************************************`
2828			`At time 5195580000`
2829			`Test INTERRUPT REQUEST DEASSERTION AFTER CLEARING INTERRUPT STATUS`
2830			`reported SUCCESSFULL!`
2831			`*****************************************************************************************`
2832
2833			`*****************************************************************************************`
2834			`At time 5196360000`
2835			`Test ERROR STATUS REGISTER VALUE CHECK AFTER ERROR TERMINATED POSTED IO WRITE ON WISHBONE`
2836			`reported SUCCESSFULL!`
2837			`*****************************************************************************************`
2838
2839			`.`
2840			`.`
2841			`.`
2842
2843
2844			`*****************************************************************************************`
2845			`At time 35435595000`
2846			`Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATION`
2847			`reported SUCCESSFULL!`
2848			`*****************************************************************************************`
2849
2850			`*****************************************************************************************`
2851			`At time 35435805000`
2852			`Test TARGET ABORT SIGNALING ON I/O ACCESSES WITH INVALID ADDRESS/BYTE ENABLE COMBINATION`
2853			`reported SUCCESSFULL!`
2854			`*****************************************************************************************`
2855
2856			`*****************************************************************************************`
2857			`At time 35436615000`
2858			`Test PCI DEVICE STATUS REGISTER VALUE AFTER TARGET ABORT`
2859			`reported SUCCESSFULL!`
2860			`*****************************************************************************************`
2861
2862			`*****************************************************************************************`
2863			`At time 35437060000`
2864			`Test ERROR CONTROL AND STATUS REGISTER VALUE CHECK AFTER TARGET ABORTS`
2865			`reported SUCCESSFULL!`
2866			`*****************************************************************************************`
2867
2868			`*****************************************************************************************`
2869			`At time 35442465000`
2870			`Test SIMULTANEOUS WRITE REFERENCE TO WB SLAVE AND PCI TARGET`
2871			`reported SUCCESSFULL!`
2872			`*****************************************************************************************`
2873
2874			`*****************************************************************************************`
2875			`At time 35445045000`
2876			`Test SIMULTANEOUS MULTI BEAT WRITES THROUGH WB SLAVE AND PCI TARGET`
2877			`reported SUCCESSFULL!`
2878			`*****************************************************************************************`
2879
2880			`*****************************************************************************************`
2881			`At time 35446240000`
2882			`Test SIMULTANEOUS MULTI BEAT WRITE REFERENCE TO PCI TARGET AND WB SLAVE`
2883			`reported SUCCESSFULL!`
2884			`*****************************************************************************************`
2885
2886			`*****************************************************************************************`
2887			`At time 35450840000`
2888			`Test ORDERING OF TRANSACTIONS MOVING IN SAME DIRECTION - WRITE THROUGH WB SLAVE, READ THROUGH PCI TARGET`
2889			`reported SUCCESSFULL!`
2890			`*****************************************************************************************`
2891
2892			`*****************************************************************************************`
2893			`At time 35453520000`
2894			`Test ORDERING OF TRANSACTIONS MOVING IN SAME DIRECTION - WRITE THROUGH PCI TARGET, READ THROUGH WB SLAVE`
2895			`reported SUCCESSFULL!`
2896			`*****************************************************************************************`
2897
2898			`***************************** PCI Testcase summary *****************************`
2899			`Tests performed: 36000`
2900			`Failed tests : 0`
2901			`Successfull tests: 36000`
2902			`***************************** PCI Testcase summary *****************************`

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[/] [pci/] [tags/] [rel_WB_B3/] [sim/] [rtl_sim/] [log/] [example_pci_tb.log] - Blame information for rev 154