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mihad |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// File name "constants.v" ////
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//// ////
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//// This file is part of the "PCI bridge" project ////
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//// http://www.opencores.org/cores/pci/ ////
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//// ////
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//// Author(s): ////
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//// - Miha Dolenc (mihad@opencores.org) ////
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//// - Tadej Markovic (tadej@opencores.org) ////
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//// ////
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//// All additional information is avaliable in the README.pdf ////
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//// file. ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 Miha Dolenc, mihad@opencores.org ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2001/07/17 15:11:14 mihad
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// Added some WISHBONE slave defines
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//
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//
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////////////////////////////////////////////////////////////////////////
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//// ////
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//// FIFO parameters define behaviour of FIFO control logic and ////
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//// FIFO depths. ////
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//// ////
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////////////////////////////////////////////////////////////////////////
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// FPGA implementation definitions :
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// FPGA definition is optional - if it's defined, BLOCK SelectRam+ will
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// be used for FIFO storage space. Implementation is SYNCHRONOUS regardles
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// of SYNCHRONOUS parameter definition. Smallest FPGA must have at leat 6
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// block select rams available. For bigger FPGAs, there is possibility of
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// defining BIG - only for FPGAs with 12 or more available block rams
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// Defining FPGA without BIG limits any FIFO to max depth of 128 ( address
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// length 7). Large FPGAs with BIG definition provide max 256 ( address length
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// 8) depth for each FIFO. FIFO depth MUST be power of 2, so address length can
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// be defined
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// Minimum FIFO depth of any FIFO is 8 - control logic is such that address
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// lengths less than 3 are not supported
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`define FPGA
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`define WBW_DEPTH 16
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`define WBW_ADDR_LENGTH 4
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`define WBR_DEPTH 32
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`define WBR_ADDR_LENGTH 5
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`define PCIW_DEPTH 64
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`define PCIW_ADDR_LENGTH 6
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`define PCIR_DEPTH 128
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`define PCIR_ADDR_LENGTH 7
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//`define BIG
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// if FPGA is not defined (commented out), there can still be control logic
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// for synchronous rams used by defining SYNCHRONOUS
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`define SYNCHRONOUS
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// if neither FPGA or SYNCRONOUS are defined, control logic for asynchronous
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// rams is included
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// control bus encoding definitions
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`define ADDRESS 4'hf // address entry
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`define LAST 4'h0 // last data entry in transaction
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`define DATA_ERROR 4'h8 // data was read with error signaled
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`define DATA 4'h1 // intermediate data beat in a burst
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// Flip flop delay included in assignements to every register
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`define FF_DELAY 2 // FF propagation delay
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`timescale 100ps/10ps
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// PCI bridge HOST/GUEST implentation
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// - for HOST implementation 'HOST' MUST be written othervise there is GUEST
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// implementation and 'GUEST MUST be written !!!
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`define HOST
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// MAX Retry counter value for WISHBONE Master state-machine
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// This value is 8-bit because of 8-bit retry counter !!!
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`define WB_RTY_CNT_MAX 8'hff
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// no. of PCI Target IMAGES
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// - The maximum number of images is "6". By default there are first two images
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// used and the first (PCI_IMAGE0) is assigned to Configuration space! With a
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// 'define' PCI_IMAGEx you choose the number of used PCI IMAGES in a bridge
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// without PCI_IMAGE0 (e.g. PCI_IMAGE3 tells, that PCI_IMAGE1, PCI_IMAGE2 and
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// PCI_IMAGE3 are used for mapping the space from WB to PCI. Offcourse,
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// PCI_IMAGE0 is assigned to Configuration space). That leave us PCI_IMAGE5 as
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// the maximum number of images.
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// There is one exeption, when the core is implemented as HOST. If so, then the
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// PCI specification allowes the Configuration space NOT to be visible on the
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// PCI bus. With `define PCI_IMAGE6 (and `define HOST), we assign PCI_IMAGE0
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// to normal WB to PCI image and not to configuration space!
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`define PCI_IMAGE6
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// no. of WISHBONE Slave IMAGES
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// - The maximum number of images is "6". By default there are first two images
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// used and the first (WB_IMAGE0) is assigned to Configuration space! With a
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// 'define' WB_IMAGEx you choose the number of used WB IMAGES in a bridge
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// without WB_IMAGE0 (e.g. WB_IMAGE3 tells, that WB_IMAGE1, WB_IMAGE2 and
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// WB_IMAGE3 are used for mapping the space from PCI to WB. Offcourse,
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// WB_IMAGE0 is assigned to Configuration space). That leave us WB_IMAGE5 as
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// the maximum number of images.
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`define WB_IMAGE5
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// Configuration space base address for accesses from WISHBONE bus
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`define WB_CONFIGURATION_BASE 20'hCCCC_C
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// PCI target & WB slave ADDRESS names for configuration space !!!
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`define P_IMG_CTRL0_ADDR 12'h100
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`define P_BA0_ADDR 12'h104 // = PCI_CONF_SPC_BAR
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`define P_AM0_ADDR 12'h108
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`define P_TA0_ADDR 12'h10c
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`define P_IMG_CTRL1_ADDR 12'h110
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`define P_BA1_ADDR 12'h114
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`define P_AM1_ADDR 12'h118
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`define P_TA1_ADDR 12'h11c
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`define P_IMG_CTRL2_ADDR 12'h120
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`define P_BA2_ADDR 12'h124
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`define P_AM2_ADDR 12'h128
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`define P_TA2_ADDR 12'h12c
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`define P_IMG_CTRL3_ADDR 12'h130
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`define P_BA3_ADDR 12'h134
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`define P_AM3_ADDR 12'h138
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`define P_TA3_ADDR 12'h13c
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`define P_IMG_CTRL4_ADDR 12'h140
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`define P_BA4_ADDR 12'h144
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`define P_AM4_ADDR 12'h148
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`define P_TA4_ADDR 12'h14c
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`define P_IMG_CTRL5_ADDR 12'h150
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`define P_BA5_ADDR 12'h154
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`define P_AM5_ADDR 12'h158
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`define P_TA5_ADDR 12'h15c
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`define P_ERR_CS_ADDR 12'h160
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`define P_ERR_ADDR_ADDR 12'h164
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`define P_ERR_DATA_ADDR 12'h168
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`define WB_CONF_SPC_BAR_ADDR 12'h800
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`define W_IMG_CTRL1_ADDR 12'h804
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`define W_BA1_ADDR 12'h808
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`define W_AM1_ADDR 12'h80c
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`define W_TA1_ADDR 12'h810
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`define W_IMG_CTRL2_ADDR 12'h814
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`define W_BA2_ADDR 12'h818
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`define W_AM2_ADDR 12'h81c
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`define W_TA2_ADDR 12'h820
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`define W_IMG_CTRL3_ADDR 12'h824
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`define W_BA3_ADDR 12'h828
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`define W_AM3_ADDR 12'h82c
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`define W_TA3_ADDR 12'h830
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`define W_IMG_CTRL4_ADDR 12'h834
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`define W_BA4_ADDR 12'h838
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`define W_AM4_ADDR 12'h83c
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`define W_TA4_ADDR 12'h840
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`define W_IMG_CTRL5_ADDR 12'h844
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`define W_BA5_ADDR 12'h848
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`define W_AM5_ADDR 12'h84c
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`define W_TA5_ADDR 12'h850
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`define W_ERR_CS_ADDR 12'h854
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`define W_ERR_ADDR_ADDR 12'h858
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`define W_ERR_DATA_ADDR 12'h85c
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`define CNF_ADDR_ADDR 12'h860
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`define CNF_DATA_ADDR 12'h864
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`define INT_ACK_ADDR 12'h868
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`define ICR_ADDR 12'hff8
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`define ISR_ADDR 12'hffc
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// the width of the registers
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`define REG_WIDTH 32
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// timing delays
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`define DLY_L1 1
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`define DLY_L2 2
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`define DLY_L3 3
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`define DLY_L4 4
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`define DLY_L5 5
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/*-----------------------------------------------------------------------------------------------------------
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[000h-00Ch] First 4 DWORDs (32-bit) of PCI configuration header - the same regardless of the HEADER type !
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r_ prefix is a sign for read only registers
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Vendor_ID is an ID for a specific vendor defined by PCI_SIG - 2321h does not belong to anyone (e.g.
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Xilinx's Vendor_ID is 10EEh and Altera's Vendor_ID is 1172h). Device_ID and Revision_ID should be used
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together by application.
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66MHz goes into 66MHz capable bit and indicates that device can operate on 66MHz PCI bus.
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-----------------------------------------------------------------------------------------------------------*/
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`define HEADER_DEVICE_ID 16'h0001
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`define HEADER_VENDOR_ID 16'h2321
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`define HEADER_REVISION_ID 8'h01
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`define HEADER_66MHz 1'b0
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