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[/] [pci/] [tags/] [working_demo/] [old_stuff/] [pci_master32/] [pci_master32_sm.v] - Blame information for rev 154

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1 2 mihad 
`include "pci_stat.v"
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module pci_master32_sm
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(
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    // system inputs
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    clk_in,
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    reset_in,
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    // arbitration
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    pci_req_out,
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    pci_req_en_out,
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    pci_gnt_in,
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    // master in/outs
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    pci_frame_in,
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    pci_frame_out,
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    pci_frame_en_out,
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    pci_irdy_in,
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    pci_irdy_out,
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    pci_irdy_en_out,
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    // target response inputs
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    pci_trdy_in,
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    pci_stop_in,
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    pci_devsel_in,
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    // address, data, bus command, byte enable in/outs
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    pci_ad_in,
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    pci_ad_out,
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    pci_ad_en_out,
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    pci_cbe_out,
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    pci_cbe_en_out,
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    // other side of state machine
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    address_i,
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    bc_i,
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    data_i,
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    data_o,
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    be_i,
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    req_i,
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    rdy_i,
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    status_o,
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    last_i,
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    latency_tim_val_i
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) ;
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// system inputs
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input   clk_in,
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        reset_in ;
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/*==================================================================================================================
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PCI interface signals - bidirectional signals are divided to inputs and outputs in I/O cells instantiation
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module. Enables are separate signals.
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==================================================================================================================*/
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// arbitration
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output  pci_req_out,
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        pci_req_en_out ;
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input   pci_gnt_in ;
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// master in/outs
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input    pci_frame_in ;
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output   pci_frame_out,
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         pci_frame_en_out ;
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input    pci_irdy_in ;
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output   pci_irdy_out,
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         pci_irdy_en_out,
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// target response inputs
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input   pci_trdy_in,
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        pci_stop_in,
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        pci_devsel_in ;
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// address, data, bus command, byte enable in/outs
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input   [31:0]  pci_ad_in ;
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output  [31:0]  pci_ad_out ;
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output          pci_ad_en_out ;
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output  [3:0]   pci_cbe_out ;
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output          pci_cbe_en_out ;
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/*==================================================================================================================
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Other side of master state machine - the one that issues requests.
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==================================================================================================================*/
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/*==================================================================================================================
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address input - address always qualifies current data present at data_i input or data that needs to be read from
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                data_o output.
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==================================================================================================================*/
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input   [31:0]  address_i ; // current request address input
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/*==================================================================================================================
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bus command input - bus command is always valid vhen request is asserted and identifies what state machine should
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                    do.
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==================================================================================================================*/
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input   [3:0]   bc_i ;      // current request bus command input
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/*==================================================================================================================
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data input - for PCI write bus commands - this bus provides valid write data during write commands when rdy_i is
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             asserted. If rdy_i is deasserted then state machine inserts wait states ( if between burst )
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==================================================================================================================*/
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input   [31:0]  data_i ;    // current dataphase data input
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/*==================================================================================================================
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data output - for PCI read bus commands - data on this bus is provided from master state machine and is qualified
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              with `TRANSFERED status. When `TRANSFERED status is present on status output, backend is responsible
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              for storing this data. Backend signals if it is ready to accept data with rdy_i input.
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==================================================================================================================*/
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output  [31:0]  data_o ;    // for read operations - current request data output
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/*==================================================================================================================
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byte enable input - active low byte enables for driving BE# pins on pci during transfers - they are valid always
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                    when request is asserted by the backend
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==================================================================================================================*/
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input   [3:0]   be_i ;      // current dataphase byte enable inputs
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/*==================================================================================================================
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request and ready inputs from backend - req_i input means that backend has some transaction request for PCI bus.
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During write requests it must provide address, bus command, byte enables and data. Write data is qualified with
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rdy_i signal input. State machine signals status back to the backend. Statuses are described later.
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During read requests backend must provide address, bus command and byte enables to the state machine. When it is ready
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to receive data, it asserts rdy_i. Status of current request is signaled to back end all the time.
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==================================================================================================================*/
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input           req_i ;     // initiator cycle is requested
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input           rdy_i ;     // requestor indicates that data is ready to be sent for write transaction and ready to
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                            // be received on read transaction
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/*==================================================================================================================
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Last input - this input in conjuction with req_i and rdy_i qualifies last data beat in current request.
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             for single transfers all three signals are asserted in parallel, for burst transfers last_i is inactive
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             until last intended data is present at data_i or requested from data_o. After last is sampled asserted,
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             state machine must go to idle state and monitor for new requests.
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==================================================================================================================*/
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input           last_i ;    // last dataphase in current transaction indicator
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/*==================================================================================================================
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Status output - Status is always provided to the backend depending on PCI transaction progress. Status descriptions:
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`WAIT - default status - means that current request is not processed in any way yet - this status is propagated
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        to backend when Master state machine is requesting for the bus, latency timer has expired on current phase,
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        target is inserting wait states or rdy_i input is down.
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`TRANSFERED - status means, that current data phase is completing succesfully on PCI bus. During writes, this status
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              signals to the backend that it should provide new data imediately after rising clock edge or deassert
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              rdy_i if it is not ready to do so. During reads, this status signals to the backend that on the rising
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              edge of clock data must be latched from data_o bus. After this, backend must deassert rdy_i if it is not
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              ready to accept more data.
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`DISCONNECT_WO_DATA - Disconnect Without Data can be treated by the backend the same as `WAIT status. Separate status
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                      is provided only becuse some backends might use it for different purposes.
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`DISCONNECT_W_DATA  - Dissconnect With Data can be treated the same as `TRANSFERED status. Separate status is
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                      provided because some backends might use it for different purposes
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`TABORT - Target Abort status - current transfer resulted in target abort termination. Backend must not repeat this
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                                transaction anymore. State machine is not responsible for error handling
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`MABORT - State Machine signals this status to backend when no Target claims the transaction. Backend must decide if
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          this is an error or not. State machine isn't responsible for error handling
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`RETRY  - State Machine signals this status to backend when Target Retry occurs on current dataphase. State Machine
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          is responsible for releasing a bus, by PCI protocol, while transaction repeating is up to backend.
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==================================================================================================================*/
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output  [3:0]   status_o ;  // current dataphase completion status
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// latency timer value input - state machine starts latency timer whenever it starts a transaction and last is not
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// asserted ( meaning burst transfer ).
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input [7:0] latency_tim_val_i ;
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endmodule

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