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mihad |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// File name "delayed_write_reg.v" ////
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//// ////
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//// This file is part of the "PCI bridge" project ////
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//// http://www.opencores.org/cores/pci/ ////
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//// ////
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//// Author(s): ////
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//// - mihad@opencores.org ////
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//// - Miha Dolenc ////
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//// ////
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//// All additional information is avaliable in the README.pdf ////
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//// file. ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2001/07/19 09:44:20 mihad
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// Only delayed write storage is provided after merging delayed requests.
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// All delayed reads now pass through FIFO.
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//
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//
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`include "constants.v"
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module DELAYED_WRITE_REG
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(
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reset_in,
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req_clk_in,
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comp_wdata_out,
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req_we_in,
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req_wdata_in
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);
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// system inputs
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input reset_in,
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req_clk_in ; // request clock input
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output [31:0] comp_wdata_out ; // data output
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input req_we_in ; // write enable input
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input [31:0] req_wdata_in ; // data input - latched with posedge of req_clk_in when req_we_in is high
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reg [31:0] comp_wdata_out ;
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// write request operation
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always@(posedge req_clk_in or posedge reset_in)
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begin
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if (reset_in)
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comp_wdata_out <= #`FF_DELAY 32'h0000_0000 ;
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else
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if (req_we_in)
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comp_wdata_out <= #`FF_DELAY req_wdata_in ;
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end
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endmodule // IACK_STORAGE
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