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[/] [pci/] [tags/] [working_demo/] [old_stuff/] [wb_slave/] [test_bench/] [wb_master32.v] - Blame information for rev 154

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  File name "wb_master32.v"                                   ////
////                                                              ////
////  This file is part of the "PCI bridge" project               ////
////  http://www.opencores.org/cores/pci/                         ////
////                                                              ////
////  Author(s):                                                  ////
////      - Miha Dolenc (mihad@opencores.org)                     ////
////      - Winefred Washington                                   ////
////                                                              ////
////  All additional information is avaliable in the README.pdf   ////
////  file.                                                       ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2  2001/07/19 09:50:08  mihad
// Only delayed write storage is provided after merging delayed requests.
// All delayed reads now pass through FIFO.
//
//
 
`define Tp 1
 
module WB_MASTER32(CLK_I, RST_I, TAG_I, TAG_O,
                   ACK_I, ADR_O, CYC_O, DAT_I, DAT_O, ERR_I, RTY_I, SEL_O, STB_O, WE_O, CAB_O);
 
    input               CLK_I;
    input                   RST_I;
    input    [3:0]       TAG_I;
    output   [3:0]  TAG_O;
    input                   ACK_I;
    output   [31:0] ADR_O;
    output                  CYC_O;
    input    [31:0] DAT_I;
    output   [31:0] DAT_O;
    input               ERR_I;
    input                   RTY_I;
    output   [3:0]       SEL_O;
    output              STB_O;
    output                  WE_O;
    output          CAB_O ;
 
    reg [31:0]  ADR_O;
    reg [3:0]    SEL_O;
    reg                 CYC_O;
    reg                 WE_O;
    reg [31:0]   DAT_O;
    reg         CAB_O ;
    reg         STB_O ;
 
    // timeout counter and timeout flag for canceling deadlocked cycles 
    reg [7:0]   tocount ;
    reg         toflag ;
 
    // assign outputs to unknown state while in reset
    always@(RST_I)
    begin
        if (RST_I)
        begin
                ADR_O <= 32'hxxxx_xxxx ;
            SEL_O <= 4'hx ;
            CYC_O <= 1'b0 ;
                    WE_O  <= 1'bx ;
                    DAT_O <= 32'hxxxx_xxxx ;
            CAB_O <= 1'b0 ;
            STB_O <= 1'b0 ;
        end
    end //reset
 
    task blkwr ;
        input [31:0]    address ;   // address input
        input [31:0]    data ;      // data input 
        input [3:0]     select ;    // selects input
        input           burst ;     // burst (cab) input flag
        input           start ;     // start flag
        input           stop ;      // stop flag - terminates cycle
        output [2:0]    result ;    // result output: result[2] = acknowledge, result[1] = error, result[0] = retry
    begin
        // if this is the first cycle, synchronize operation to clock
        if (start)
            @(posedge CLK_I) ;
 
        // assign outputs
        ADR_O <= #`Tp address ;
        SEL_O <= #`Tp select ;
        CYC_O <= #`Tp 1'b1 ;
                WE_O  <= #`Tp 1'b1 ;
                DAT_O <= #`Tp data ;
        CAB_O <= #`Tp burst ;
 
        // if data is not valid insert a wait cycle - STB = 0
        if (data  === 32'hxxxxxxxx)
            STB_O <= #`Tp 1'b0 ;
        else
            STB_O <= #`Tp 1'b1 ;
 
        // wait for current cycle to end
        @(posedge CLK_I) ;
 
        if (STB_O)
            while (~(ACK_I || ERR_I || RTY_I || toflag))
                @(posedge CLK_I) ;
 
        result = {ACK_I, ERR_I, RTY_I} ;
 
        STB_O <= #`Tp 1'b0 ;
 
        // terminate the cycle if stop flag is set or error, retry or timeout is signalled
        if(stop || result[1:0])
        begin
            CYC_O <= #`Tp 1'b0 ;
            CAB_O <= #`Tp 1'b0 ;
        end
 
        #`Tp ;
    end
    endtask // blkwr
 
    task blkrd ;
        input   [31:0]  address ;       // read address
        input   [3:0]   select ;        // byte selects
        input           burst ;         // burst flag
        input           start ;         // start flag
        input           stop ;          // stop flag
        output  [34:0]  status_w_data ; // status with data - [34:32] = status[34]=acknowledge, status[33]=error, status[32]=retry
        reg     [2:0]   result ;
    begin
        // if this is the first cycle, synchronize operation to clock
        if (start)
            @(posedge CLK_I) ;
 
        // assign outputs
        ADR_O <= #`Tp address ;
        SEL_O <= #`Tp select ;
        CYC_O <= #`Tp 1'b1 ;
                WE_O  <= #`Tp 1'b0 ;
        CAB_O <= #`Tp burst ;
        STB_O <= #`Tp 1'b1 ;
 
        // invalid selects insert wait cycles
        if (select === 4'bxxxx)
            STB_O <= #`Tp 1'b0 ;
        else
            STB_O <= #`Tp 1'b1 ;
 
        // wait for current cycle to end
        @(posedge CLK_I) ;
        if (STB_O)
            while (~(ACK_I || ERR_I || RTY_I || toflag))
                @(posedge CLK_I) ;
 
        result = {ACK_I, ERR_I, RTY_I} ;
        status_w_data = {result, DAT_I} ;
 
        STB_O <= #`Tp 1'b0 ;
 
        if(stop || result[1:0] || toflag)
        begin
            CYC_O <= #`Tp 1'b0 ;
            CAB_O <= #`Tp 1'b0 ;
        end
 
        #`Tp ;
    end
    endtask // blkrd
 
    // timeout flag generation
    always@(posedge CLK_I or posedge RST_I)
    begin
        if (RST_I)
        begin
            toflag  <= 1'b0 ;
            tocount <= 8'h00 ;
        end
        else
        begin
            // whenever cycle is in progress and data is qualified count cycles with no slave response
            if (CYC_O && STB_O && ~(ACK_I || ERR_I || RTY_I))
            begin
                tocount <= tocount + 1 ;
            end
            else
            // reset counter and flag when cycle or strobe are inactive or slave responds whith whatever response signal
            begin
                tocount <= 8'h00 ;
                toflag  <= 1'b0 ;
            end
 
            if ( tocount == 8'hFF)
                toflag <= 1'b1 ;
        end
 
 
    end
endmodule
 
 
 
 
 

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[/] [pci/] [tags/] [working_demo/] [old_stuff/] [wb_slave/] [test_bench/] [wb_master32.v] - Blame information for rev 154

Line No.	Rev	Author	Line
1	2	mihad	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// File name "wb_master32.v" ////`
4			`//// ////`
5			`//// This file is part of the "PCI bridge" project ////`
6			`//// http://www.opencores.org/cores/pci/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Miha Dolenc (mihad@opencores.org) ////`
10			`//// - Winefred Washington ////`
11			`//// ////`
12			`//// All additional information is avaliable in the README.pdf ////`
13			`//// file. ////`
14			`//// ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42			`//`
43			`// CVS Revision History`
44			`//`
45			`// $Log: not supported by cvs2svn $`
46			`// Revision 1.2 2001/07/19 09:50:08 mihad`
47			`// Only delayed write storage is provided after merging delayed requests.`
48			`// All delayed reads now pass through FIFO.`
49			`//`
50			`//`
51
52			`define Tp 1
53
54			`module WB_MASTER32(CLK_I, RST_I, TAG_I, TAG_O,`
55			`ACK_I, ADR_O, CYC_O, DAT_I, DAT_O, ERR_I, RTY_I, SEL_O, STB_O, WE_O, CAB_O);`
56
57			`input CLK_I;`
58			`input RST_I;`
59			`input [3:0] TAG_I;`
60			`output [3:0] TAG_O;`
61			`input ACK_I;`
62			`output [31:0] ADR_O;`
63			`output CYC_O;`
64			`input [31:0] DAT_I;`
65			`output [31:0] DAT_O;`
66			`input ERR_I;`
67			`input RTY_I;`
68			`output [3:0] SEL_O;`
69			`output STB_O;`
70			`output WE_O;`
71			`output CAB_O ;`
72
73			`reg [31:0] ADR_O;`
74			`reg [3:0] SEL_O;`
75			`reg CYC_O;`
76			`reg WE_O;`
77			`reg [31:0] DAT_O;`
78			`reg CAB_O ;`
79			`reg STB_O ;`
80
81			`// timeout counter and timeout flag for canceling deadlocked cycles`
82			`reg [7:0] tocount ;`
83			`reg toflag ;`
84
85			`// assign outputs to unknown state while in reset`
86			`always@(RST_I)`
87			`begin`
88			`if (RST_I)`
89			`begin`
90			`ADR_O <= 32'hxxxx_xxxx ;`
91			`SEL_O <= 4'hx ;`
92			`CYC_O <= 1'b0 ;`
93			`WE_O <= 1'bx ;`
94			`DAT_O <= 32'hxxxx_xxxx ;`
95			`CAB_O <= 1'b0 ;`
96			`STB_O <= 1'b0 ;`
97			`end`
98			`end //reset`
99
100			`task blkwr ;`
101			`input [31:0] address ; // address input`
102			`input [31:0] data ; // data input`
103			`input [3:0] select ; // selects input`
104			`input burst ; // burst (cab) input flag`
105			`input start ; // start flag`
106			`input stop ; // stop flag - terminates cycle`
107			`output [2:0] result ; // result output: result[2] = acknowledge, result[1] = error, result[0] = retry`
108			`begin`
109			`// if this is the first cycle, synchronize operation to clock`
110			`if (start)`
111			`@(posedge CLK_I) ;`
112
113			`// assign outputs`
114			ADR_O <= #`Tp address ;
115			SEL_O <= #`Tp select ;
116			CYC_O <= #`Tp 1'b1 ;
117			WE_O <= #`Tp 1'b1 ;
118			DAT_O <= #`Tp data ;
119			CAB_O <= #`Tp burst ;
120
121			`// if data is not valid insert a wait cycle - STB = 0`
122			`if (data === 32'hxxxxxxxx)`
123			STB_O <= #`Tp 1'b0 ;
124			`else`
125			STB_O <= #`Tp 1'b1 ;
126
127			`// wait for current cycle to end`
128			`@(posedge CLK_I) ;`
129
130			`if (STB_O)`
131			`while (~(ACK_I \|\| ERR_I \|\| RTY_I \|\| toflag))`
132			`@(posedge CLK_I) ;`
133
134			`result = {ACK_I, ERR_I, RTY_I} ;`
135
136			STB_O <= #`Tp 1'b0 ;
137
138			`// terminate the cycle if stop flag is set or error, retry or timeout is signalled`
139			`if(stop \|\| result[1:0])`
140			`begin`
141			CYC_O <= #`Tp 1'b0 ;
142			CAB_O <= #`Tp 1'b0 ;
143			`end`
144
145			#`Tp ;
146			`end`
147			`endtask // blkwr`
148
149			`task blkrd ;`
150			`input [31:0] address ; // read address`
151			`input [3:0] select ; // byte selects`
152			`input burst ; // burst flag`
153			`input start ; // start flag`
154			`input stop ; // stop flag`
155			`output [34:0] status_w_data ; // status with data - [34:32] = status[34]=acknowledge, status[33]=error, status[32]=retry`
156			`reg [2:0] result ;`
157			`begin`
158			`// if this is the first cycle, synchronize operation to clock`
159			`if (start)`
160			`@(posedge CLK_I) ;`
161
162			`// assign outputs`
163			ADR_O <= #`Tp address ;
164			SEL_O <= #`Tp select ;
165			CYC_O <= #`Tp 1'b1 ;
166			WE_O <= #`Tp 1'b0 ;
167			CAB_O <= #`Tp burst ;
168			STB_O <= #`Tp 1'b1 ;
169
170			`// invalid selects insert wait cycles`
171			`if (select === 4'bxxxx)`
172			STB_O <= #`Tp 1'b0 ;
173			`else`
174			STB_O <= #`Tp 1'b1 ;
175
176			`// wait for current cycle to end`
177			`@(posedge CLK_I) ;`
178			`if (STB_O)`
179			`while (~(ACK_I \|\| ERR_I \|\| RTY_I \|\| toflag))`
180			`@(posedge CLK_I) ;`
181
182			`result = {ACK_I, ERR_I, RTY_I} ;`
183			`status_w_data = {result, DAT_I} ;`
184
185			STB_O <= #`Tp 1'b0 ;
186
187			`if(stop \|\| result[1:0] \|\| toflag)`
188			`begin`
189			CYC_O <= #`Tp 1'b0 ;
190			CAB_O <= #`Tp 1'b0 ;
191			`end`
192
193			#`Tp ;
194			`end`
195			`endtask // blkrd`
196
197			`// timeout flag generation`
198			`always@(posedge CLK_I or posedge RST_I)`
199			`begin`
200			`if (RST_I)`
201			`begin`
202			`toflag <= 1'b0 ;`
203			`tocount <= 8'h00 ;`
204			`end`
205			`else`
206			`begin`
207			`// whenever cycle is in progress and data is qualified count cycles with no slave response`
208			`if (CYC_O && STB_O && ~(ACK_I \|\| ERR_I \|\| RTY_I))`
209			`begin`
210			`tocount <= tocount + 1 ;`
211			`end`
212			`else`
213			`// reset counter and flag when cycle or strobe are inactive or slave responds whith whatever response signal`
214			`begin`
215			`tocount <= 8'h00 ;`
216			`toflag <= 1'b0 ;`
217			`end`
218
219			`if ( tocount == 8'hFF)`
220			`toflag <= 1'b1 ;`
221			`end`
222
223
224			`end`
225			`endmodule`
226
227
228
229
230