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mihad |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// File name "wb_slave.v" ////
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//// ////
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//// This file is part of the "PCI bridge" project ////
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//// http://www.opencores.org/cores/pci/ ////
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//// ////
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//// Author(s): ////
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//// - Miha Dolenc (mihad@opencores.org) ////
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//// ////
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//// All additional information is avaliable in the README.pdf ////
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//// file. ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.6 2001/07/30 15:24:02 mihad
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// Updated selects checking on WISHBONE bus, so it does not pass any
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// requests to pci which conflict with pci specification.
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//
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//
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`define FSM_BITS 4 // number of bits needed for FSM states
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// WISHBONE data output selections encoding
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`include "bus_commands.v"
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`include "constants.v"
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module WB_SLAVE( wb_clock_in,
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reset_in,
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wb_hit_in,
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wb_conf_hit_in,
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wb_map_in,
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wb_pref_en_in,
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wb_mrl_en_in,
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wb_addr_in,
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del_bc_in,
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wb_del_req_pending_in,
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wb_del_comp_pending_in,
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pci_drcomp_pending_in,
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del_bc_out,
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del_req_out,
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del_done_out,
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del_burst_out,
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del_write_out,
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del_write_in,
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del_error_in,
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del_in_progress_out,
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ccyc_addr_in,
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wb_del_addr_in,
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wb_del_be_in,
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wb_conf_offset_out,
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wb_conf_renable_out,
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wb_conf_wenable_out,
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wb_conf_be_out,
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wb_conf_data_in,
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wb_conf_data_out,
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wb_data_out,
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wb_cbe_out,
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wbw_fifo_wenable_out,
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wbw_fifo_control_out,
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wbw_fifo_almost_full_in,
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wbw_fifo_full_in,
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wbr_fifo_renable_out,
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wbr_fifo_be_in,
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wbr_fifo_data_in,
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wbr_fifo_control_in,
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wbr_fifo_flush_out,
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wbr_fifo_almost_empty_in,
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wbr_fifo_empty_in,
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pciw_fifo_empty_in,
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wbs_lock_in,
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CYC_I,
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STB_I,
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WE_I,
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SEL_I,
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SDATA_I,
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SDATA_O,
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ACK_O,
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RTY_O,
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ERR_O,
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CAB_I
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);
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/*----------------------------------------------------------------------------------------------------------------------
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Various parameters needed for state machine and other stuff
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----------------------------------------------------------------------------------------------------------------------*/
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parameter WBR_SEL = 1'b0 ;
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parameter CONF_SEL = 1'b1 ;
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parameter S_IDLE = `FSM_BITS'h0 ;
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parameter S_W_ADDR_DATA = `FSM_BITS'h1 ;
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parameter S_TURN_ARROUND = `FSM_BITS'h2 ;
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parameter S_READ = `FSM_BITS'h3 ;
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parameter S_CONF_WRITE = `FSM_BITS'h4 ;
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parameter S_CONF_READ = `FSM_BITS'h5 ;
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/*----------------------------------------------------------------------------------------------------------------------
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System signals inputs
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wb_clock_in - WISHBONE bus clock input
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reset_in - system reset input controlled by bridge's reset logic
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----------------------------------------------------------------------------------------------------------------------*/
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input wb_clock_in, reset_in ;
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/*----------------------------------------------------------------------------------------------------------------------
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Inputs from address decoding logic
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wb_hit_in - Decoder logic indicates if address is in a range of one of images
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wb_conf_hit_in - Decoder logic indicates that address is in configuration space range
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wb_map_in - Decoder logic provides information about image mapping - memory mapped image - wb_map_in = 0
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IO space mapped image - wb_map_in = 1
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wb_pref_en_in - Prefetch enable signal from currently selected image - used for PCI bus command usage
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wb_addr_in - Address already transalted from WB bus to PCI bus input
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wb_mrl_en_in - Memory read line enable input for each image
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----------------------------------------------------------------------------------------------------------------------*/
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input [4:0] wb_hit_in ; // hit indicators
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input wb_conf_hit_in ; // configuration hit indicator
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input [4:0] wb_pref_en_in ; // prefetch enable from all images
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input [4:0] wb_mrl_en_in ; // Memory Read line command enable from images
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input [4:0] wb_map_in ; // address space mapping indicators - 1 memory space mapping, 0-IO space mapping
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input [31:0] wb_addr_in ; // Translated address input
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/*----------------------------------------------------------------------------------------------------------------------
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Delayed transaction control inputs and outputs:
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Used for locking particular accesses when delayed transactions are in progress:
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wb_del_addr_in - delayed transaction address input - when completion is ready it's used for transaction decoding
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wb_del_be_in - delayed transaction byte enable input - when completion is ready it's used for transaction decoding
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----------------------------------------------------------------------------------------------------------------------*/
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input [31:0] wb_del_addr_in ;
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input [3:0] wb_del_be_in ;
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input [3:0] del_bc_in ; // delayed request bus command used
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input wb_del_req_pending_in ; // delayed request pending indicator
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input wb_del_comp_pending_in ; // delayed completion pending indicator
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input pci_drcomp_pending_in ; // PCI initiated delayed read completion pending
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output [3:0] del_bc_out ; // delayed transaction bus command output
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output del_req_out ; // output for issuing delayed transaction requests
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output del_done_out ; // output indicating current delayed completion finished on WISHBONE bus
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output del_burst_out ; // delayed burst transaction indicator
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output del_in_progress_out ; // delayed in progress indicator - since delayed transaction can be a burst transaction, progress indicator must be used for proper operation
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output del_write_out ; // write enable for delayed transaction - used for indicating that transaction is a write
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input del_write_in ; // indicates that current delayed completion is from a write request
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input del_error_in ; // indicate that delayed request terminated with an error - used for write requests
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input [31:0] ccyc_addr_in ; // configuration cycle address input - it's separate from other addresses, since it is stored separately and decoded for type 0 configuration access
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/*----------------------------------------------------------------------------------------------------------------------
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Configuration space access control and data signals
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wb_conf_offset_out - lower 12 bits of address input provided for register offset
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wb_conf_renable - read enable signal for configuration space accesses
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wb_conf_wenable - write enable signal for configuration space accesses
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wb_conf_be_out - byte enable signals for configuration space accesses
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wb_conf_data_in - data from configuration space
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wb_conf_data_in - data provided for configuration space
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----------------------------------------------------------------------------------------------------------------------*/
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output [11:0] wb_conf_offset_out ; // register offset output
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output wb_conf_renable_out, // configuration read and write enable outputs
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wb_conf_wenable_out ;
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output [3:0] wb_conf_be_out ; // byte enable outputs for configuration space
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input [31:0] wb_conf_data_in ; // configuration data input from configuration space
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output [31:0] wb_conf_data_out ; // configuration data output for configuration space
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/*----------------------------------------------------------------------------------------------------------------------
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Data from WISHBONE bus output to interiror of the core:
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Data output is used for normal and configuration accesses.
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---------------------------------------------------------------------------------------------------------------------*/
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output [31:0] wb_data_out ;
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/*----------------------------------------------------------------------------------------------------------------------
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Bus command - byte enable output - during address phase of image access this bus holds information about PCI
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bus command that should be used, during dataphases ( configuration or image access ) this bus contains inverted
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SEL_I signals
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---------------------------------------------------------------------------------------------------------------------*/
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output [3:0] wb_cbe_out ;
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/*----------------------------------------------------------------------------------------------------------------------
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WBW_FIFO control signals used for sinking data into WBW_FIFO and status monitoring
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---------------------------------------------------------------------------------------------------------------------*/
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output wbw_fifo_wenable_out ; // write enable for WBW_FIFO output
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output [3:0] wbw_fifo_control_out ; // control bus output for WBW_FIFO
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input wbw_fifo_almost_full_in ; // almost full status indicator from WBW_FIFO
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input wbw_fifo_full_in ; // full status indicator from WBW_FIFO
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/*----------------------------------------------------------------------------------------------------------------------
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WBR_FIFO control signals used for fetching data from WBR_FIFO and status monitoring
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---------------------------------------------------------------------------------------------------------------------*/
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output wbr_fifo_renable_out ; // WBR_FIFO read enable output
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input [3:0] wbr_fifo_be_in ; // byte enable input from WBR_FIFO
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input [31:0] wbr_fifo_data_in ; // data input from WBR_FIFO
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input [3:0] wbr_fifo_control_in ; // control bus input from WBR_FIFO
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output wbr_fifo_flush_out ; // flush signal for WBR_FIFO
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input wbr_fifo_almost_empty_in ; // almost empty status indicator from WBR_FIFO
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input wbr_fifo_empty_in ; // empty status indicator from WBR_FIFO
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// used for transaction ordering requirements - WISHBONE read cannot complete until writes from PCI are completed
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input pciw_fifo_empty_in ; // empty status indicator from PCIW_FIFO
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/*----------------------------------------------------------------------------------------------------------------------
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wbs_lock_in - internal signal - when error reporting is enabled and WISHBONE master detects an error while completing
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posted write on PCI, then WISHBONE slave unit doesn't accept any new requests or posted writes. Delayed completions
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are allowed to complete on WISHBONE if all other requirements are satisfied also.
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---------------------------------------------------------------------------------------------------------------------*/
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input wbs_lock_in ;
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/*----------------------------------------------------------------------------------------------------------------------
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WISHBONE bus interface signals - can be connected directly to WISHBONE bus
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---------------------------------------------------------------------------------------------------------------------*/
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input CYC_I ; // cycle indicator
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input STB_I ; // strobe input - input data is valid when strobe and cycle indicator are high
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input WE_I ; // write enable input - 1 - write operation, 0 - read operation
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input [3:0] SEL_I ; // Byte select inputs
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input [31:0] SDATA_I ; // WISHBONE slave interface input data bus
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output [31:0] SDATA_O ; // WISHBONE slave interface output data bus
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output ACK_O ; // Acknowledge output - qualifies valid data on data output bus or received data on data input bus
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output RTY_O ; // retry output - signals to WISHBONE master that cycle should be terminated and retried later
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output ERR_O ; // Signals to WISHBONE master that access resulted in an error
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input CAB_I ; // consecutive address burst input - indicates that master will do a serial address transfer in current cycle
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reg [(`FSM_BITS - 1):0] c_state ; //current state register
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reg [(`FSM_BITS - 1):0] n_state ; //next state input to current state register
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// state machine register control
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always@(posedge wb_clock_in or posedge reset_in)
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begin
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if (reset_in)
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c_state <= #`FF_DELAY S_IDLE ;
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else
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c_state <= #`FF_DELAY n_state ;
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end
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// write operation indicator for delayed transaction requests
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assign del_write_out = WE_I ;
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// variable for bus command multiplexer logic output for delayed requests
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reg [3:0] del_bc ;
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//register for intermediate data and select storage
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reg [35:0] d_incoming ;
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// enable for incoming data register
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reg d_incoming_ena ;
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// incoming data register control logic
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always@(posedge wb_clock_in or posedge reset_in)
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begin
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if (reset_in)
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d_incoming <= #`FF_DELAY {35{1'b0}} ;
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else if (d_incoming_ena)
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d_incoming <= #`FF_DELAY {SEL_I, SDATA_I} ;
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end
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/*===================================================================================================================================================================================
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Write allow for image accesses. Writes through images are allowed when all of following are true:
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- WBW_FIFO musn't be almost full nor full for image writes to be allowed - Every transaction takes at least two locations in the FIFO
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- delayed read from from WISHBONE to PCI request musn't be present
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- delayed read from PCI to WISHBONE completion musn't be present
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- lock input musn't be set - it can be set because of error reporting or because PCI master state machine is disabled
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===================================================================================================================================================================================*/
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wire img_wallow = ~|{ wbw_fifo_almost_full_in , wbw_fifo_full_in, (wb_del_req_pending_in && ~del_write_in) , pci_drcomp_pending_in, wbs_lock_in } ;
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/*===================================================================================================================================================================================
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WISHBONE slave can request an image read accesses when all of following are true:
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- delayed completion is not present
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- delayed request is not present
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- operation is not locked because of error reporting mechanism or because PCI master is disabled
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===================================================================================================================================================================================*/
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wire do_dread_request = ~|{ wb_del_req_pending_in, wb_del_comp_pending_in, wbs_lock_in } ;
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/*===================================================================================================================================================================================
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WISHBONE slave can complete an image read accesses when all of following are true:
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- delayed read completion is present
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- delayed read completion is the same as current read access ( dread_completion_hit is 1 )
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- PCI Write FIFO is empty - no posted write is waiting to be finished in PCIW_FIFO
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- WBR_FIFO empty status is active
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===================================================================================================================================================================================*/
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wire select_and_bc_hit = ( SEL_I == wb_del_be_in ) && ( del_bc == del_bc_in ) ;
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wire dread_completion_hit = ( wb_del_addr_in == wb_addr_in ) && select_and_bc_hit && ~del_write_in ;
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wire do_dread_completion = wb_del_comp_pending_in && pciw_fifo_empty_in && dread_completion_hit && ~wbr_fifo_empty_in ;
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`ifdef GUEST
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// wires indicating allowance for configuration cycle generation requests
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wire do_ccyc_req = 1'b0 ;
|
319 |
|
|
wire do_ccyc_comp = 1'b0 ;
|
320 |
|
|
|
321 |
|
|
// wires indicating allowance for interrupt acknowledge cycle generation requests
|
322 |
|
|
wire do_iack_req = 1'b0 ;
|
323 |
|
|
wire do_iack_comp = 1'b0 ;
|
324 |
|
|
|
325 |
|
|
// variables for configuration access control signals
|
326 |
|
|
reg conf_wenable ;
|
327 |
|
|
assign wb_conf_wenable_out = 1'b0 ;
|
328 |
|
|
|
329 |
|
|
// configuration cycle data register hit
|
330 |
|
|
wire ccyc_hit = 1'b0 ;
|
331 |
|
|
wire iack_hit = 1'b0 ;
|
332 |
|
|
|
333 |
|
|
`else
|
334 |
|
|
`ifdef HOST
|
335 |
|
|
// only host implementation has access for generating interrupt acknowledge and configuration cycles
|
336 |
|
|
|
337 |
|
|
// wires indicating allowance for configuration cycle generation requests
|
338 |
|
|
wire do_ccyc_req = ~|{ wb_del_comp_pending_in, wb_del_req_pending_in, wbs_lock_in } ;
|
339 |
|
|
wire do_ccyc_comp = wb_del_comp_pending_in && select_and_bc_hit && ((pciw_fifo_empty_in && ~del_write_in && ~wbr_fifo_empty_in) || del_write_in) ;
|
340 |
|
|
|
341 |
|
|
// wires indicating allowance for interrupt acknowledge cycle generation requests
|
342 |
|
|
wire do_iack_req = ~|{ wb_del_comp_pending_in, wb_del_req_pending_in, wbs_lock_in } ;
|
343 |
|
|
wire do_iack_comp = wb_del_comp_pending_in && select_and_bc_hit && pciw_fifo_empty_in && ~del_write_in && ~wbr_fifo_empty_in;
|
344 |
|
|
|
345 |
|
|
// variables for configuration access control signals
|
346 |
|
|
reg conf_wenable ;
|
347 |
|
|
assign wb_conf_wenable_out = conf_wenable ;
|
348 |
|
|
|
349 |
|
|
// configuration cycle data register hit
|
350 |
|
|
wire ccyc_hit = ({wb_addr_in[11:2], 2'b00} == `CNF_DATA_ADDR) ;
|
351 |
|
|
wire iack_hit = ({wb_addr_in[11:2], 2'b00} == `INT_ACK_ADDR) ;
|
352 |
|
|
`endif
|
353 |
|
|
`endif
|
354 |
|
|
|
355 |
|
|
// configuration read enable - supplied for host and guest bridges
|
356 |
|
|
reg conf_renable ;
|
357 |
|
|
assign wb_conf_renable_out = conf_renable ;
|
358 |
|
|
|
359 |
|
|
// wire for write attempt - 1 when external WB master is attempting a write
|
360 |
|
|
wire wattempt = ( CYC_I && STB_I && WE_I ) ; // write is qualified when cycle, strobe and write enable inputs are all high
|
361 |
|
|
|
362 |
|
|
// wire for read attempt - 1 when external WB master is attempting a read
|
363 |
|
|
wire rattempt = ( CYC_I && STB_I && ~WE_I ) ; // read is qualified when cycle and strobe are high and write enable is low
|
364 |
|
|
|
365 |
|
|
// burst access indicator
|
366 |
|
|
wire burst_transfer = CYC_I && CAB_I ;
|
367 |
|
|
|
368 |
|
|
// address allignement indicator
|
369 |
|
|
wire alligned_address = wb_addr_in[1:0] == 2'b00 ;
|
370 |
|
|
|
371 |
|
|
// SEL_I error indicator for IO and configuration accesses - select lines must be alligned with address
|
372 |
|
|
reg sel_error ;
|
373 |
|
|
always@(wb_addr_in or SEL_I)
|
374 |
|
|
begin
|
375 |
|
|
case (wb_addr_in[1:0])
|
376 |
|
|
2'b00: sel_error <= ~SEL_I[0] ; // select 0 must be 1, all others are don't cares.
|
377 |
|
|
2'b01: sel_error <= ~SEL_I[1] || SEL_I[0] ; // byte 0 can't be selected, byte 1 must be selected
|
378 |
|
|
2'b10: sel_error <= ~SEL_I[2] || SEL_I[1] || SEL_I[0] ; // bytes 0 and 1 can't be selected, byte 2 must be selected
|
379 |
|
|
2'b11: sel_error <= ~SEL_I[3] || SEL_I[2] || SEL_I[1] || SEL_I[0] ; // bytes 0, 1 and 2 can't be selected, byte 3 must be selected
|
380 |
|
|
endcase
|
381 |
|
|
end
|
382 |
|
|
|
383 |
|
|
// WBW_FIFO control output
|
384 |
|
|
reg [3:0] wbw_fifo_control ;
|
385 |
|
|
assign wbw_fifo_control_out = wbw_fifo_control ; //control bus output for WBW_FIFO
|
386 |
|
|
|
387 |
|
|
// WBW_FIFO wenable output assignment
|
388 |
|
|
reg wbw_fifo_wenable ;
|
389 |
|
|
assign wbw_fifo_wenable_out = wbw_fifo_wenable ; //write enable for WBW_FIFO
|
390 |
|
|
|
391 |
|
|
// WBR_FIFO control outputs
|
392 |
|
|
reg wbr_fifo_flush, wbr_fifo_renable ; // flush and read enable outputs
|
393 |
|
|
assign wbr_fifo_renable_out = wbr_fifo_renable ; //read enable for wbr_fifo
|
394 |
|
|
assign wbr_fifo_flush_out = wbr_fifo_flush ; // flush for wbr_fifo
|
395 |
|
|
|
396 |
|
|
// delayed transaction request control signals
|
397 |
|
|
reg del_req, del_done ;
|
398 |
|
|
assign del_req_out = del_req ; // read request
|
399 |
|
|
assign del_done_out = del_done ; // read done
|
400 |
|
|
|
401 |
|
|
// WISHBONE handshaking control outputs
|
402 |
|
|
reg ack, rty, err ;
|
403 |
|
|
assign ACK_O = ack ;
|
404 |
|
|
assign RTY_O = rty ;
|
405 |
|
|
assign ERR_O = err ;
|
406 |
|
|
|
407 |
|
|
/*----------------------------------------------------------------------------------------------------------------------
|
408 |
|
|
Control logic for image hits
|
409 |
|
|
img_hit - state of wb_hit_in bus when first data is acknowledged
|
410 |
|
|
same_hit - comparator output that compares first data phase's wb_hit_input and current wb_hit_input
|
411 |
|
|
---------------------------------------------------------------------------------------------------------------------*/
|
412 |
|
|
reg [4:0] img_hit ;
|
413 |
|
|
|
414 |
|
|
wire hit_latch_en = ( c_state == S_IDLE ) && ack ;
|
415 |
|
|
|
416 |
|
|
always@(posedge wb_clock_in or posedge reset_in)
|
417 |
|
|
begin
|
418 |
|
|
if (reset_in)
|
419 |
|
|
img_hit <= #`FF_DELAY 5'h00 ;
|
420 |
|
|
else
|
421 |
|
|
if (hit_latch_en)
|
422 |
|
|
img_hit <= #`FF_DELAY wb_hit_in ;
|
423 |
|
|
end
|
424 |
|
|
|
425 |
|
|
wire same_hit = ( img_hit == wb_hit_in ) ;
|
426 |
|
|
|
427 |
|
|
/*----------------------------------------------------------------------------------------------------------------------
|
428 |
|
|
Control logic for image control signals
|
429 |
|
|
pref_en - prefetch enable of currently selected image
|
430 |
|
|
mrl_en - Memory read line enable of currently selected image
|
431 |
|
|
map - Address space mapping for currently selected image
|
432 |
|
|
---------------------------------------------------------------------------------------------------------------------*/
|
433 |
|
|
reg pref_en, mrl_en, map ;
|
434 |
|
|
|
435 |
|
|
// hit error indicator
|
436 |
|
|
reg hit_error ;
|
437 |
|
|
|
438 |
|
|
always@(wb_hit_in or wb_pref_en_in or wb_mrl_en_in or wb_map_in)
|
439 |
|
|
begin
|
440 |
|
|
case (wb_hit_in)
|
441 |
|
|
5'h01: begin
|
442 |
|
|
pref_en <= wb_pref_en_in[0] ;
|
443 |
|
|
mrl_en <= wb_mrl_en_in[0] ;
|
444 |
|
|
map <= wb_map_in[0] ;
|
445 |
|
|
hit_error <= 1'b0 ;
|
446 |
|
|
end
|
447 |
|
|
|
448 |
|
|
5'h02: begin
|
449 |
|
|
pref_en <= wb_pref_en_in[1] ;
|
450 |
|
|
mrl_en <= wb_mrl_en_in[1] ;
|
451 |
|
|
map <= wb_map_in[1] ;
|
452 |
|
|
hit_error <= 1'b0 ;
|
453 |
|
|
end
|
454 |
|
|
|
455 |
|
|
5'h04: begin
|
456 |
|
|
pref_en <= wb_pref_en_in[2] ;
|
457 |
|
|
mrl_en <= wb_mrl_en_in[2] ;
|
458 |
|
|
map <= wb_map_in[2] ;
|
459 |
|
|
hit_error <= 1'b0 ;
|
460 |
|
|
end
|
461 |
|
|
|
462 |
|
|
5'h08: begin
|
463 |
|
|
pref_en <= wb_pref_en_in[3] ;
|
464 |
|
|
mrl_en <= wb_mrl_en_in[3] ;
|
465 |
|
|
map <= wb_map_in[3] ;
|
466 |
|
|
hit_error <= 1'b0 ;
|
467 |
|
|
end
|
468 |
|
|
|
469 |
|
|
5'h10: begin
|
470 |
|
|
pref_en <= wb_pref_en_in[4] ;
|
471 |
|
|
mrl_en <= wb_mrl_en_in[4] ;
|
472 |
|
|
map <= wb_map_in[4] ;
|
473 |
|
|
hit_error <= 1'b0 ;
|
474 |
|
|
end
|
475 |
|
|
|
476 |
|
|
default:begin
|
477 |
|
|
pref_en <= 1'b0 ;
|
478 |
|
|
mrl_en <= 1'b0 ;
|
479 |
|
|
map <= 1'b0 ;
|
480 |
|
|
hit_error <= |(wb_hit_in) ;
|
481 |
|
|
end
|
482 |
|
|
endcase
|
483 |
|
|
end
|
484 |
|
|
|
485 |
|
|
assign del_burst_out = CAB_I && pref_en && ~WE_I; // delayed burst indicator - only when WB master attempts CAB transfer and prefetch enable of corresponding image is set -
|
486 |
|
|
// applies for reads only - delayed write cannot be a burst
|
487 |
|
|
|
488 |
|
|
/*----------------------------------------------------------------------------------------------------------------------
|
489 |
|
|
Delayed transaction bus command generation
|
490 |
|
|
Bus command for delayed reads depends on image's address space mapping and control bits and
|
491 |
|
|
whether or not these are interrupt acknowledge requests or configuration cycle requests
|
492 |
|
|
---------------------------------------------------------------------------------------------------------------------*/
|
493 |
|
|
assign del_bc_out = del_bc ;
|
494 |
|
|
|
495 |
|
|
always@(map or CAB_I or mrl_en or pref_en or iack_hit or ccyc_hit or WE_I or wb_conf_hit_in)
|
496 |
|
|
begin
|
497 |
|
|
`ifdef HOST
|
498 |
|
|
if (wb_conf_hit_in)
|
499 |
|
|
begin
|
500 |
|
|
if (iack_hit)
|
501 |
|
|
begin
|
502 |
|
|
del_bc <= `BC_IACK ;
|
503 |
|
|
end
|
504 |
|
|
else
|
505 |
|
|
begin
|
506 |
|
|
if (WE_I)
|
507 |
|
|
del_bc <= `BC_CONF_WRITE ;
|
508 |
|
|
else
|
509 |
|
|
del_bc <= `BC_CONF_READ ;
|
510 |
|
|
end
|
511 |
|
|
end
|
512 |
|
|
else
|
513 |
|
|
`endif
|
514 |
|
|
begin
|
515 |
|
|
if (map) // map = 1 - IO space
|
516 |
|
|
begin
|
517 |
|
|
del_bc <= `BC_IO_READ ;
|
518 |
|
|
end
|
519 |
|
|
else
|
520 |
|
|
if ( CAB_I && mrl_en && pref_en) // burst and memory read line enable
|
521 |
|
|
begin
|
522 |
|
|
del_bc <= `BC_MEM_READ_LN ;
|
523 |
|
|
end
|
524 |
|
|
else // normal single memory access
|
525 |
|
|
begin
|
526 |
|
|
del_bc <= `BC_MEM_READ ;
|
527 |
|
|
end
|
528 |
|
|
end
|
529 |
|
|
end
|
530 |
|
|
|
531 |
|
|
// WISHBONE data output select lines for output multiplexor
|
532 |
|
|
reg sdata_o_sel ;
|
533 |
|
|
|
534 |
|
|
reg del_in_progress_out ; // state machine indicates whether current read completion is in progress on WISHBONE bus
|
535 |
|
|
|
536 |
|
|
// state machine logic
|
537 |
|
|
always@(
|
538 |
|
|
c_state or
|
539 |
|
|
wattempt or
|
540 |
|
|
img_wallow or
|
541 |
|
|
burst_transfer or
|
542 |
|
|
wb_hit_in or
|
543 |
|
|
map or
|
544 |
|
|
same_hit or
|
545 |
|
|
alligned_address or
|
546 |
|
|
rattempt or
|
547 |
|
|
do_dread_request or
|
548 |
|
|
do_dread_completion or
|
549 |
|
|
wbr_fifo_almost_empty_in or
|
550 |
|
|
wbr_fifo_control_in or
|
551 |
|
|
wb_conf_hit_in or
|
552 |
|
|
sel_error or
|
553 |
|
|
do_ccyc_req or
|
554 |
|
|
do_ccyc_comp or
|
555 |
|
|
ccyc_hit or
|
556 |
|
|
del_write_in or
|
557 |
|
|
del_error_in or
|
558 |
|
|
do_iack_req or
|
559 |
|
|
do_iack_comp or
|
560 |
|
|
iack_hit or
|
561 |
|
|
hit_error
|
562 |
|
|
)
|
563 |
|
|
begin
|
564 |
|
|
case (c_state)
|
565 |
|
|
S_IDLE:begin
|
566 |
|
|
if (wattempt)
|
567 |
|
|
begin
|
568 |
|
|
// read signals in inactive state when writes are in progress
|
569 |
|
|
wbr_fifo_flush <= 1'b0 ;
|
570 |
|
|
wbr_fifo_renable <= 1'b0 ;
|
571 |
|
|
|
572 |
|
|
// configuration read enable control signal inactive
|
573 |
|
|
conf_renable <= 1'b0 ;
|
574 |
|
|
|
575 |
|
|
// WISHBONE data output selection - since this is a write, hold wbr output
|
576 |
|
|
sdata_o_sel <= WBR_SEL ;
|
577 |
|
|
|
578 |
|
|
// read cannot be in progress while write is attempted
|
579 |
|
|
del_in_progress_out <= 1'b0 ;
|
580 |
|
|
|
581 |
|
|
// delayed request signals inactive
|
582 |
|
|
del_req <= 1'b0 ;
|
583 |
|
|
del_done <= 1'b0 ;
|
584 |
|
|
|
585 |
|
|
// configuration access control signals inactive
|
586 |
|
|
conf_wenable <= 1'b0 ;
|
587 |
|
|
conf_renable <= 1'b0 ;
|
588 |
|
|
|
589 |
|
|
if(wb_hit_in)
|
590 |
|
|
begin
|
591 |
|
|
|
592 |
|
|
// check error conditions for image writes
|
593 |
|
|
if (
|
594 |
|
|
(map && (burst_transfer || sel_error)) || // IO write is a burst or has wrong select lines active= Error
|
595 |
|
|
(~map && ~alligned_address) || // Mem write to nonaligned address = error
|
596 |
|
|
hit_error // images overlaping - error
|
597 |
|
|
)
|
598 |
|
|
begin
|
599 |
|
|
n_state <= S_IDLE ; // stay in idle state because of an error condition
|
600 |
|
|
|
601 |
|
|
// respond with an error
|
602 |
|
|
ack <= 1'b0 ;
|
603 |
|
|
rty <= 1'b0 ;
|
604 |
|
|
err <= 1'b1 ;
|
605 |
|
|
|
606 |
|
|
// write signals in inactive state
|
607 |
|
|
wbw_fifo_control <= `ADDRESS ;
|
608 |
|
|
wbw_fifo_wenable <= 1'b0 ;
|
609 |
|
|
d_incoming_ena <= 1'b0 ;
|
610 |
|
|
|
611 |
|
|
end // error conditions
|
612 |
|
|
else
|
613 |
|
|
// check for retry conditions for image writes
|
614 |
|
|
if ( ~img_wallow ) // write to image not allowed at this time = retry
|
615 |
|
|
begin
|
616 |
|
|
n_state <= S_IDLE ; // stay in IDLE
|
617 |
|
|
|
618 |
|
|
// respond with a retry
|
619 |
|
|
ack <= 1'b0 ;
|
620 |
|
|
rty <= 1'b1 ;
|
621 |
|
|
err <= 1'b0 ;
|
622 |
|
|
|
623 |
|
|
// write signals in inactive state
|
624 |
|
|
wbw_fifo_control <= `ADDRESS ;
|
625 |
|
|
wbw_fifo_wenable <= 1'b0 ;
|
626 |
|
|
d_incoming_ena <= 1'b0 ;
|
627 |
|
|
|
628 |
|
|
end //retry
|
629 |
|
|
else // everything OK - proceed
|
630 |
|
|
begin
|
631 |
|
|
n_state <= S_W_ADDR_DATA ; // goto write transfer state
|
632 |
|
|
|
633 |
|
|
// respond with acknowledge
|
634 |
|
|
ack <= 1'b1 ;
|
635 |
|
|
rty <= 1'b0 ;
|
636 |
|
|
err <= 1'b0 ;
|
637 |
|
|
|
638 |
|
|
// write control signals
|
639 |
|
|
// fifo is enabled - address is written to it with appropriate control encoding
|
640 |
|
|
wbw_fifo_control <= `ADDRESS ;
|
641 |
|
|
wbw_fifo_wenable <= 1'b1 ;
|
642 |
|
|
// data is latched to data incoming intermidiate stage - it will be put in FIFO later
|
643 |
|
|
d_incoming_ena <= 1'b1 ;
|
644 |
|
|
|
645 |
|
|
end // image write OK
|
646 |
|
|
end //wb_hit_in
|
647 |
|
|
else // no image hit
|
648 |
|
|
|
649 |
|
|
if (wb_conf_hit_in) // configuration space hit
|
650 |
|
|
begin
|
651 |
|
|
// image write control signals inactive - give outputs one clock cycle setup time
|
652 |
|
|
n_state <= S_CONF_WRITE ; // go to conf. write state
|
653 |
|
|
|
654 |
|
|
// don't respond yet
|
655 |
|
|
ack <= 1'b0 ;
|
656 |
|
|
rty <= 1'b0 ;
|
657 |
|
|
err <= 1'b0 ;
|
658 |
|
|
|
659 |
|
|
// write signals in inactive state
|
660 |
|
|
wbw_fifo_control <= `ADDRESS ;
|
661 |
|
|
wbw_fifo_wenable <= 1'b0 ;
|
662 |
|
|
d_incoming_ena <= 1'b0 ;
|
663 |
|
|
|
664 |
|
|
end // wb_conf_hit_in*/
|
665 |
|
|
else
|
666 |
|
|
begin // no hit
|
667 |
|
|
n_state <= S_IDLE ; // stay in IDLE
|
668 |
|
|
|
669 |
|
|
// don't respond
|
670 |
|
|
ack <= 1'b0 ;
|
671 |
|
|
rty <= 1'b0 ;
|
672 |
|
|
err <= 1'b0 ;
|
673 |
|
|
|
674 |
|
|
// write signals in inactive state
|
675 |
|
|
wbw_fifo_control <= `ADDRESS ;
|
676 |
|
|
wbw_fifo_wenable <= 1'b0 ;
|
677 |
|
|
d_incoming_ena <= 1'b0 ;
|
678 |
|
|
|
679 |
|
|
end // no hit
|
680 |
|
|
end //wattempt
|
681 |
|
|
else
|
682 |
|
|
if (rattempt)
|
683 |
|
|
begin
|
684 |
|
|
// write signals in inactive state
|
685 |
|
|
wbw_fifo_control <= `ADDRESS ;
|
686 |
|
|
wbw_fifo_wenable <= 1'b0 ;
|
687 |
|
|
d_incoming_ena <= 1'b0 ;
|
688 |
|
|
|
689 |
|
|
// configuration access signals inactive
|
690 |
|
|
conf_wenable <= 1'b0 ;
|
691 |
|
|
conf_renable <= 1'b0 ;
|
692 |
|
|
|
693 |
|
|
if(wb_hit_in)
|
694 |
|
|
begin
|
695 |
|
|
// WISHBONE data output selection - drive wbr_output
|
696 |
|
|
sdata_o_sel <= WBR_SEL ;
|
697 |
|
|
|
698 |
|
|
// check error conditions for image reads
|
699 |
|
|
if (
|
700 |
|
|
(map && (burst_transfer || sel_error)) || // IO read is a burst or has wrong select lines active= Error
|
701 |
|
|
(~map && ~alligned_address) || // Mem read from nonaligned address = error
|
702 |
|
|
hit_error // images overlaping - error
|
703 |
|
|
)
|
704 |
|
|
begin
|
705 |
|
|
n_state <= S_IDLE ; // stay in idle because of an error
|
706 |
|
|
|
707 |
|
|
// respond with error
|
708 |
|
|
ack <= 1'b0 ;
|
709 |
|
|
rty <= 1'b0 ;
|
710 |
|
|
err <= 1'b1 ;
|
711 |
|
|
|
712 |
|
|
// read controls inactive
|
713 |
|
|
wbr_fifo_flush <= 1'b0 ;
|
714 |
|
|
wbr_fifo_renable <= 1'b0 ;
|
715 |
|
|
del_req <= 1'b0 ;
|
716 |
|
|
del_done <= 1'b0 ;
|
717 |
|
|
|
718 |
|
|
// read is not in progress
|
719 |
|
|
del_in_progress_out <= 1'b0 ;
|
720 |
|
|
|
721 |
|
|
end // error conditions
|
722 |
|
|
else
|
723 |
|
|
|
724 |
|
|
// check for retry conditions for image reads
|
725 |
|
|
if ( ~do_dread_request && ~do_dread_completion) // read through image not allowed at this time = retry
|
726 |
|
|
begin
|
727 |
|
|
n_state <= S_IDLE ; // stay in idle state
|
728 |
|
|
|
729 |
|
|
// respond with retry
|
730 |
|
|
ack <= 1'b0 ;
|
731 |
|
|
rty <= 1'b1 ;
|
732 |
|
|
err <= 1'b0 ;
|
733 |
|
|
|
734 |
|
|
// read controls inactive
|
735 |
|
|
wbr_fifo_flush <= 1'b0 ;
|
736 |
|
|
wbr_fifo_renable <= 1'b0 ;
|
737 |
|
|
del_req <= 1'b0 ;
|
738 |
|
|
del_done <= 1'b0 ;
|
739 |
|
|
|
740 |
|
|
// read is not in progress
|
741 |
|
|
del_in_progress_out <= 1'b0 ;
|
742 |
|
|
|
743 |
|
|
end //retry
|
744 |
|
|
else
|
745 |
|
|
if ( do_dread_request ) // read request can be accepted
|
746 |
|
|
begin
|
747 |
|
|
n_state <= S_IDLE ; // stay in IDLE
|
748 |
|
|
|
749 |
|
|
// respond with retry
|
750 |
|
|
ack <= 1'b0 ;
|
751 |
|
|
rty <= 1'b1 ;
|
752 |
|
|
err <= 1'b0 ;
|
753 |
|
|
|
754 |
|
|
// FIFO signals inactive
|
755 |
|
|
wbr_fifo_flush <= 1'b0 ;
|
756 |
|
|
wbr_fifo_renable <= 1'b0 ;
|
757 |
|
|
|
758 |
|
|
// signal read request
|
759 |
|
|
del_req <= 1'b1 ;
|
760 |
|
|
del_done <= 1'b0 ;
|
761 |
|
|
|
762 |
|
|
// read is not in progress
|
763 |
|
|
del_in_progress_out <= 1'b0 ;
|
764 |
|
|
|
765 |
|
|
end //do_dread_request
|
766 |
|
|
else // do_dread_completion
|
767 |
|
|
begin
|
768 |
|
|
// check if data is error message
|
769 |
|
|
if (wbr_fifo_control_in == `DATA_ERROR)
|
770 |
|
|
begin
|
771 |
|
|
n_state <= S_IDLE ; // stay in idle state
|
772 |
|
|
|
773 |
|
|
// respond with error
|
774 |
|
|
ack <= 1'b0 ;
|
775 |
|
|
rty <= 1'b0 ;
|
776 |
|
|
err <= 1'b1 ;
|
777 |
|
|
|
778 |
|
|
// read from FIFO to free up location that error is taking up
|
779 |
|
|
wbr_fifo_flush <= 1'b0 ;
|
780 |
|
|
wbr_fifo_renable <= 1'b1 ;
|
781 |
|
|
|
782 |
|
|
// respond that read is finished
|
783 |
|
|
del_req <= 1'b0 ;
|
784 |
|
|
del_done <= 1'b1 ;
|
785 |
|
|
|
786 |
|
|
// read is in progress nevertheless it was terminated with an error
|
787 |
|
|
del_in_progress_out <= 1'b1 ;
|
788 |
|
|
|
789 |
|
|
end // DATA_ERROR
|
790 |
|
|
else
|
791 |
|
|
if (wbr_fifo_almost_empty_in)
|
792 |
|
|
begin
|
793 |
|
|
// only one location is in the FIFO - acknowledge the transfer and stay in this state
|
794 |
|
|
n_state <= S_IDLE ; // stay in idle state
|
795 |
|
|
|
796 |
|
|
// respond with acknowledge
|
797 |
|
|
ack <= 1'b1 ;
|
798 |
|
|
rty <= 1'b0 ;
|
799 |
|
|
err <= 1'b0 ;
|
800 |
|
|
|
801 |
|
|
// read from FIFO
|
802 |
|
|
wbr_fifo_flush <= 1'b0 ;
|
803 |
|
|
wbr_fifo_renable <= 1'b1 ;
|
804 |
|
|
|
805 |
|
|
// respond that read is finished
|
806 |
|
|
del_req <= 1'b0 ;
|
807 |
|
|
del_done <= 1'b1 ;
|
808 |
|
|
|
809 |
|
|
// read is in progress
|
810 |
|
|
del_in_progress_out <= 1'b1 ;
|
811 |
|
|
end
|
812 |
|
|
else
|
813 |
|
|
begin
|
814 |
|
|
n_state <= S_READ ; // go to read state
|
815 |
|
|
|
816 |
|
|
// respond with acknowledge since data output from FIFO is always prepared
|
817 |
|
|
ack <= 1'b1 ;
|
818 |
|
|
rty <= 1'b0 ;
|
819 |
|
|
err <= 1'b0 ;
|
820 |
|
|
|
821 |
|
|
// enable read from FIFO - on posedge of clock new data will be provided
|
822 |
|
|
wbr_fifo_flush <= 1'b0 ;
|
823 |
|
|
wbr_fifo_renable <= 1'b1 ;
|
824 |
|
|
del_req <= 1'b0 ;
|
825 |
|
|
del_done <= 1'b0 ;
|
826 |
|
|
|
827 |
|
|
// read is in progress
|
828 |
|
|
del_in_progress_out <= 1'b1 ;
|
829 |
|
|
|
830 |
|
|
end // no DATA_ERROR
|
831 |
|
|
|
832 |
|
|
end // do_dread_completion
|
833 |
|
|
end //wb_hit_in
|
834 |
|
|
else //~wb_hit
|
835 |
|
|
if(wb_conf_hit_in) // read from configuration space
|
836 |
|
|
begin
|
837 |
|
|
n_state <= S_CONF_READ ; // go to configuration space read state - give outputs one clock cycle for setup
|
838 |
|
|
|
839 |
|
|
// image read signals inactive
|
840 |
|
|
wbr_fifo_flush <= 1'b0 ;
|
841 |
|
|
wbr_fifo_renable <= 1'b0 ;
|
842 |
|
|
del_req <= 1'b0 ;
|
843 |
|
|
del_done <= 1'b0 ;
|
844 |
|
|
|
845 |
|
|
// do not respond yet
|
846 |
|
|
ack <= 1'b0 ;
|
847 |
|
|
rty <= 1'b0 ;
|
848 |
|
|
err <= 1'b0 ;
|
849 |
|
|
|
850 |
|
|
// WISHBONE data output selection - drive configuration space output
|
851 |
|
|
sdata_o_sel <= CONF_SEL ;
|
852 |
|
|
|
853 |
|
|
// read is not in progress since this is configuration read
|
854 |
|
|
del_in_progress_out <= 1'b0 ;
|
855 |
|
|
|
856 |
|
|
end //read from configuration space
|
857 |
|
|
|
858 |
|
|
else // no hit
|
859 |
|
|
|
860 |
|
|
begin
|
861 |
|
|
n_state <= S_IDLE ;
|
862 |
|
|
wbr_fifo_flush <= 1'b0 ;
|
863 |
|
|
wbr_fifo_renable <= 1'b0 ;
|
864 |
|
|
del_req <= 1'b0 ;
|
865 |
|
|
del_done <= 1'b0 ;
|
866 |
|
|
ack <= 1'b0 ;
|
867 |
|
|
rty <= 1'b0 ;
|
868 |
|
|
err <= 1'b0 ;
|
869 |
|
|
|
870 |
|
|
// WISHBONE data output selection - drive wbr_output
|
871 |
|
|
sdata_o_sel <= WBR_SEL ;
|
872 |
|
|
|
873 |
|
|
// read is not in progress since there is no image hit
|
874 |
|
|
del_in_progress_out <= 1'b0 ;
|
875 |
|
|
|
876 |
|
|
end // no hit
|
877 |
|
|
end //if (rattempt)
|
878 |
|
|
else // no write and no read attempt - do nothing
|
879 |
|
|
begin
|
880 |
|
|
n_state <= S_IDLE ;
|
881 |
|
|
|
882 |
|
|
// write signals - all in inactive state
|
883 |
|
|
wbw_fifo_control <= `ADDRESS ;
|
884 |
|
|
wbw_fifo_wenable <= 1'b0 ;
|
885 |
|
|
d_incoming_ena <= 1'b0 ;
|
886 |
|
|
|
887 |
|
|
// handshaking signals inactive
|
888 |
|
|
ack <= 1'b0 ;
|
889 |
|
|
rty <= 1'b0 ;
|
890 |
|
|
err <= 1'b0 ;
|
891 |
|
|
|
892 |
|
|
// read signals inactive
|
893 |
|
|
wbr_fifo_flush <= 1'b0 ;
|
894 |
|
|
wbr_fifo_renable <= 1'b0 ;
|
895 |
|
|
del_req <= 1'b0 ;
|
896 |
|
|
del_done <= 1'b0 ;
|
897 |
|
|
|
898 |
|
|
// configuration space control signals inactive
|
899 |
|
|
conf_wenable <= 1'b0 ;
|
900 |
|
|
conf_renable <= 1'b0 ;
|
901 |
|
|
|
902 |
|
|
// WISHBONE data output selection - drive wbr_output
|
903 |
|
|
sdata_o_sel <= WBR_SEL ;
|
904 |
|
|
|
905 |
|
|
// read is not in progress
|
906 |
|
|
del_in_progress_out <= 1'b0 ;
|
907 |
|
|
|
908 |
|
|
end //no write and no read attempt
|
909 |
|
|
end //`S_IDLE
|
910 |
|
|
S_W_ADDR_DATA: begin
|
911 |
|
|
// read signals inactive
|
912 |
|
|
wbr_fifo_flush <= 1'b0 ;
|
913 |
|
|
wbr_fifo_renable <= 1'b0 ;
|
914 |
|
|
del_req <= 1'b0 ;
|
915 |
|
|
del_done <= 1'b0 ;
|
916 |
|
|
|
917 |
|
|
// configuration space control signals inactive
|
918 |
|
|
conf_wenable <= 1'b0 ;
|
919 |
|
|
conf_renable <= 1'b0 ;
|
920 |
|
|
|
921 |
|
|
// WISHBONE data output selection - drive wbr_output
|
922 |
|
|
sdata_o_sel <= WBR_SEL ;
|
923 |
|
|
|
924 |
|
|
// delayed transaction is not in progress when receiving posted burst write
|
925 |
|
|
del_in_progress_out <= 1'b0 ;
|
926 |
|
|
|
927 |
|
|
if (burst_transfer)
|
928 |
|
|
if (wattempt)
|
929 |
|
|
begin
|
930 |
|
|
// check for error conditions
|
931 |
|
|
if ( ~same_hit || // burst transfer crossed image range
|
932 |
|
|
~alligned_address ) // address is not alligned
|
933 |
|
|
begin
|
934 |
|
|
n_state <= S_TURN_ARROUND ; // goto turn-arround state
|
935 |
|
|
|
936 |
|
|
// respond with an error
|
937 |
|
|
ack <= 1'b0 ;
|
938 |
|
|
rty <= 1'b0 ;
|
939 |
|
|
err <= 1'b1 ;
|
940 |
|
|
|
941 |
|
|
// write data latched in itermediate register and tag it as last
|
942 |
|
|
wbw_fifo_control <= `LAST ;
|
943 |
|
|
wbw_fifo_wenable <= 1'b1 ;
|
944 |
|
|
d_incoming_ena <= 1'b0 ;
|
945 |
|
|
|
946 |
|
|
end // error
|
947 |
|
|
else //no error
|
948 |
|
|
// check for retry condition
|
949 |
|
|
if (~img_wallow)
|
950 |
|
|
begin
|
951 |
|
|
n_state <= S_TURN_ARROUND ; // FIFO was filled or error lock occurred - goto turnarround state
|
952 |
|
|
|
953 |
|
|
// respond with retry
|
954 |
|
|
ack <= 1'b0 ;
|
955 |
|
|
rty <= 1'b1 ;
|
956 |
|
|
err <= 1'b0 ;
|
957 |
|
|
|
958 |
|
|
// write last data latched in intermediate register
|
959 |
|
|
wbw_fifo_control <= `LAST ;
|
960 |
|
|
wbw_fifo_wenable <= 1'b1 ;
|
961 |
|
|
d_incoming_ena <= 1'b0 ;
|
962 |
|
|
|
963 |
|
|
end // retry
|
964 |
|
|
else // no error and no retry - acknowledge
|
965 |
|
|
begin
|
966 |
|
|
n_state <= S_W_ADDR_DATA ; // stay in current state
|
967 |
|
|
|
968 |
|
|
// respond with acknowledge
|
969 |
|
|
ack <= 1'b1 ;
|
970 |
|
|
rty <= 1'b0 ;
|
971 |
|
|
err <= 1'b0 ;
|
972 |
|
|
|
973 |
|
|
// write data from intermediate register to fifo and latch new data provided
|
974 |
|
|
wbw_fifo_control <= `DATA ;
|
975 |
|
|
wbw_fifo_wenable <= 1'b1 ;
|
976 |
|
|
d_incoming_ena <= 1'b1 ;
|
977 |
|
|
|
978 |
|
|
end // no error and no retry - acknowledge
|
979 |
|
|
end // wattempt
|
980 |
|
|
else // no write attempt
|
981 |
|
|
begin
|
982 |
|
|
n_state <= S_W_ADDR_DATA ; // master is inserting WS - stay in current state
|
983 |
|
|
|
984 |
|
|
// response signals inactive
|
985 |
|
|
ack <= 1'b0 ;
|
986 |
|
|
rty <= 1'b0 ;
|
987 |
|
|
err <= 1'b0 ;
|
988 |
|
|
|
989 |
|
|
//write signals inactive
|
990 |
|
|
wbw_fifo_control <= `DATA ;
|
991 |
|
|
wbw_fifo_wenable <= 1'b0 ;
|
992 |
|
|
d_incoming_ena <= 1'b0 ;
|
993 |
|
|
|
994 |
|
|
end // no write attempt
|
995 |
|
|
else // ~burst transfer
|
996 |
|
|
begin
|
997 |
|
|
n_state <= S_TURN_ARROUND ; // no burst transfer - go back to idle
|
998 |
|
|
|
999 |
|
|
// do not respond
|
1000 |
|
|
ack <= 1'b0 ;
|
1001 |
|
|
rty <= 1'b0 ;
|
1002 |
|
|
err <= 1'b0 ;
|
1003 |
|
|
|
1004 |
|
|
// write last data to FIFO and don't latch new data
|
1005 |
|
|
wbw_fifo_control <= `LAST ;
|
1006 |
|
|
wbw_fifo_wenable <= 1'b1 ;
|
1007 |
|
|
d_incoming_ena <= 1'b0 ;
|
1008 |
|
|
|
1009 |
|
|
end // burst_transfer
|
1010 |
|
|
end // S_W_ADDR_DATA
|
1011 |
|
|
|
1012 |
|
|
S_READ:begin
|
1013 |
|
|
// write signals in inactive state
|
1014 |
|
|
wbw_fifo_control <= `ADDRESS ;
|
1015 |
|
|
wbw_fifo_wenable <= 1'b0 ;
|
1016 |
|
|
d_incoming_ena <= 1'b0 ;
|
1017 |
|
|
|
1018 |
|
|
// configuration space control signals inactive
|
1019 |
|
|
conf_wenable <= 1'b0 ;
|
1020 |
|
|
conf_renable <= 1'b0 ;
|
1021 |
|
|
|
1022 |
|
|
// WISHBONE data output selection - drive wbr_output
|
1023 |
|
|
sdata_o_sel <= WBR_SEL ;
|
1024 |
|
|
|
1025 |
|
|
// this state is for reads only - in this state read is in progress all the time
|
1026 |
|
|
del_in_progress_out <= 1'b1 ;
|
1027 |
|
|
|
1028 |
|
|
if(burst_transfer)
|
1029 |
|
|
begin
|
1030 |
|
|
if(rattempt)
|
1031 |
|
|
begin
|
1032 |
|
|
// check for error conditions
|
1033 |
|
|
if (~same_hit || // read passed image's range
|
1034 |
|
|
~alligned_address ) // address is not alligned within burst transfer
|
1035 |
|
|
begin
|
1036 |
|
|
// return to idle state
|
1037 |
|
|
n_state <= S_IDLE ;
|
1038 |
|
|
|
1039 |
|
|
// signal an error
|
1040 |
|
|
ack <= 1'b0 ;
|
1041 |
|
|
rty <= 1'b0 ;
|
1042 |
|
|
err <= 1'b1 ;
|
1043 |
|
|
|
1044 |
|
|
// read signals : signal that read completion has finished on WISHBONE and flush FIFO
|
1045 |
|
|
wbr_fifo_flush <= 1'b1 ;
|
1046 |
|
|
wbr_fifo_renable <= 1'b0 ;
|
1047 |
|
|
del_req <= 1'b0 ;
|
1048 |
|
|
del_done <= 1'b1 ;
|
1049 |
|
|
end // error
|
1050 |
|
|
else
|
1051 |
|
|
if (wbr_fifo_control_in == `DATA_ERROR)
|
1052 |
|
|
begin
|
1053 |
|
|
// signal an error has occured on PCI bus during this location read
|
1054 |
|
|
n_state <= S_IDLE ; // go back to idle state
|
1055 |
|
|
|
1056 |
|
|
// respond with error
|
1057 |
|
|
ack <= 1'b0 ;
|
1058 |
|
|
rty <= 1'b0 ;
|
1059 |
|
|
err <= 1'b1 ;
|
1060 |
|
|
|
1061 |
|
|
// read controls - enable fifo read and signal that read is finished
|
1062 |
|
|
wbr_fifo_flush <= 1'b0 ;
|
1063 |
|
|
wbr_fifo_renable <= 1'b1 ;
|
1064 |
|
|
del_req <= 1'b0 ;
|
1065 |
|
|
del_done <= 1'b1 ;
|
1066 |
|
|
end
|
1067 |
|
|
else
|
1068 |
|
|
if (wbr_fifo_almost_empty_in) // WB is now reading last data from FIFO
|
1069 |
|
|
begin
|
1070 |
|
|
n_state <= S_IDLE ; // go back to idle state
|
1071 |
|
|
|
1072 |
|
|
// acknowledge the transaction
|
1073 |
|
|
ack <= 1'b1 ;
|
1074 |
|
|
rty <= 1'b0 ;
|
1075 |
|
|
err <= 1'b0 ;
|
1076 |
|
|
|
1077 |
|
|
// read controls - enable fifo read and signal that read is finished
|
1078 |
|
|
wbr_fifo_flush <= 1'b0 ;
|
1079 |
|
|
wbr_fifo_renable <= 1'b1 ;
|
1080 |
|
|
del_req <= 1'b0 ;
|
1081 |
|
|
del_done <= 1'b1 ;
|
1082 |
|
|
|
1083 |
|
|
end //wbr_fifo_almost_empty_in
|
1084 |
|
|
else //~wbr_fifo_almost_empty_in
|
1085 |
|
|
begin
|
1086 |
|
|
n_state <= S_READ ; // stay in this state
|
1087 |
|
|
|
1088 |
|
|
// acknowledge the transaction
|
1089 |
|
|
ack <= 1'b1 ;
|
1090 |
|
|
rty <= 1'b0 ;
|
1091 |
|
|
err <= 1'b0 ;
|
1092 |
|
|
|
1093 |
|
|
// read controls - enable fifo read
|
1094 |
|
|
wbr_fifo_flush <= 1'b0 ;
|
1095 |
|
|
wbr_fifo_renable <= 1'b1 ;
|
1096 |
|
|
del_req <= 1'b0 ;
|
1097 |
|
|
del_done <= 1'b0 ;
|
1098 |
|
|
end //~wbr_fifo_almost_empty_in
|
1099 |
|
|
end //rattempt
|
1100 |
|
|
else
|
1101 |
|
|
begin //~rattempt
|
1102 |
|
|
n_state <= S_READ ; // stay in this state
|
1103 |
|
|
|
1104 |
|
|
// response signals inactive
|
1105 |
|
|
ack <= 1'b0 ;
|
1106 |
|
|
rty <= 1'b0 ;
|
1107 |
|
|
err <= 1'b0 ;
|
1108 |
|
|
|
1109 |
|
|
// read controls - inactive - master inserting WS
|
1110 |
|
|
wbr_fifo_flush <= 1'b0 ;
|
1111 |
|
|
wbr_fifo_renable <= 1'b0 ;
|
1112 |
|
|
del_req <= 1'b0 ;
|
1113 |
|
|
del_done <= 1'b0 ;
|
1114 |
|
|
end //~rattempt
|
1115 |
|
|
end //burst_transfer
|
1116 |
|
|
else //~burst_transfer
|
1117 |
|
|
begin
|
1118 |
|
|
// this isn't a burst transfer - return to IDLE state
|
1119 |
|
|
n_state <= S_IDLE ;
|
1120 |
|
|
|
1121 |
|
|
// do not respond with any signal
|
1122 |
|
|
ack <= 1'b0 ;
|
1123 |
|
|
rty <= 1'b0 ;
|
1124 |
|
|
err <= 1'b0 ;
|
1125 |
|
|
|
1126 |
|
|
// read signals : signal that read completion has finished on WISHBONE and flush FIFO
|
1127 |
|
|
wbr_fifo_flush <= 1'b1 ;
|
1128 |
|
|
wbr_fifo_renable <= 1'b0 ;
|
1129 |
|
|
del_req <= 1'b0 ;
|
1130 |
|
|
del_done <= 1'b1 ;
|
1131 |
|
|
|
1132 |
|
|
end //~burst_transfer
|
1133 |
|
|
end // S_READ
|
1134 |
|
|
|
1135 |
|
|
S_TURN_ARROUND:begin
|
1136 |
|
|
// turn-arround is provided for FIFO - it does everything necesarry by itself
|
1137 |
|
|
n_state <= S_IDLE ; // next state is always idle
|
1138 |
|
|
|
1139 |
|
|
// response signals inactive
|
1140 |
|
|
ack <= 1'b0 ;
|
1141 |
|
|
rty <= 1'b0 ;
|
1142 |
|
|
err <= 1'b0 ;
|
1143 |
|
|
|
1144 |
|
|
//write signals inactive
|
1145 |
|
|
wbw_fifo_control <= `ADDRESS ;
|
1146 |
|
|
wbw_fifo_wenable <= 1'b0 ;
|
1147 |
|
|
d_incoming_ena <= 1'b0 ;
|
1148 |
|
|
|
1149 |
|
|
// read signals inactive
|
1150 |
|
|
wbr_fifo_flush <= 1'b0 ;
|
1151 |
|
|
wbr_fifo_renable <= 1'b0 ;
|
1152 |
|
|
del_req <= 1'b0 ;
|
1153 |
|
|
del_done <= 1'b0 ;
|
1154 |
|
|
|
1155 |
|
|
// configuration space control signals inactive
|
1156 |
|
|
conf_wenable <= 1'b0 ;
|
1157 |
|
|
conf_renable <= 1'b0 ;
|
1158 |
|
|
|
1159 |
|
|
// WISHBONE data output selection - drive wbr_output
|
1160 |
|
|
sdata_o_sel <= WBR_SEL ;
|
1161 |
|
|
|
1162 |
|
|
// read is not in progress
|
1163 |
|
|
del_in_progress_out <= 1'b0 ;
|
1164 |
|
|
|
1165 |
|
|
end // S_TURN_ARROUND
|
1166 |
|
|
S_CONF_WRITE: begin
|
1167 |
|
|
n_state <= S_IDLE ; // next state after configuration access is always idle
|
1168 |
|
|
|
1169 |
|
|
//image write signals inactive
|
1170 |
|
|
wbw_fifo_control <= `ADDRESS ;
|
1171 |
|
|
wbw_fifo_wenable <= 1'b0 ;
|
1172 |
|
|
d_incoming_ena <= 1'b0 ;
|
1173 |
|
|
|
1174 |
|
|
// image read signals inactive
|
1175 |
|
|
wbr_fifo_flush <= 1'b0 ;
|
1176 |
|
|
wbr_fifo_renable <= 1'b0 ;
|
1177 |
|
|
|
1178 |
|
|
// configuration space read enable control signal inactive
|
1179 |
|
|
conf_renable <= 1'b0 ;
|
1180 |
|
|
|
1181 |
|
|
// WISHBONE data output selection - drive wbr_output
|
1182 |
|
|
sdata_o_sel <= WBR_SEL ;
|
1183 |
|
|
|
1184 |
|
|
if (wb_conf_hit_in && wattempt)
|
1185 |
|
|
begin
|
1186 |
|
|
if (burst_transfer || // bursts not allowed to configuration space
|
1187 |
|
|
sel_error ) // illegal address and select lines combination
|
1188 |
|
|
begin
|
1189 |
|
|
// burst transfer to configuration space
|
1190 |
|
|
// respond with an error
|
1191 |
|
|
ack <= 1'b0 ;
|
1192 |
|
|
rty <= 1'b0 ;
|
1193 |
|
|
err <= 1'b1 ;
|
1194 |
|
|
|
1195 |
|
|
// configuration access write enable control signal inactive
|
1196 |
|
|
conf_wenable <= 1'b0 ;
|
1197 |
|
|
|
1198 |
|
|
// delayed request signals inactive
|
1199 |
|
|
del_req <= 1'b0 ;
|
1200 |
|
|
del_done <= 1'b0 ;
|
1201 |
|
|
|
1202 |
|
|
// delayed is not in progress since this is an error
|
1203 |
|
|
del_in_progress_out <= 1'b0 ;
|
1204 |
|
|
|
1205 |
|
|
end //error
|
1206 |
|
|
else
|
1207 |
|
|
|
1208 |
|
|
`ifdef GUEST
|
1209 |
|
|
begin
|
1210 |
|
|
// guest bridge doesn't have write access to configuration space
|
1211 |
|
|
conf_wenable <= 1'b0 ;
|
1212 |
|
|
|
1213 |
|
|
// acknowledge the cycle
|
1214 |
|
|
rty <= 1'b0 ;
|
1215 |
|
|
ack <= 1'b1 ;
|
1216 |
|
|
err <= 1'b0 ;
|
1217 |
|
|
|
1218 |
|
|
// delayed request signals inactive
|
1219 |
|
|
del_req <= 1'b0 ;
|
1220 |
|
|
del_done <= 1'b0 ;
|
1221 |
|
|
|
1222 |
|
|
// delayed transaction is not in progress
|
1223 |
|
|
del_in_progress_out <= 1'b0 ;
|
1224 |
|
|
end
|
1225 |
|
|
|
1226 |
|
|
`else
|
1227 |
|
|
`ifdef HOST
|
1228 |
|
|
// check whether this is a write to conf. cycle register
|
1229 |
|
|
if ( ccyc_hit )
|
1230 |
|
|
begin
|
1231 |
|
|
conf_wenable <= 1'b0 ;
|
1232 |
|
|
// retry
|
1233 |
|
|
if (~do_ccyc_req && ~do_ccyc_comp) // neither request or completion can be performed at this time - retry
|
1234 |
|
|
begin
|
1235 |
|
|
|
1236 |
|
|
rty <= 1'b1 ;
|
1237 |
|
|
ack <= 1'b0 ;
|
1238 |
|
|
err <= 1'b0 ;
|
1239 |
|
|
|
1240 |
|
|
// delayed request signals inactive
|
1241 |
|
|
del_req <= 1'b0 ;
|
1242 |
|
|
del_done <= 1'b0 ;
|
1243 |
|
|
|
1244 |
|
|
// delayed transaction is not in progress
|
1245 |
|
|
del_in_progress_out <= 1'b0 ;
|
1246 |
|
|
|
1247 |
|
|
end //retry
|
1248 |
|
|
else
|
1249 |
|
|
if (do_ccyc_req)
|
1250 |
|
|
begin
|
1251 |
|
|
// request can be issued - respond with retry
|
1252 |
|
|
rty <= 1'b1 ;
|
1253 |
|
|
ack <= 1'b0 ;
|
1254 |
|
|
err <= 1'b0 ;
|
1255 |
|
|
|
1256 |
|
|
// issue delayed request
|
1257 |
|
|
del_req <= 1'b1 ;
|
1258 |
|
|
del_done <= 1'b0 ;
|
1259 |
|
|
|
1260 |
|
|
// delayed completion is not in progress
|
1261 |
|
|
del_in_progress_out <= 1'b0 ;
|
1262 |
|
|
end
|
1263 |
|
|
else // do ccyc completion
|
1264 |
|
|
begin
|
1265 |
|
|
|
1266 |
|
|
// signal completion done and in progress
|
1267 |
|
|
del_req <= 1'b0 ;
|
1268 |
|
|
del_done <= 1'b1 ;
|
1269 |
|
|
del_in_progress_out <= 1'b1 ;
|
1270 |
|
|
|
1271 |
|
|
if (del_error_in) // request was finished with target abort - signal an error
|
1272 |
|
|
begin
|
1273 |
|
|
rty <= 1'b0 ;
|
1274 |
|
|
ack <= 1'b0 ;
|
1275 |
|
|
err <= 1'b1 ;
|
1276 |
|
|
|
1277 |
|
|
end // del_error_in
|
1278 |
|
|
else
|
1279 |
|
|
begin // ccyc master abort or normal
|
1280 |
|
|
rty <= 1'b0 ;
|
1281 |
|
|
ack <= 1'b1 ;
|
1282 |
|
|
err <= 1'b0 ;
|
1283 |
|
|
end
|
1284 |
|
|
end //ccyc completion
|
1285 |
|
|
end //conf_cyc_hit
|
1286 |
|
|
else //ordinary configuration hit
|
1287 |
|
|
begin
|
1288 |
|
|
|
1289 |
|
|
// enable configuration space write
|
1290 |
|
|
conf_wenable <= 1'b1 ;
|
1291 |
|
|
|
1292 |
|
|
// acknowledge the cycle
|
1293 |
|
|
rty <= 1'b0 ;
|
1294 |
|
|
ack <= 1'b1 ;
|
1295 |
|
|
err <= 1'b0 ;
|
1296 |
|
|
|
1297 |
|
|
// delayed request controls inactive
|
1298 |
|
|
del_req <= 1'b0 ;
|
1299 |
|
|
del_done <= 1'b0 ;
|
1300 |
|
|
del_in_progress_out <= 1'b0 ;
|
1301 |
|
|
|
1302 |
|
|
end //ordinary configuration hit
|
1303 |
|
|
`endif
|
1304 |
|
|
`endif
|
1305 |
|
|
end // wb_conf_hit_in
|
1306 |
|
|
|
1307 |
|
|
else // no conf hit
|
1308 |
|
|
begin
|
1309 |
|
|
rty <= 1'b0 ;
|
1310 |
|
|
ack <= 1'b0 ;
|
1311 |
|
|
err <= 1'b0 ;
|
1312 |
|
|
|
1313 |
|
|
// configuration write enable inactive
|
1314 |
|
|
conf_wenable <= 1'b0 ;
|
1315 |
|
|
|
1316 |
|
|
// configuration cycle controls inactive
|
1317 |
|
|
del_req <= 1'b0 ;
|
1318 |
|
|
del_done <= 1'b0 ;
|
1319 |
|
|
del_in_progress_out <= 1'b0 ;
|
1320 |
|
|
|
1321 |
|
|
end // no conf hit
|
1322 |
|
|
|
1323 |
|
|
end // S_CONF_WRITE
|
1324 |
|
|
|
1325 |
|
|
S_CONF_READ: begin
|
1326 |
|
|
n_state <= S_IDLE ; // next state after configuration access is always idle
|
1327 |
|
|
|
1328 |
|
|
//image write signals inactive
|
1329 |
|
|
wbw_fifo_control <= `ADDRESS ;
|
1330 |
|
|
wbw_fifo_wenable <= 1'b0 ;
|
1331 |
|
|
d_incoming_ena <= 1'b0 ;
|
1332 |
|
|
|
1333 |
|
|
// image read signals inactive
|
1334 |
|
|
wbr_fifo_flush <= 1'b0 ;
|
1335 |
|
|
|
1336 |
|
|
// configuration space write enable control signal inactive
|
1337 |
|
|
conf_wenable <= 1'b0 ;
|
1338 |
|
|
|
1339 |
|
|
if(wb_conf_hit_in && rattempt) // read from configuration space
|
1340 |
|
|
begin
|
1341 |
|
|
|
1342 |
|
|
if (burst_transfer || // bursts not allowed to configuration space
|
1343 |
|
|
sel_error ) // illegal address and select lines combination
|
1344 |
|
|
begin
|
1345 |
|
|
// respond with an error
|
1346 |
|
|
ack <= 1'b0 ;
|
1347 |
|
|
rty <= 1'b0 ;
|
1348 |
|
|
err <= 1'b1 ;
|
1349 |
|
|
|
1350 |
|
|
// delayed request control inactive
|
1351 |
|
|
del_req <= 1'b0 ;
|
1352 |
|
|
del_done <= 1'b0 ;
|
1353 |
|
|
|
1354 |
|
|
// delayed transaction is not in progress
|
1355 |
|
|
del_in_progress_out <= 1'b0 ;
|
1356 |
|
|
|
1357 |
|
|
// configuration read enable inactive
|
1358 |
|
|
conf_renable <= 1'b0 ;
|
1359 |
|
|
|
1360 |
|
|
// WISHBONE data output selection - drive configuration output
|
1361 |
|
|
sdata_o_sel <= CONF_SEL ;
|
1362 |
|
|
|
1363 |
|
|
// fifo read enable inactive
|
1364 |
|
|
wbr_fifo_renable <= 1'b0 ;
|
1365 |
|
|
|
1366 |
|
|
end //error
|
1367 |
|
|
else
|
1368 |
|
|
|
1369 |
|
|
`ifdef GUEST
|
1370 |
|
|
|
1371 |
|
|
begin // ordinary configuration read
|
1372 |
|
|
ack <= 1'b1 ;
|
1373 |
|
|
rty <= 1'b0 ;
|
1374 |
|
|
err <= 1'b0 ;
|
1375 |
|
|
|
1376 |
|
|
// configuration read enable active
|
1377 |
|
|
conf_renable <= 1'b1 ;
|
1378 |
|
|
|
1379 |
|
|
// WISHBONE data output selection - drive configuration output
|
1380 |
|
|
sdata_o_sel <= CONF_SEL ;
|
1381 |
|
|
|
1382 |
|
|
// delayed request signals inactive
|
1383 |
|
|
del_req <= 1'b0 ;
|
1384 |
|
|
del_done <= 1'b0 ;
|
1385 |
|
|
del_in_progress_out <= 1'b0 ;
|
1386 |
|
|
|
1387 |
|
|
// fifo read enable inactive
|
1388 |
|
|
wbr_fifo_renable <= 1'b0 ;
|
1389 |
|
|
|
1390 |
|
|
end // ordinary configuration read
|
1391 |
|
|
|
1392 |
|
|
`else
|
1393 |
|
|
`ifdef HOST
|
1394 |
|
|
// check whether this is a read from conf. cycle register
|
1395 |
|
|
if ( ccyc_hit )
|
1396 |
|
|
begin
|
1397 |
|
|
|
1398 |
|
|
// configuration read enable inactive
|
1399 |
|
|
conf_renable <= 1'b0 ;
|
1400 |
|
|
|
1401 |
|
|
// WISHBONE data output selection - drive configuration cycle output
|
1402 |
|
|
sdata_o_sel <= WBR_SEL ;
|
1403 |
|
|
|
1404 |
|
|
// retry
|
1405 |
|
|
if (~do_ccyc_req && ~do_ccyc_comp) // neither request or completion can be performed at this time - retry
|
1406 |
|
|
begin
|
1407 |
|
|
rty <= 1'b1 ;
|
1408 |
|
|
ack <= 1'b0 ;
|
1409 |
|
|
err <= 1'b0 ;
|
1410 |
|
|
|
1411 |
|
|
// do not issue new request
|
1412 |
|
|
del_req <= 1'b0 ;
|
1413 |
|
|
del_done <= 1'b0 ;
|
1414 |
|
|
del_in_progress_out <= 1'b0 ;
|
1415 |
|
|
|
1416 |
|
|
// fifo read enable inactive
|
1417 |
|
|
wbr_fifo_renable <= 1'b0 ;
|
1418 |
|
|
|
1419 |
|
|
end //retry
|
1420 |
|
|
else
|
1421 |
|
|
if (do_ccyc_req)
|
1422 |
|
|
begin
|
1423 |
|
|
// request can be issued - respond with retry
|
1424 |
|
|
rty <= 1'b1 ;
|
1425 |
|
|
ack <= 1'b0 ;
|
1426 |
|
|
err <= 1'b0 ;
|
1427 |
|
|
|
1428 |
|
|
// initiate configuration write request
|
1429 |
|
|
del_req <= 1'b1 ;
|
1430 |
|
|
del_done <= 1'b0 ;
|
1431 |
|
|
del_in_progress_out <= 1'b0 ;
|
1432 |
|
|
|
1433 |
|
|
// fifo read enable inactive
|
1434 |
|
|
wbr_fifo_renable <= 1'b0 ;
|
1435 |
|
|
end
|
1436 |
|
|
else // do ccyc completion
|
1437 |
|
|
begin
|
1438 |
|
|
|
1439 |
|
|
// signal completion done and in progress
|
1440 |
|
|
del_done <= 1'b1 ;
|
1441 |
|
|
del_in_progress_out <= 1'b1 ;
|
1442 |
|
|
|
1443 |
|
|
// fifo read enable
|
1444 |
|
|
wbr_fifo_renable <= 1'b1 ;
|
1445 |
|
|
|
1446 |
|
|
// don't issue new request
|
1447 |
|
|
del_req <= 1'b0 ;
|
1448 |
|
|
|
1449 |
|
|
if (del_error_in) // request was finished with target abort - signal an error
|
1450 |
|
|
begin
|
1451 |
|
|
rty <= 1'b0 ;
|
1452 |
|
|
ack <= 1'b0 ;
|
1453 |
|
|
err <= 1'b1 ;
|
1454 |
|
|
|
1455 |
|
|
end // ccyc_tabort
|
1456 |
|
|
else
|
1457 |
|
|
begin // ccyc master abort or normal
|
1458 |
|
|
rty <= 1'b0 ;
|
1459 |
|
|
ack <= 1'b1 ;
|
1460 |
|
|
err <= 1'b0 ;
|
1461 |
|
|
end
|
1462 |
|
|
end // ccyc_completion
|
1463 |
|
|
end //conf_cyc_hit
|
1464 |
|
|
else
|
1465 |
|
|
// check if this is an interrupt acknowledge cycle request
|
1466 |
|
|
if(iack_hit)
|
1467 |
|
|
begin
|
1468 |
|
|
|
1469 |
|
|
// configuration read enable inactive
|
1470 |
|
|
conf_renable <= 1'b0 ;
|
1471 |
|
|
|
1472 |
|
|
// WISHBONE data output selection - drive interrupt acknowledge output
|
1473 |
|
|
sdata_o_sel <= WBR_SEL ;
|
1474 |
|
|
|
1475 |
|
|
// retry
|
1476 |
|
|
if (~do_iack_req && ~do_iack_comp) // neither request or completion can be performed at this time - retry
|
1477 |
|
|
begin
|
1478 |
|
|
rty <= 1'b1 ;
|
1479 |
|
|
ack <= 1'b0 ;
|
1480 |
|
|
err <= 1'b0 ;
|
1481 |
|
|
|
1482 |
|
|
// delayed control signals inactive
|
1483 |
|
|
del_req <= 1'b0 ;
|
1484 |
|
|
del_done <= 1'b0 ;
|
1485 |
|
|
del_in_progress_out <= 1'b0 ;
|
1486 |
|
|
|
1487 |
|
|
// fifo read enable inactive
|
1488 |
|
|
wbr_fifo_renable <= 1'b0 ;
|
1489 |
|
|
|
1490 |
|
|
end //retry
|
1491 |
|
|
else
|
1492 |
|
|
if (do_iack_req)
|
1493 |
|
|
begin
|
1494 |
|
|
// request can be issued - respond with retry
|
1495 |
|
|
rty <= 1'b1 ;
|
1496 |
|
|
ack <= 1'b0 ;
|
1497 |
|
|
err <= 1'b0 ;
|
1498 |
|
|
|
1499 |
|
|
// initiate interrupt acknowledge request
|
1500 |
|
|
del_req <= 1'b1 ;
|
1501 |
|
|
del_done <= 1'b0 ;
|
1502 |
|
|
del_in_progress_out <= 1'b0 ;
|
1503 |
|
|
|
1504 |
|
|
// fifo read enable inactive
|
1505 |
|
|
wbr_fifo_renable <= 1'b0 ;
|
1506 |
|
|
|
1507 |
|
|
end
|
1508 |
|
|
else
|
1509 |
|
|
begin //do iack completion
|
1510 |
|
|
del_req <= 1'b0 ;
|
1511 |
|
|
del_done <= 1'b1 ; // signal done
|
1512 |
|
|
del_in_progress_out <= 1'b1 ;
|
1513 |
|
|
|
1514 |
|
|
// fifo read enable
|
1515 |
|
|
wbr_fifo_renable <= 1'b1 ;
|
1516 |
|
|
|
1517 |
|
|
rty <= 1'b0 ; // retry inactive - completion can be terminated with either acknowledge or error
|
1518 |
|
|
|
1519 |
|
|
if (del_error_in) // terminated with target abort
|
1520 |
|
|
begin
|
1521 |
|
|
ack <= 1'b0 ;
|
1522 |
|
|
err <= 1'b1 ;
|
1523 |
|
|
end // target abort
|
1524 |
|
|
else
|
1525 |
|
|
begin
|
1526 |
|
|
ack <= 1'b1 ;
|
1527 |
|
|
err <= 1'b0 ;
|
1528 |
|
|
end // target termination normal
|
1529 |
|
|
|
1530 |
|
|
end // do iack completion
|
1531 |
|
|
|
1532 |
|
|
end // iack_hit
|
1533 |
|
|
else
|
1534 |
|
|
begin // configuration read from ordinary configuration space
|
1535 |
|
|
// configuration cycle controls inactive
|
1536 |
|
|
del_req <= 1'b0 ;
|
1537 |
|
|
del_done <= 1'b0 ;
|
1538 |
|
|
del_in_progress_out <= 1'b0 ;
|
1539 |
|
|
|
1540 |
|
|
// fifo read enable inactive
|
1541 |
|
|
wbr_fifo_renable <= 1'b0 ;
|
1542 |
|
|
|
1543 |
|
|
// configuration read enable active
|
1544 |
|
|
conf_renable <= 1'b1 ;
|
1545 |
|
|
|
1546 |
|
|
// acknowledge this cycle
|
1547 |
|
|
rty <= 1'b0 ;
|
1548 |
|
|
ack <= 1'b1 ;
|
1549 |
|
|
err <= 1'b0 ;
|
1550 |
|
|
|
1551 |
|
|
// WISHBONE data output selection - drive configuration output
|
1552 |
|
|
sdata_o_sel <= CONF_SEL ;
|
1553 |
|
|
end
|
1554 |
|
|
`endif
|
1555 |
|
|
`endif
|
1556 |
|
|
|
1557 |
|
|
end //read from configuration space
|
1558 |
|
|
|
1559 |
|
|
else // no hit
|
1560 |
|
|
begin
|
1561 |
|
|
// response signals inactive
|
1562 |
|
|
ack <= 1'b0 ;
|
1563 |
|
|
rty <= 1'b0 ;
|
1564 |
|
|
err <= 1'b0 ;
|
1565 |
|
|
|
1566 |
|
|
// configuration cycle controls inactive
|
1567 |
|
|
del_req <= 1'b0 ;
|
1568 |
|
|
del_done <= 1'b0 ;
|
1569 |
|
|
del_in_progress_out <= 1'b0 ;
|
1570 |
|
|
|
1571 |
|
|
// fifo read enable inactive
|
1572 |
|
|
wbr_fifo_renable <= 1'b0 ;
|
1573 |
|
|
|
1574 |
|
|
// configuration read enable inactive
|
1575 |
|
|
conf_renable <= 1'b0 ;
|
1576 |
|
|
|
1577 |
|
|
// WISHBONE data output selection - drive configuration output
|
1578 |
|
|
sdata_o_sel <= CONF_SEL ;
|
1579 |
|
|
|
1580 |
|
|
end // no hit
|
1581 |
|
|
end //S_CONF_READ
|
1582 |
|
|
default:begin
|
1583 |
|
|
n_state <= S_IDLE ; // return to idle state
|
1584 |
|
|
|
1585 |
|
|
// response signals inactive
|
1586 |
|
|
ack <= 1'b0 ;
|
1587 |
|
|
rty <= 1'b0 ;
|
1588 |
|
|
err <= 1'b0 ;
|
1589 |
|
|
|
1590 |
|
|
//write signals inactive
|
1591 |
|
|
wbw_fifo_control <= `ADDRESS ;
|
1592 |
|
|
wbw_fifo_wenable <= 1'b0 ;
|
1593 |
|
|
d_incoming_ena <= 1'b0 ;
|
1594 |
|
|
|
1595 |
|
|
// read signals inactive
|
1596 |
|
|
wbr_fifo_flush <= 1'b0 ;
|
1597 |
|
|
wbr_fifo_renable <= 1'b0 ;
|
1598 |
|
|
del_req <= 1'b0 ;
|
1599 |
|
|
del_done <= 1'b0 ;
|
1600 |
|
|
|
1601 |
|
|
// configuration space control signals inactive
|
1602 |
|
|
conf_wenable <= 1'b0 ;
|
1603 |
|
|
conf_renable <= 1'b0 ;
|
1604 |
|
|
|
1605 |
|
|
// WISHBONE data output selection - drive wbr output
|
1606 |
|
|
sdata_o_sel <= WBR_SEL ;
|
1607 |
|
|
|
1608 |
|
|
// read is not in progress
|
1609 |
|
|
del_in_progress_out <= 1'b0 ;
|
1610 |
|
|
|
1611 |
|
|
end //default
|
1612 |
|
|
endcase
|
1613 |
|
|
end
|
1614 |
|
|
|
1615 |
|
|
// configuration space offset output assignment
|
1616 |
|
|
assign wb_conf_offset_out = {wb_addr_in[11:2], 2'b00} ; // upper 10 bits of address input and two zeros
|
1617 |
|
|
|
1618 |
|
|
// Configuration space byte enables output
|
1619 |
|
|
assign wb_conf_be_out = SEL_I ; // just route select lines from WISHBONE to conf space
|
1620 |
|
|
|
1621 |
|
|
// data output assignment - for image writes, first data is address, subsequent data comes from intermediate register
|
1622 |
|
|
reg [31:0] wb_data_out ;
|
1623 |
|
|
always@(ccyc_hit or c_state or wb_addr_in or ccyc_addr_in or d_incoming)
|
1624 |
|
|
begin
|
1625 |
|
|
wb_data_out <= d_incoming ;
|
1626 |
|
|
if ( c_state == S_IDLE )
|
1627 |
|
|
wb_data_out <= wb_addr_in ;
|
1628 |
|
|
else
|
1629 |
|
|
if ( ((c_state == S_CONF_WRITE) || (c_state == S_CONF_READ)) && ccyc_hit )
|
1630 |
|
|
wb_data_out <= ccyc_addr_in ;
|
1631 |
|
|
end
|
1632 |
|
|
|
1633 |
|
|
// command / byte enable assignment - with address, bus command is provided, with data - byte enables are provided
|
1634 |
|
|
reg [3:0] wb_cbe ;
|
1635 |
|
|
assign wb_cbe_out = wb_cbe ;
|
1636 |
|
|
|
1637 |
|
|
always@(c_state or d_incoming or map)
|
1638 |
|
|
begin
|
1639 |
|
|
if (c_state == S_IDLE)
|
1640 |
|
|
begin
|
1641 |
|
|
if (map)
|
1642 |
|
|
wb_cbe <= `BC_IO_WRITE ;
|
1643 |
|
|
else
|
1644 |
|
|
wb_cbe <= `BC_MEM_WRITE ;
|
1645 |
|
|
end
|
1646 |
|
|
else
|
1647 |
|
|
wb_cbe <= ~(d_incoming[35:32]) ;
|
1648 |
|
|
end
|
1649 |
|
|
|
1650 |
|
|
// for configuration writes, data output is always data from WISHBONE - in guest implementation data is all 0.
|
1651 |
|
|
`ifdef GUEST
|
1652 |
|
|
assign wb_conf_data_out = 32'h00000000 ;
|
1653 |
|
|
`else
|
1654 |
|
|
`ifdef HOST
|
1655 |
|
|
assign wb_conf_data_out = SDATA_I ;
|
1656 |
|
|
`endif
|
1657 |
|
|
`endif
|
1658 |
|
|
|
1659 |
|
|
// WISHBONE data output multiplexor
|
1660 |
|
|
reg [31:0] sdata ;
|
1661 |
|
|
assign SDATA_O = sdata ;
|
1662 |
|
|
|
1663 |
|
|
always@(sdata_o_sel or wbr_fifo_data_in or wb_conf_data_in)
|
1664 |
|
|
begin
|
1665 |
|
|
case (sdata_o_sel)
|
1666 |
|
|
WBR_SEL :sdata <= wbr_fifo_data_in ;
|
1667 |
|
|
CONF_SEL:sdata <= wb_conf_data_in ;
|
1668 |
|
|
endcase
|
1669 |
|
|
end
|
1670 |
|
|
|
1671 |
|
|
endmodule //WB_SLAVE
|