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[/] [pci/] [tags/] [working_demo/] [rtl/] [verilog/] [delayed_sync.v] - Blame information for rev 154

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  File name "delayed_sync.v"                                  ////
////                                                              ////
////  This file is part of the "PCI bridge" project               ////
////  http://www.opencores.org/cores/pci/                         ////
////                                                              ////
////  Author(s):                                                  ////
////      - Miha Dolenc (mihad@opencores.org)                     ////
////                                                              ////
////  All additional information is avaliable in the README       ////
////  file.                                                       ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1  2001/10/02 15:33:46  mihad
// New project directory structure
//
//
 
// module provides synchronization mechanism between requesting and completing side of the bridge
`include "constants.v"
`include "bus_commands.v"
`include "timescale.v"
module DELAYED_SYNC
(
    reset_in,
    req_clk_in,
    comp_clk_in,
    req_in,
    comp_in,
    done_in,
    in_progress_in,
    comp_req_pending_out,
    req_req_pending_out,
    req_comp_pending_out,
    comp_comp_pending_out,
    addr_in,
    be_in,
    addr_out,
    be_out,
    we_in,
    we_out,
    bc_in,
    bc_out,
    status_in,
    status_out,
    comp_flush_out,
    burst_in,
    burst_out,
    retry_expired_in
);
 
// system inputs
input reset_in,         // reset input
      req_clk_in,       // requesting clock input
      comp_clk_in ;     // completing clock input
 
// request, completion, done and in progress indication inputs
input req_in,           // request qualifier - when 1 it indicates that valid request data is provided on inputs
      comp_in,          // completion qualifier - when 1, completing side indicates that request has completed
      done_in,          // done input - when 1 indicates that requesting side of the bridge has completed a transaction on requesting bus
      in_progress_in ;  // in progress indicator - indicates that current completion is in progress on requesting side of the bridge
 
// pending indication outputs
output  comp_req_pending_out,   // completion side request output - resynchronized from requesting clock to completing clock
        req_req_pending_out,    // request pending output for requesting side
        req_comp_pending_out,   // completion pending output for requesting side of the bridge - it indicates when completion is ready for completing on requesting bus
        comp_comp_pending_out ; // completion pending output for completing side of the bridge
 
// additional signals and wires for clock domain passage of signals
reg     comp_req_pending,
        req_req_pending,
        req_comp_pending,
        req_comp_pending_sample,
        comp_comp_pending,
        req_done_reg,
        comp_done_reg_main,
        comp_done_reg_clr,
        req_rty_exp_reg,
        req_rty_exp_clr,
        comp_rty_exp_reg,
        comp_rty_exp_clr ;
 
wire    sync_comp_req_pending,
        sync_req_comp_pending,
        sync_comp_done,
        sync_req_rty_exp,
        sync_comp_rty_exp_clr ;
 
// inputs from requesting side - only this side can set address, bus command, byte enables, write enable and burst - outputs are common for both sides
// all signals that identify requests are stored in this module
 
input [31:0]    addr_in ;   // address bus input
input [3:0]     be_in ;     // byte enable input
input           we_in ;     // write enable input - read/write request indication 1 = write request / 0 = read request
input [3:0]     bc_in ;     // bus command input
input           burst_in ;  // burst indicator    - qualifies operation as burst/single transfer 1 = burst / 0 = single transfer
 
// common request outputs used both by completing and requesting sides
// this outputs are not resynchronized, since flags determine the request status
output [31:0]   addr_out ;
output [3:0]    be_out ;
output          we_out ;
output [3:0]    bc_out ;
output          burst_out ;
 
// completion side signals encoded termination status - 0 = normal completion / 1 = error terminated completion
input          status_in ;
output         status_out ;
 
// input signals that delayed transaction has been retried for max number of times
// on this signal request is ditched, otherwise it would cause a deadlock
// requestor can issue another request and procedure will be repeated 
input   retry_expired_in ;
 
// completion flush output - if in 2^^16 clock cycles transaction is not repeated by requesting agent - flush completion data
output  comp_flush_out ;
 
// output registers for common signals
reg [31:0]   addr_out ;
reg [3:0]    be_out ;
reg          we_out ;
reg [3:0]    bc_out ;
reg          burst_out ;
 
// delayed transaction information is stored only when request is issued and request nor completion are pending
wire new_request = req_in && ~req_comp_pending_out && ~req_req_pending_out ;
always@(posedge req_clk_in or posedge reset_in)
begin
    if (reset_in)
    begin
        addr_out  <= #`FF_DELAY 32'h0000_0000 ;
        be_out    <= #`FF_DELAY 4'h0 ;
        we_out    <= #`FF_DELAY 1'b0 ;
        bc_out    <= #`FF_DELAY `BC_RESERVED0 ;
        burst_out <= #`FF_DELAY 1'b0 ;
    end
    else
        if (new_request)
        begin
            addr_out  <= #`FF_DELAY addr_in ;
            be_out    <= #`FF_DELAY be_in ;
            we_out    <= #`FF_DELAY we_in ;
            bc_out    <= #`FF_DELAY bc_in ;
            burst_out <= #`FF_DELAY burst_in ;
        end
end
 
// completion pending cycle counter
reg [16:0] comp_cycle_count ;
 
/*=================================================================================================================================
Passing of requests between clock domains:
request originates on requesting side. It's then synchronized with two flip-flops to cross to completing clock domain
=================================================================================================================================*/
// main request flip-flop triggered on requesting side's clock
// request is cleared whenever completion or retry expired is signalled from opposite side of the bridge
wire req_req_clear = req_comp_pending || (req_rty_exp_reg && ~req_rty_exp_clr) ;
always@(posedge req_clk_in or posedge reset_in)
begin
    if ( reset_in )
        req_req_pending <= #`FF_DELAY 1'b0 ;
    else
    if ( req_req_clear )
        req_req_pending <= #`FF_DELAY 1'b0 ;
    else
    if ( req_in )
        req_req_pending <= #`FF_DELAY 1'b1 ;
end
 
// interemediate stage request synchronization flip - flop - this one is prone to metastability
// and should have setup and hold times disabled during simulation
synchronizer_flop req_sync
(
    .data_in        (req_req_pending),
    .clk_out        (comp_clk_in),
    .sync_data_out  (sync_comp_req_pending),
    .async_reset    (reset_in)
) ;
 
// wire for clearing completion side request flag - whenever completion or retry expired are signalled
wire comp_req_pending_clear = comp_req_pending && ( comp_in || retry_expired_in) ;
 
// wire for enabling request flip - flop - it is enabled when completion is not active and done is not active
wire comp_req_pending_ena   = ~comp_comp_pending && ~comp_done_reg_main && ~comp_rty_exp_reg ;
 
// completion side request flip flop - gets a value from intermediate stage sync flip flop
always@(posedge comp_clk_in or posedge reset_in)
begin
    if ( reset_in )
        comp_req_pending <= #`FF_DELAY 1'b0 ;
    else
    if ( comp_req_pending_clear )
        comp_req_pending <= #`FF_DELAY 1'b0 ;
    else
    if ( comp_req_pending_ena )
        comp_req_pending <= #`FF_DELAY sync_comp_req_pending ;
end
 
// completion side request output assignment - when request ff is set and completion ff is not set
assign comp_req_pending_out = comp_req_pending ;
 
// requesting side request pending output
assign req_req_pending_out  = req_req_pending ;
/*=================================================================================================================================
Passing of completions between clock domains:
completion originates on completing side. It's then synchronized with two flip-flops to cross to requesting clock domain
=================================================================================================================================*/
// main completion Flip - Flop - triggered by completing side's clock
// completion side completion pending flag is cleared when done flag propagates through clock domains
wire comp_comp_clear = comp_done_reg_main && ~comp_done_reg_clr ;
always@(posedge comp_clk_in or posedge reset_in)
begin
    if ( reset_in )
        comp_comp_pending <= #`FF_DELAY 1'b0 ;
    else
    if ( comp_comp_clear )
        comp_comp_pending <= #`FF_DELAY 1'b0 ;
    else
    if ( comp_in && comp_req_pending )
        comp_comp_pending <= #`FF_DELAY 1'b1 ;
end
 
assign comp_comp_pending_out = comp_comp_pending ;
 
// interemediate stage completion synchronization flip - flop - this one is prone to metastability
synchronizer_flop comp_sync
(
    .data_in        (comp_comp_pending),
    .clk_out        (req_clk_in),
    .sync_data_out  (sync_req_comp_pending),
    .async_reset    (reset_in)
) ;
 
// request side completion pending flip flop is cleared whenever done is signalled or completion counter expires - 2^^16 clock cycles
wire req_comp_pending_clear = done_in || comp_cycle_count[16];
 
// request side completion pending flip flop is disabled while done flag is set
wire req_comp_pending_ena   = ~req_done_reg ;
 
// request side completion flip flop - gets a value from intermediate stage sync flip flop
always@(posedge req_clk_in or posedge reset_in)
begin
    if ( reset_in )
        req_comp_pending <= #`FF_DELAY 1'b0 ;
    else
    if ( req_comp_pending_clear )
        req_comp_pending <= #`FF_DELAY 1'b0 ;
    else
    if ( req_comp_pending_ena )
        req_comp_pending <= #`FF_DELAY sync_req_comp_pending ;
end
 
// sampling FF - used for sampling incoming completion flag from completing side
always@(posedge req_clk_in or posedge reset_in)
begin
    if ( reset_in )
        req_comp_pending_sample <= #`FF_DELAY 1'b0 ;
    else
        req_comp_pending_sample <= #`FF_DELAY sync_req_comp_pending ;
end
 
// requesting side completion pending output assignment
assign req_comp_pending_out = req_comp_pending && ~req_req_pending ;
 
/*==================================================================================================================================
Passing of delayed transaction done signal between clock domains.
Done is signalled by requesting side of the bridge and is passed to completing side of the bridge
==================================================================================================================================*/
// main done flip-flop triggered on requesting side's clock
// when completing side removes completion flag, done flag is also removed, so requests can proceede
wire req_done_clear = ~req_comp_pending_sample ;
always@(posedge req_clk_in or posedge reset_in)
begin
    if ( reset_in )
        req_done_reg <= #`FF_DELAY 1'b0 ;
    else
    if ( req_done_clear )
        req_done_reg <= #`FF_DELAY 1'b0 ;
    else
    if ( done_in || comp_cycle_count[16] )
        req_done_reg <= #`FF_DELAY 1'b1 ;
end
 
synchronizer_flop done_sync
(
    .data_in        (req_done_reg),
    .clk_out        (comp_clk_in),
    .sync_data_out  (sync_comp_done),
    .async_reset    (reset_in)
) ;
 
always@(posedge comp_clk_in or posedge reset_in)
begin
    if ( reset_in )
        comp_done_reg_main <= #`FF_DELAY 1'b0 ;
    else
        comp_done_reg_main <= #`FF_DELAY sync_comp_done ;
end
 
always@(posedge comp_clk_in or posedge reset_in)
begin
    if ( reset_in )
        comp_done_reg_clr <= #`FF_DELAY 1'b0 ;
    else
        comp_done_reg_clr <= #`FF_DELAY comp_done_reg_main ;
end
 
/*=================================================================================================================================
Passing of retry expired signal between clock domains
Retry expiration originates on completing side. It's then synchronized with two flip-flops to cross to requesting clock domain
=================================================================================================================================*/
// main retry expired Flip - Flop - triggered by completing side's clock
wire comp_rty_exp_clear = comp_rty_exp_clr && comp_rty_exp_reg ;
 
// retry expired is a special case of transaction removal - retry expired propagates from completing
// clock domain to requesting clock domain to remove all pending requests and than propagates back
// to completing side to qualify valid new requests
 
always@(posedge comp_clk_in or posedge reset_in)
begin
    if ( reset_in )
        comp_rty_exp_reg <= #`FF_DELAY 1'b0 ;
    else
    if ( comp_rty_exp_clear )
        comp_rty_exp_reg <= #`FF_DELAY 1'b0 ;
    else
    if ( retry_expired_in && comp_req_pending)
        comp_rty_exp_reg <= #`FF_DELAY 1'b1 ;
end
 
// interemediate stage retry expired synchronization flip - flop - this one is prone to metastability
synchronizer_flop rty_exp_sync
(
    .data_in        (comp_rty_exp_reg),
    .clk_out        (req_clk_in),
    .sync_data_out  (sync_req_rty_exp),
    .async_reset    (reset_in)
) ;
 
// request retry expired flip flop - gets a value from intermediate stage sync flip flop
always@(posedge req_clk_in or posedge reset_in)
begin
    if ( reset_in )
        req_rty_exp_reg <= #`FF_DELAY 1'b0 ;
    else
        req_rty_exp_reg <= #`FF_DELAY sync_req_rty_exp ;
end
 
always@(posedge req_clk_in or posedge reset_in)
begin
    if ( reset_in )
        req_rty_exp_clr <= #`FF_DELAY 1'b0 ;
    else
        req_rty_exp_clr <= #`FF_DELAY req_rty_exp_reg ;
end
 
synchronizer_flop rty_exp_back_prop_sync
(
    .data_in        (req_rty_exp_reg),
    .clk_out        (comp_clk_in),
    .sync_data_out  (sync_comp_rty_exp_clr),
    .async_reset    (reset_in)
) ;
 
always@(posedge comp_clk_in or posedge reset_in)
begin
    if ( reset_in )
        comp_rty_exp_clr <= #`FF_DELAY 1'b0 ;
    else
        comp_rty_exp_clr <= #`FF_DELAY sync_comp_rty_exp_clr ;
end
 
// completion status flip flop - if 0 when completion is signalled it's finished OK otherwise it means error
reg status_out ;
always@(posedge comp_clk_in or posedge reset_in)
begin
    if (reset_in)
        status_out <= #`FF_DELAY 1'b0 ;
    else
    if (comp_in && comp_req_pending)
        status_out <= #`FF_DELAY status_in ;
end
 
// clocks counter - it counts how many clock cycles completion is present without beeing repeated
// if it counts to 2^^16 cycles the completion must be ditched
 
// wire for clearing this counter
wire clear_count = in_progress_in || ~req_comp_pending_out ;
always@(posedge req_clk_in or posedge reset_in)
begin
    if (reset_in)
        comp_cycle_count <= #`FF_DELAY 17'h0_0000 ;
    else
    if (clear_count)
        comp_cycle_count <= #`FF_DELAY 17'h0_0000 ;
    else
        comp_cycle_count <= #`FF_DELAY comp_cycle_count + 1'b1 ;
end
 
// completion flush output - used for flushing fifos when counter expires
// if counter doesn't expire, fifo flush is up to WISHBONE slave or PCI target state machines
reg comp_flush_out ;
always@(posedge req_clk_in or posedge reset_in)
begin
    if (reset_in)
        comp_flush_out <= #`FF_DELAY 1'b0 ;
    else
        comp_flush_out <= #`FF_DELAY comp_cycle_count[16] ;
end
 
endmodule //delayed_sync

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[/] [pci/] [tags/] [working_demo/] [rtl/] [verilog/] [delayed_sync.v] - Blame information for rev 154

Line No.	Rev	Author	Line
1	2	mihad	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// File name "delayed_sync.v" ////`
4			`//// ////`
5			`//// This file is part of the "PCI bridge" project ////`
6			`//// http://www.opencores.org/cores/pci/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Miha Dolenc (mihad@opencores.org) ////`
10			`//// ////`
11			`//// All additional information is avaliable in the README ////`
12			`//// file. ////`
13			`//// ////`
14			`//// ////`
15			`//////////////////////////////////////////////////////////////////////`
16			`//// ////`
17			`//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org ////`
18			`//// ////`
19			`//// This source file may be used and distributed without ////`
20			`//// restriction provided that this copyright statement is not ////`
21			`//// removed from the file and that any derivative work contains ////`
22			`//// the original copyright notice and the associated disclaimer. ////`
23			`//// ////`
24			`//// This source file is free software; you can redistribute it ////`
25			`//// and/or modify it under the terms of the GNU Lesser General ////`
26			`//// Public License as published by the Free Software Foundation; ////`
27			`//// either version 2.1 of the License, or (at your option) any ////`
28			`//// later version. ////`
29			`//// ////`
30			`//// This source is distributed in the hope that it will be ////`
31			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
32			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
33			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
34			`//// details. ////`
35			`//// ////`
36			`//// You should have received a copy of the GNU Lesser General ////`
37			`//// Public License along with this source; if not, download it ////`
38			`//// from http://www.opencores.org/lgpl.shtml ////`
39			`//// ////`
40			`//////////////////////////////////////////////////////////////////////`
41			`//`
42			`// CVS Revision History`
43			`//`
44			`// $Log: not supported by cvs2svn $`
45	6	mihad	`// Revision 1.1.1.1 2001/10/02 15:33:46 mihad`
46			`// New project directory structure`
47	2	mihad	`//`
48	6	mihad	`//`
49	2	mihad
50			`// module provides synchronization mechanism between requesting and completing side of the bridge`
51			`include "constants.v"
52			`include "bus_commands.v"
53	6	mihad	`include "timescale.v"
54	2	mihad	`module DELAYED_SYNC`
55			`(`
56			`reset_in,`
57			`req_clk_in,`
58			`comp_clk_in,`
59			`req_in,`
60			`comp_in,`
61			`done_in,`
62			`in_progress_in,`
63			`comp_req_pending_out,`
64			`req_req_pending_out,`
65			`req_comp_pending_out,`
66			`comp_comp_pending_out,`
67			`addr_in,`
68			`be_in,`
69			`addr_out,`
70			`be_out,`
71			`we_in,`
72			`we_out,`
73			`bc_in,`
74			`bc_out,`
75			`status_in,`
76			`status_out,`
77			`comp_flush_out,`
78			`burst_in,`
79			`burst_out,`
80			`retry_expired_in`
81			`);`
82
83			`// system inputs`
84			`input reset_in, // reset input`
85			`req_clk_in, // requesting clock input`
86			`comp_clk_in ; // completing clock input`
87
88			`// request, completion, done and in progress indication inputs`
89			`input req_in, // request qualifier - when 1 it indicates that valid request data is provided on inputs`
90			`comp_in, // completion qualifier - when 1, completing side indicates that request has completed`
91			`done_in, // done input - when 1 indicates that requesting side of the bridge has completed a transaction on requesting bus`
92			`in_progress_in ; // in progress indicator - indicates that current completion is in progress on requesting side of the bridge`
93
94			`// pending indication outputs`
95			`output comp_req_pending_out, // completion side request output - resynchronized from requesting clock to completing clock`
96			`req_req_pending_out, // request pending output for requesting side`
97			`req_comp_pending_out, // completion pending output for requesting side of the bridge - it indicates when completion is ready for completing on requesting bus`
98			`comp_comp_pending_out ; // completion pending output for completing side of the bridge`
99
100			`// additional signals and wires for clock domain passage of signals`
101			`reg comp_req_pending,`
102			`req_req_pending,`
103			`req_comp_pending,`
104			`req_comp_pending_sample,`
105			`comp_comp_pending,`
106			`req_done_reg,`
107			`comp_done_reg_main,`
108			`comp_done_reg_clr,`
109			`req_rty_exp_reg,`
110			`req_rty_exp_clr,`
111			`comp_rty_exp_reg,`
112			`comp_rty_exp_clr ;`
113
114			`wire sync_comp_req_pending,`
115			`sync_req_comp_pending,`
116			`sync_comp_done,`
117			`sync_req_rty_exp,`
118			`sync_comp_rty_exp_clr ;`
119
120			`// inputs from requesting side - only this side can set address, bus command, byte enables, write enable and burst - outputs are common for both sides`
121			`// all signals that identify requests are stored in this module`
122
123			`input [31:0] addr_in ; // address bus input`
124			`input [3:0] be_in ; // byte enable input`
125			`input we_in ; // write enable input - read/write request indication 1 = write request / 0 = read request`
126			`input [3:0] bc_in ; // bus command input`
127			`input burst_in ; // burst indicator - qualifies operation as burst/single transfer 1 = burst / 0 = single transfer`
128
129			`// common request outputs used both by completing and requesting sides`
130			`// this outputs are not resynchronized, since flags determine the request status`
131			`output [31:0] addr_out ;`
132			`output [3:0] be_out ;`
133			`output we_out ;`
134			`output [3:0] bc_out ;`
135			`output burst_out ;`
136
137			`// completion side signals encoded termination status - 0 = normal completion / 1 = error terminated completion`
138			`input status_in ;`
139			`output status_out ;`
140
141			`// input signals that delayed transaction has been retried for max number of times`
142			`// on this signal request is ditched, otherwise it would cause a deadlock`
143			`// requestor can issue another request and procedure will be repeated`
144			`input retry_expired_in ;`
145
146			`// completion flush output - if in 2^^16 clock cycles transaction is not repeated by requesting agent - flush completion data`
147			`output comp_flush_out ;`
148
149			`// output registers for common signals`
150			`reg [31:0] addr_out ;`
151			`reg [3:0] be_out ;`
152			`reg we_out ;`
153			`reg [3:0] bc_out ;`
154			`reg burst_out ;`
155
156			`// delayed transaction information is stored only when request is issued and request nor completion are pending`
157			`wire new_request = req_in && ~req_comp_pending_out && ~req_req_pending_out ;`
158			`always@(posedge req_clk_in or posedge reset_in)`
159			`begin`
160			`if (reset_in)`
161			`begin`
162			addr_out <= #`FF_DELAY 32'h0000_0000 ;
163			be_out <= #`FF_DELAY 4'h0 ;
164			we_out <= #`FF_DELAY 1'b0 ;
165			bc_out <= #`FF_DELAY `BC_RESERVED0 ;
166			burst_out <= #`FF_DELAY 1'b0 ;
167			`end`
168			`else`
169			`if (new_request)`
170			`begin`
171			addr_out <= #`FF_DELAY addr_in ;
172			be_out <= #`FF_DELAY be_in ;
173			we_out <= #`FF_DELAY we_in ;
174			bc_out <= #`FF_DELAY bc_in ;
175			burst_out <= #`FF_DELAY burst_in ;
176			`end`
177			`end`
178
179			`// completion pending cycle counter`
180			`reg [16:0] comp_cycle_count ;`
181
182			`/*=================================================================================================================================`
183			`Passing of requests between clock domains:`
184			`request originates on requesting side. It's then synchronized with two flip-flops to cross to completing clock domain`
185			`=================================================================================================================================*/`
186			`// main request flip-flop triggered on requesting side's clock`
187			`// request is cleared whenever completion or retry expired is signalled from opposite side of the bridge`
188			`wire req_req_clear = req_comp_pending \|\| (req_rty_exp_reg && ~req_rty_exp_clr) ;`
189			`always@(posedge req_clk_in or posedge reset_in)`
190			`begin`
191			`if ( reset_in )`
192			req_req_pending <= #`FF_DELAY 1'b0 ;
193			`else`
194			`if ( req_req_clear )`
195			req_req_pending <= #`FF_DELAY 1'b0 ;
196			`else`
197			`if ( req_in )`
198			req_req_pending <= #`FF_DELAY 1'b1 ;
199			`end`
200
201			`// interemediate stage request synchronization flip - flop - this one is prone to metastability`
202			`// and should have setup and hold times disabled during simulation`
203			`synchronizer_flop req_sync`
204			`(`
205			`.data_in (req_req_pending),`
206			`.clk_out (comp_clk_in),`
207			`.sync_data_out (sync_comp_req_pending),`
208			`.async_reset (reset_in)`
209			`) ;`
210
211			`// wire for clearing completion side request flag - whenever completion or retry expired are signalled`
212			`wire comp_req_pending_clear = comp_req_pending && ( comp_in \|\| retry_expired_in) ;`
213
214			`// wire for enabling request flip - flop - it is enabled when completion is not active and done is not active`
215			`wire comp_req_pending_ena = ~comp_comp_pending && ~comp_done_reg_main && ~comp_rty_exp_reg ;`
216
217			`// completion side request flip flop - gets a value from intermediate stage sync flip flop`
218			`always@(posedge comp_clk_in or posedge reset_in)`
219			`begin`
220			`if ( reset_in )`
221			comp_req_pending <= #`FF_DELAY 1'b0 ;
222			`else`
223			`if ( comp_req_pending_clear )`
224			comp_req_pending <= #`FF_DELAY 1'b0 ;
225			`else`
226			`if ( comp_req_pending_ena )`
227			comp_req_pending <= #`FF_DELAY sync_comp_req_pending ;
228			`end`
229
230			`// completion side request output assignment - when request ff is set and completion ff is not set`
231			`assign comp_req_pending_out = comp_req_pending ;`
232
233			`// requesting side request pending output`
234			`assign req_req_pending_out = req_req_pending ;`
235			`/*=================================================================================================================================`
236			`Passing of completions between clock domains:`
237			`completion originates on completing side. It's then synchronized with two flip-flops to cross to requesting clock domain`
238			`=================================================================================================================================*/`
239			`// main completion Flip - Flop - triggered by completing side's clock`
240			`// completion side completion pending flag is cleared when done flag propagates through clock domains`
241			`wire comp_comp_clear = comp_done_reg_main && ~comp_done_reg_clr ;`
242			`always@(posedge comp_clk_in or posedge reset_in)`
243			`begin`
244			`if ( reset_in )`
245			comp_comp_pending <= #`FF_DELAY 1'b0 ;
246			`else`
247			`if ( comp_comp_clear )`
248			comp_comp_pending <= #`FF_DELAY 1'b0 ;
249			`else`
250			`if ( comp_in && comp_req_pending )`
251			comp_comp_pending <= #`FF_DELAY 1'b1 ;
252			`end`
253
254			`assign comp_comp_pending_out = comp_comp_pending ;`
255
256			`// interemediate stage completion synchronization flip - flop - this one is prone to metastability`
257			`synchronizer_flop comp_sync`
258			`(`
259			`.data_in (comp_comp_pending),`
260			`.clk_out (req_clk_in),`
261			`.sync_data_out (sync_req_comp_pending),`
262			`.async_reset (reset_in)`
263			`) ;`
264
265			`// request side completion pending flip flop is cleared whenever done is signalled or completion counter expires - 2^^16 clock cycles`
266			`wire req_comp_pending_clear = done_in \|\| comp_cycle_count[16];`
267
268			`// request side completion pending flip flop is disabled while done flag is set`
269			`wire req_comp_pending_ena = ~req_done_reg ;`
270
271			`// request side completion flip flop - gets a value from intermediate stage sync flip flop`
272			`always@(posedge req_clk_in or posedge reset_in)`
273			`begin`
274			`if ( reset_in )`
275			req_comp_pending <= #`FF_DELAY 1'b0 ;
276			`else`
277			`if ( req_comp_pending_clear )`
278			req_comp_pending <= #`FF_DELAY 1'b0 ;
279			`else`
280			`if ( req_comp_pending_ena )`
281			req_comp_pending <= #`FF_DELAY sync_req_comp_pending ;
282			`end`
283
284			`// sampling FF - used for sampling incoming completion flag from completing side`
285			`always@(posedge req_clk_in or posedge reset_in)`
286			`begin`
287			`if ( reset_in )`
288			req_comp_pending_sample <= #`FF_DELAY 1'b0 ;
289			`else`
290			req_comp_pending_sample <= #`FF_DELAY sync_req_comp_pending ;
291			`end`
292
293			`// requesting side completion pending output assignment`
294			`assign req_comp_pending_out = req_comp_pending && ~req_req_pending ;`
295
296			`/*==================================================================================================================================`
297			`Passing of delayed transaction done signal between clock domains.`
298			`Done is signalled by requesting side of the bridge and is passed to completing side of the bridge`
299			`==================================================================================================================================*/`
300			`// main done flip-flop triggered on requesting side's clock`
301			`// when completing side removes completion flag, done flag is also removed, so requests can proceede`
302			`wire req_done_clear = ~req_comp_pending_sample ;`
303			`always@(posedge req_clk_in or posedge reset_in)`
304			`begin`
305			`if ( reset_in )`
306			req_done_reg <= #`FF_DELAY 1'b0 ;
307			`else`
308			`if ( req_done_clear )`
309			req_done_reg <= #`FF_DELAY 1'b0 ;
310			`else`
311			`if ( done_in \|\| comp_cycle_count[16] )`
312			req_done_reg <= #`FF_DELAY 1'b1 ;
313			`end`
314
315			`synchronizer_flop done_sync`
316			`(`
317			`.data_in (req_done_reg),`
318			`.clk_out (comp_clk_in),`
319			`.sync_data_out (sync_comp_done),`
320			`.async_reset (reset_in)`
321			`) ;`
322
323			`always@(posedge comp_clk_in or posedge reset_in)`
324			`begin`
325			`if ( reset_in )`
326			comp_done_reg_main <= #`FF_DELAY 1'b0 ;
327			`else`
328			comp_done_reg_main <= #`FF_DELAY sync_comp_done ;
329			`end`
330
331			`always@(posedge comp_clk_in or posedge reset_in)`
332			`begin`
333			`if ( reset_in )`
334			comp_done_reg_clr <= #`FF_DELAY 1'b0 ;
335			`else`
336			comp_done_reg_clr <= #`FF_DELAY comp_done_reg_main ;
337			`end`
338
339			`/*=================================================================================================================================`
340			`Passing of retry expired signal between clock domains`
341			`Retry expiration originates on completing side. It's then synchronized with two flip-flops to cross to requesting clock domain`
342			`=================================================================================================================================*/`
343			`// main retry expired Flip - Flop - triggered by completing side's clock`
344			`wire comp_rty_exp_clear = comp_rty_exp_clr && comp_rty_exp_reg ;`
345
346			`// retry expired is a special case of transaction removal - retry expired propagates from completing`
347			`// clock domain to requesting clock domain to remove all pending requests and than propagates back`
348			`// to completing side to qualify valid new requests`
349
350			`always@(posedge comp_clk_in or posedge reset_in)`
351			`begin`
352			`if ( reset_in )`
353			comp_rty_exp_reg <= #`FF_DELAY 1'b0 ;
354			`else`
355			`if ( comp_rty_exp_clear )`
356			comp_rty_exp_reg <= #`FF_DELAY 1'b0 ;
357			`else`
358			`if ( retry_expired_in && comp_req_pending)`
359			comp_rty_exp_reg <= #`FF_DELAY 1'b1 ;
360			`end`
361
362			`// interemediate stage retry expired synchronization flip - flop - this one is prone to metastability`
363			`synchronizer_flop rty_exp_sync`
364			`(`
365			`.data_in (comp_rty_exp_reg),`
366			`.clk_out (req_clk_in),`
367			`.sync_data_out (sync_req_rty_exp),`
368			`.async_reset (reset_in)`
369			`) ;`
370
371			`// request retry expired flip flop - gets a value from intermediate stage sync flip flop`
372			`always@(posedge req_clk_in or posedge reset_in)`
373			`begin`
374			`if ( reset_in )`
375			req_rty_exp_reg <= #`FF_DELAY 1'b0 ;
376			`else`
377			req_rty_exp_reg <= #`FF_DELAY sync_req_rty_exp ;
378			`end`
379
380			`always@(posedge req_clk_in or posedge reset_in)`
381			`begin`
382			`if ( reset_in )`
383			req_rty_exp_clr <= #`FF_DELAY 1'b0 ;
384			`else`
385			req_rty_exp_clr <= #`FF_DELAY req_rty_exp_reg ;
386			`end`
387
388			`synchronizer_flop rty_exp_back_prop_sync`
389			`(`
390			`.data_in (req_rty_exp_reg),`
391			`.clk_out (comp_clk_in),`
392			`.sync_data_out (sync_comp_rty_exp_clr),`
393			`.async_reset (reset_in)`
394			`) ;`
395
396			`always@(posedge comp_clk_in or posedge reset_in)`
397			`begin`
398			`if ( reset_in )`
399			comp_rty_exp_clr <= #`FF_DELAY 1'b0 ;
400			`else`
401			comp_rty_exp_clr <= #`FF_DELAY sync_comp_rty_exp_clr ;
402			`end`
403
404			`// completion status flip flop - if 0 when completion is signalled it's finished OK otherwise it means error`
405			`reg status_out ;`
406			`always@(posedge comp_clk_in or posedge reset_in)`
407			`begin`
408			`if (reset_in)`
409			status_out <= #`FF_DELAY 1'b0 ;
410			`else`
411			`if (comp_in && comp_req_pending)`
412			status_out <= #`FF_DELAY status_in ;
413			`end`
414
415			`// clocks counter - it counts how many clock cycles completion is present without beeing repeated`
416			`// if it counts to 2^^16 cycles the completion must be ditched`
417
418			`// wire for clearing this counter`
419			`wire clear_count = in_progress_in \|\| ~req_comp_pending_out ;`
420			`always@(posedge req_clk_in or posedge reset_in)`
421			`begin`
422			`if (reset_in)`
423			comp_cycle_count <= #`FF_DELAY 17'h0_0000 ;
424			`else`
425			`if (clear_count)`
426			comp_cycle_count <= #`FF_DELAY 17'h0_0000 ;
427			`else`
428			comp_cycle_count <= #`FF_DELAY comp_cycle_count + 1'b1 ;
429			`end`
430
431			`// completion flush output - used for flushing fifos when counter expires`
432			`// if counter doesn't expire, fifo flush is up to WISHBONE slave or PCI target state machines`
433			`reg comp_flush_out ;`
434			`always@(posedge req_clk_in or posedge reset_in)`
435			`begin`
436			`if (reset_in)`
437			comp_flush_out <= #`FF_DELAY 1'b0 ;
438			`else`
439			comp_flush_out <= #`FF_DELAY comp_cycle_count[16] ;
440			`end`
441
442			`endmodule //delayed_sync`