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[/] [pci/] [tags/] [working_demo/] [rtl/] [verilog/] [dp_sram.v] - Blame information for rev 154

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  File name "dp_sram.v"                                       ////
////                                                              ////
////  This file is part of the "PCI bridge" project               ////
////  http://www.opencores.org/cores/pci/                         ////
////                                                              ////
////  Author(s):                                                  ////
////      - mihad@opencores.org                                   ////
////      - Miha Dolenc                                           ////
////                                                              ////
////  All additional information is avaliable in the README.pdf   ////
////  file.                                                       ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Miha Dolenc, mihad@opencores.org          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1  2001/10/02 15:33:46  mihad
// New project directory structure
//
// Revision 1.1  2001/08/06 18:12:43  mihad
// Pocasi delamo kompletno zadevo
//
//
 
`include "constants.v"
`include "timescale.v"
 
// behavioral syncronous read / syncronous write RAM
module DP_SRAM(reset_in, wclock_in, rclock_in, data_in, raddr_in, waddr_in, data_out, renable_in, wenable_in);
 
parameter ADDR_LENGTH = 7 ;
parameter SIZE = 128 ;
input reset_in ;
input wclock_in ;
input rclock_in ;
input [39:0] data_in ;
input [(ADDR_LENGTH - 1):0] raddr_in ;
input [(ADDR_LENGTH - 1):0] waddr_in ;
output [39:0] data_out ;
input renable_in ;
input wenable_in ;
 
reg [39:0] mem [(SIZE - 1):0] ;
wire [(ADDR_LENGTH - 1):0] raddr = raddr_in ;
wire [(ADDR_LENGTH - 1):0] waddr = waddr_in ;
 
reg [39:0] out_data ;
 
assign data_out = out_data ;
 
always@(posedge rclock_in or posedge reset_in)
begin
    if(reset_in)
        out_data <= #`FF_DELAY 40'h0000000000 ;
    else if (renable_in)
        out_data <= #`FF_DELAY mem[raddr] ;
end
 
always@(posedge wclock_in)
begin
    if (wenable_in)
        mem[waddr] <= #`FF_DELAY data_in ;
end
 
endmodule

Line No.	Rev	Author	Line
1	2	mihad	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// File name "dp_sram.v" ////`
4			`//// ////`
5			`//// This file is part of the "PCI bridge" project ////`
6			`//// http://www.opencores.org/cores/pci/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - mihad@opencores.org ////`
10			`//// - Miha Dolenc ////`
11			`//// ////`
12			`//// All additional information is avaliable in the README.pdf ////`
13			`//// file. ////`
14			`//// ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2000 Miha Dolenc, mihad@opencores.org ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42			`//`
43			`// CVS Revision History`
44			`//`
45			`// $Log: not supported by cvs2svn $`
46	6	mihad	`// Revision 1.1.1.1 2001/10/02 15:33:46 mihad`
47			`// New project directory structure`
48			`//`
49	2	mihad	`// Revision 1.1 2001/08/06 18:12:43 mihad`
50			`// Pocasi delamo kompletno zadevo`
51			`//`
52			`//`
53
54			`include "constants.v"
55	6	mihad	`include "timescale.v"
56
57	2	mihad	`// behavioral syncronous read / syncronous write RAM`
58			`module DP_SRAM(reset_in, wclock_in, rclock_in, data_in, raddr_in, waddr_in, data_out, renable_in, wenable_in);`
59
60			`parameter ADDR_LENGTH = 7 ;`
61			`parameter SIZE = 128 ;`
62			`input reset_in ;`
63			`input wclock_in ;`
64			`input rclock_in ;`
65			`input [39:0] data_in ;`
66			`input [(ADDR_LENGTH - 1):0] raddr_in ;`
67			`input [(ADDR_LENGTH - 1):0] waddr_in ;`
68			`output [39:0] data_out ;`
69			`input renable_in ;`
70			`input wenable_in ;`
71
72			`reg [39:0] mem [(SIZE - 1):0] ;`
73			`wire [(ADDR_LENGTH - 1):0] raddr = raddr_in ;`
74			`wire [(ADDR_LENGTH - 1):0] waddr = waddr_in ;`
75
76			`reg [39:0] out_data ;`
77
78			`assign data_out = out_data ;`
79
80			`always@(posedge rclock_in or posedge reset_in)`
81			`begin`
82			`if(reset_in)`
83			out_data <= #`FF_DELAY 40'h0000000000 ;
84			`else if (renable_in)`
85			out_data <= #`FF_DELAY mem[raddr] ;
86			`end`
87
88			`always@(posedge wclock_in)`
89			`begin`
90			`if (wenable_in)`
91			mem[waddr] <= #`FF_DELAY data_in ;
92			`end`
93
94			`endmodule`

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[/] [pci/] [tags/] [working_demo/] [rtl/] [verilog/] [dp_sram.v] - Blame information for rev 154