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[/] [pci/] [tags/] [working_demo/] [rtl/] [verilog/] [pci_target32_interface.v] - Blame information for rev 154

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1 2 mihad 
//////////////////////////////////////////////////////////////////////
2 
////                                                              ////
3 
////  File name: pci_target32_interface.v                         ////
4 
////                                                              ////
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////  This file is part of the "PCI bridge" project               ////
6 
////  http://www.opencores.org/cores/pci/                         ////
7 
////                                                              ////
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////  Author(s):                                                  ////
9 
////      - Tadej Markovic, tadej@opencores.org                   ////
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////                                                              ////
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////  All additional information is avaliable in the README.txt   ////
12 
////  file.                                                       ////
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////                                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Tadej Markovic, tadej@opencores.org       ////
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////                                                              ////
19 
//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
21 
//// removed from the file and that any derivative work contains  ////
22 
//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
27 
//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
41 
//
42 
// CVS Revision History
43 
//
44 
// $Log: not supported by cvs2svn $
45 6 mihad 
// Revision 1.1.1.1  2001/10/02 15:33:47  mihad
46 
// New project directory structure
47 2 mihad 
//
48 6 mihad 
//
49 2 mihad 
 
50 
`include "bus_commands.v"
51 
`include "constants.v"
52 6 mihad 
`include "timescale.v"
53 2 mihad 
 
54 
module PCI_TARGET32_INTERFACE
55 
(
56 
    // system inputs
57 
    clk_in,
58 
    reset_in,
59 
 
60 
    // PCI Target side of INTERFACE
61 
    address_in,
62 
    addr_claim_out,
63 
    bc_in,
64 
    bc0_in,
65 
    data_in,
66 
    data_out,
67 
    be_in,
68 
    req_in,
69 
    rdy_in,
70 
    addr_phase_in,
71 
    bckp_trdy_in,
72 
    last_reg_in,
73 
    frame_reg_in,
74 
    fetch_pcir_fifo_in,
75 
    load_medium_reg_in,
76 
    sel_fifo_mreg_in,
77 
    sel_conf_fifo_in,
78 
    fetch_conf_in,
79 
    load_to_pciw_fifo_in,
80 
    load_to_conf_in,
81 
    same_read_out,
82 
 
83 
        norm_access_to_config_out,
84 
        read_completed_out,
85 
        read_processing_out,
86 
        target_abort_out,
87 
        disconect_wo_data_out,
88 
        pciw_fifo_full_out,
89 
        pcir_fifo_data_err_out,
90 
        wbw_fifo_empty_out,
91 
 
92 
        // Delayed synchronizacion module signals
93 
        req_out,
94 
    done_out,
95 
    in_progress_out,
96 
        req_req_pending_in,
97 
    req_comp_pending_in,
98 
        addr_out,
99 
    be_out,
100 
    we_out,
101 
    bc_out,
102 
    burst_out,
103 
        strd_addr_in,
104 
        strd_bc_in,
105 
    status_in,
106 
    comp_flush_in,
107 
 
108 
        // FIFO signals
109 
        pcir_fifo_renable_out,
110 
        pcir_fifo_data_in,
111 
        pcir_fifo_be_in,
112 
        pcir_fifo_control_in,
113 
        pcir_fifo_flush_out,
114 
        pcir_fifo_almost_empty_in,
115 
        pcir_fifo_empty_in,
116 
        pciw_fifo_wenable_out,
117 
        pciw_fifo_addr_data_out,
118 
        pciw_fifo_cbe_out,
119 
        pciw_fifo_control_out,
120 
        pciw_fifo_two_left_in,
121 
        pciw_fifo_almost_full_in,
122 
        pciw_fifo_full_in,
123 
        wbw_fifo_empty_in,
124 
 
125 
        // Configuration space signals
126 
        conf_hit_out,
127 
        conf_addr_out,
128 
        conf_data_out,
129 
        conf_data_in,
130 
        conf_be_out,
131 
        conf_we_out,
132 
        conf_re_out,
133 
        mem_enable_in,
134 
        io_enable_in,
135 
        mem_io_addr_space0_in,
136 
        mem_io_addr_space1_in,
137 
        mem_io_addr_space2_in,
138 
        mem_io_addr_space3_in,
139 
        mem_io_addr_space4_in,
140 
        mem_io_addr_space5_in,
141 
        pre_fetch_en0_in,
142 
        pre_fetch_en1_in,
143 
        pre_fetch_en2_in,
144 
        pre_fetch_en3_in,
145 
        pre_fetch_en4_in,
146 
        pre_fetch_en5_in,
147 
        pci_base_addr0_in,
148 
        pci_base_addr1_in,
149 
        pci_base_addr2_in,
150 
        pci_base_addr3_in,
151 
        pci_base_addr4_in,
152 
        pci_base_addr5_in,
153 
        pci_addr_mask0_in,
154 
        pci_addr_mask1_in,
155 
        pci_addr_mask2_in,
156 
        pci_addr_mask3_in,
157 
        pci_addr_mask4_in,
158 
        pci_addr_mask5_in,
159 
        pci_tran_addr0_in,
160 
        pci_tran_addr1_in,
161 
        pci_tran_addr2_in,
162 
        pci_tran_addr3_in,
163 
        pci_tran_addr4_in,
164 
        pci_tran_addr5_in,
165 
        addr_tran_en0_in,
166 
        addr_tran_en1_in,
167 
        addr_tran_en2_in,
168 
        addr_tran_en3_in,
169 
        addr_tran_en4_in,
170 
        addr_tran_en5_in
171 
) ;
172 
 
173 
/*==================================================================================================================
174 
System inputs.
175 
==================================================================================================================*/
176 
// PCI side clock and reset
177 
input   clk_in,
178 
        reset_in ;
179 
 
180 
 
181 
/*==================================================================================================================
182 
Side of the PCI Target state machine
183 
==================================================================================================================*/
184 
// Data, byte enables, bus commands and address ports
185 
input   [31:0]   address_in ;            // current request address input - registered
186 
output          addr_claim_out ;        // current request address claim output
187 
input   [3:0]   bc_in ;                          // current request bus command input - registered
188 
input                   bc0_in ;                        // current cycle RW signal
189 
output  [31:0]  data_out ;                       // for read operations - current dataphase data output
190 
input   [31:0]  data_in ;                        // for write operations - current request data input - registered
191 
input   [3:0]    be_in ;                         // current dataphase byte enable inputs - registered
192 
// Port connection control signals from PCI FSM
193 
input           req_in ;                // Read is requested to WB master from PCI side
194 
input           rdy_in ;                // DATA / ADDRESS selection from PCI side when read or write - registered
195 
input                   addr_phase_in ;         // Indicates address phase and also fast-back-to-back address phase - registered
196 
input                   bckp_trdy_in ;          // TRDY output (which is registered) equivalent
197 
input               last_reg_in ;               // Indicates last data phase - registered
198 
input                   frame_reg_in ;          // FRAME input signal - registered
199 
input               fetch_pcir_fifo_in ;// Read enable for PCIR_FIFO when when read is finishen on WB side
200 
input               load_medium_reg_in ;// Load data from PCIR_FIFO to medium register (first data must be prepared on time)
201 
input               sel_fifo_mreg_in ;  // Read data selection between PCIR_FIFO and medium register
202 
input               sel_conf_fifo_in ;  // Read data selection between Configuration registers and "FIFO"
203 
input               fetch_conf_in ;             // Read enable for configuration space registers
204 
input               load_to_pciw_fifo_in ;// Write enable to PCIW_FIFO
205 
input               load_to_conf_in ;   // Write enable to Configuration space registers
206 
 
207 
 
208 
/*==================================================================================================================
209 
Status outputs to PCI side (FSM)
210 
==================================================================================================================*/
211 
output                  same_read_out ;                         // Indicates the same read request (important when read is finished on WB side)
212 
output                  norm_access_to_config_out ;     // Indicates the access to Configuration space with MEMORY commands
213 
output                  read_completed_out ;            // Indicates that read request is completed on WB side
214 
output                  read_processing_out ;           // Indicates that read request is processing on WB side
215 
output                  target_abort_out ;                      // Indicates target abort termination
216 
output                  disconect_wo_data_out ;         // Indicates disconnect with OR without data termination
217 
output                  pciw_fifo_full_out ;            // Indicates that write PCIW_FIFO is full
218 
output                  pcir_fifo_data_err_out ;        // Indicates data error on current data read from PCIR_FIFO
219 
output                  wbw_fifo_empty_out ;            // Indicates that WB SLAVE has no data to be written to PCI bus
220 
 
221 
 
222 
/*==================================================================================================================
223 
Read request interface through Delayed sinchronization module to WB Master
224 
==================================================================================================================*/
225 
// request, completion, done and progress indicator outputs for delayed_sync module where they are synchronized
226 
output                  req_out,                // request qualifier - when 1 it indicates that valid data is provided on outputs
227 
                        done_out,               // done output - when 1 indicates that PCI Target has completed a cycle on its bus
228 
                        in_progress_out ;       // out progress indicator - indicates that current completion is in progress on
229 
                                                                        //   PCI Target side
230 
// pending indication inputs - PCI Target side must know about requests and completions
231 
input                   req_req_pending_in ;    // request pending input for PCI Target side
232 
input                   req_comp_pending_in ;   // completion pending input for PCI Target side - it indicates when completion
233 
                                                                                //   is ready for completing on PCI Target bus
234 
// various data outputs - PCI Target sets address, bus command, byte enables, write enable and burst
235 
output  [31:0]   addr_out ;   // address bus output
236 
output  [3:0]    be_out ;     // byte enable output
237 
output          we_out ;     // write enable output - read/write request indication 1 = write request / 0 = read request
238 
output  [3:0]    bc_out ;     // bus command output
239 
output                  burst_out ;  // pre-fetch enable & burst read - qualifies pre-fetch for access to current image space
240 
 
241 
// completion side signals encoded termination status - 0 = normal completion / 1 = error terminated completion
242 
input   [31:0]   strd_addr_in ;  // Stored requested read access address
243 
input   [3:0]    strd_bc_in ;    // Stored requested read access bus command
244 
input                   status_in ;     // Error status reported - NOT USED because FIFO control bits determin data error status
245 
input               comp_flush_in ;     // If completition counter (2^16 clk periods) has expired, PCIR_FIFO must flush data
246 
 
247 
 
248 
/*==================================================================================================================
249 
PCIR_PCIW_FIFO signals from pci side
250 
==================================================================================================================*/
251 
// PCIR_FIFO control signals used for fetching data from PCIR_FIFO
252 
output                  pcir_fifo_renable_out ;                 // read enable output to PCIR_FIFO
253 
input   [31:0]   pcir_fifo_data_in ;                             // data input from PCIR_FIFO
254 
input   [3:0]    pcir_fifo_be_in ;                               // byte enable input from PCIR_FIFO
255 
input   [3:0]    pcir_fifo_control_in ;                  // control signals input from PCIR_FIFO
256 
output                  pcir_fifo_flush_out ;                   // flush PCIR_FIFO
257 
input                   pcir_fifo_almost_empty_in ;             // almost empty indicator from PCIR_FIFO
258 
input                   pcir_fifo_empty_in ;                    // empty indicator
259 
 
260 
// PCIW_FIFO control signals used for sinking data into PCIW_FIFO and status monitoring
261 
output                  pciw_fifo_wenable_out ;         // write enable output to PCIW_FIFO
262 
output  [31:0]   pciw_fifo_addr_data_out ;       // address / data output signals to PCIW_FIFO
263 
output  [3:0]    pciw_fifo_cbe_out ;                     // command / byte enable signals to PCIW_FIFO
264 
output  [3:0]    pciw_fifo_control_out ;         // control signals to PCIW_FIFO
265 
input                   pciw_fifo_two_left_in ;         // two data spaces left in PCIW_FIFO
266 
input                   pciw_fifo_almost_full_in ;      // almost full indicator from PCIW_FIFO
267 
input                   pciw_fifo_full_in ;                     // full indicator from PCIW_FIFO
268 
 
269 
// WBW_FIFO empy control signal used when delayed read is complete in PCIR_FIFO
270 
input                   wbw_fifo_empty_in ;                     // empty indicator from WBW_FIFO
271 
 
272 
 
273 
/*==================================================================================================================
274 
Configuration space signals - from and to registers
275 
==================================================================================================================*/
276 
// BUS for reading and writing to configuration space registers
277 
output                  conf_hit_out ;  // like "chip select" for configuration space
278 
output  [11:0]   conf_addr_out ; // address to configuration space when there is access to it
279 
output  [31:0]   conf_data_out ; // data to configuration space - for writing to registers
280 
input   [31:0]   conf_data_in ;  // data from configuration space - for reading from registers
281 
output  [3:0]    conf_be_out ;   // byte enables used for correct writing to configuration space
282 
output                  conf_we_out ;   // write enable control signal - 1 for writing / 0 for nothing
283 
output                  conf_re_out ;   // read enable control signal - 1 for reading / 0 for nothing
284 
 
285 
// Inputs for image control registers
286 
input                   mem_enable_in ; // allowed access to memory mapped image
287 
input                   io_enable_in ;  // allowed access to io mapped image
288 
 
289 
// Inputs needed for determining if image is assigned to memory or io space with pre-fetch and address translation
290 
input                   mem_io_addr_space0_in ; // bit-0 in pci_base_addr0 register
291 
input                   mem_io_addr_space1_in ; // bit-0 in pci_base_addr1 register
292 
input                   mem_io_addr_space2_in ; // bit-0 in pci_base_addr2 register
293 
input                   mem_io_addr_space3_in ; // bit-0 in pci_base_addr3 register
294 
input                   mem_io_addr_space4_in ; // bit-0 in pci_base_addr4 register
295 
input                   mem_io_addr_space5_in ; // bit-0 in pci_base_addr5 register
296 
input                   pre_fetch_en0_in ;      // bit-1 in pci_image_ctr0 register
297 
input                   pre_fetch_en1_in ;      // bit-1 in pci_image_ctr1 register
298 
input                   pre_fetch_en2_in ;      // bit-1 in pci_image_ctr2 register
299 
input                   pre_fetch_en3_in ;      // bit-1 in pci_image_ctr3 register
300 
input                   pre_fetch_en4_in ;      // bit-1 in pci_image_ctr4 register
301 
input                   pre_fetch_en5_in ;      // bit-1 in pci_image_ctr5 register
302 
 
303 
// Input from image registers - register values needed for decoder to work properly
304 
input   [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)]    pci_base_addr0_in ;     // base address from base address register
305 
input   [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)]    pci_base_addr1_in ; // base address from base address register
306 
input   [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)]    pci_base_addr2_in ; // base address from base address register
307 
input   [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)]    pci_base_addr3_in ; // base address from base address register
308 
input   [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)]    pci_base_addr4_in ; // base address from base address register
309 
input   [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)]    pci_base_addr5_in ; // base address from base address register
310 
input   [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)]    pci_addr_mask0_in ; // masking of base address from address mask register
311 
input   [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)]    pci_addr_mask1_in ; // masking of base address from address mask register
312 
input   [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)]    pci_addr_mask2_in ; // masking of base address from address mask register
313 
input   [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)]    pci_addr_mask3_in ; // masking of base address from address mask register
314 
input   [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)]    pci_addr_mask4_in ; // masking of base address from address mask register
315 
input   [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)]    pci_addr_mask5_in ; // masking of base address from address mask register
316 
input   [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)]    pci_tran_addr0_in ; // translation address from address translation register
317 
input   [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)]    pci_tran_addr1_in ; // translation address from address translation register
318 
input   [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)]    pci_tran_addr2_in ; // translation address from address translation register
319 
input   [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)]    pci_tran_addr3_in ; // translation address from address translation register
320 
input   [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)]    pci_tran_addr4_in ; // translation address from address translation register
321 
input   [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)]    pci_tran_addr5_in ; // translation address from address translation register
322 
 
323 
input                   addr_tran_en0_in ;      // address translation enable bit
324 
input                   addr_tran_en1_in ;      // address translation enable bit
325 
input                   addr_tran_en2_in ;      // address translation enable bit
326 
input                   addr_tran_en3_in ;      // address translation enable bit
327 
input                   addr_tran_en4_in ;      // address translation enable bit
328 
input                   addr_tran_en5_in ;      // address translation enable bit
329 
 
330 
/*==================================================================================================================
331 
END of input / output PORT DEFINITONS !!!
332 
==================================================================================================================*/
333 
 
334 
// address output from address multiplexer
335 
reg             [31:0]   address ;
336 
// prefetch enable for access to selected image space
337 
reg                             pre_fetch_en ;
338 
 
339 
// Input addresses and image hits from address decoders - addresses are multiplexed to address
340 
wire                    hit0_in ;
341 
wire    [31:0]   address0_in ;
342 
wire                    hit1_in ;
343 
wire    [31:0]   address1_in ;
344 
`ifdef          PCI_IMAGE2
345 
wire                    hit2_in ;
346 
wire    [31:0]   address2_in ;
347 
`endif
348 
`ifdef          PCI_IMAGE3
349 
wire                    hit2_in ;
350 
wire    [31:0]   address2_in ;
351 
wire                    hit3_in ;
352 
wire    [31:0]   address3_in ;
353 
`endif
354 
`ifdef          PCI_IMAGE4
355 
wire                    hit2_in ;
356 
wire    [31:0]   address2_in ;
357 
wire                    hit3_in ;
358 
wire    [31:0]   address3_in ;
359 
wire                    hit4_in ;
360 
wire    [31:0]   address4_in ;
361 
`endif
362 
`ifdef          PCI_IMAGE5
363 
wire                    hit2_in ;
364 
wire    [31:0]   address2_in ;
365 
wire                    hit3_in ;
366 
wire    [31:0]   address3_in ;
367 
wire                    hit4_in ;
368 
wire    [31:0]   address4_in ;
369 
wire                    hit5_in ;
370 
wire    [31:0]   address5_in ;
371 
`endif
372 
`ifdef          PCI_IMAGE6
373 
wire                    hit2_in ;
374 
wire    [31:0]   address2_in ;
375 
wire                    hit3_in ;
376 
wire    [31:0]   address3_in ;
377 
wire                    hit4_in ;
378 
wire    [31:0]   address4_in ;
379 
wire                    hit5_in ;
380 
wire    [31:0]   address5_in ;
381 
`endif
382 
 
383 
// Include address decoders
384 
        PCI_DECODER   #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder0
385 
                                   (.hit                        (hit0_in),
386 
                                        .addr_out               (address0_in),
387 
                                        .addr_in                (address_in),
388 
                                        .base_addr              (pci_base_addr0_in),
389 
                                        .mask_addr              (pci_addr_mask0_in),
390 
                                        .tran_addr              (pci_tran_addr0_in),
391 
                                        .at_en                  (addr_tran_en0_in),
392 
                                        .mem_io_space   (mem_io_addr_space0_in),
393 
                                        .mem_en                 (mem_enable_in),
394 
                                        .io_en                  (io_enable_in)
395 
                                        ) ;
396 
        PCI_DECODER   #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder1
397 
                                   (.hit                        (hit1_in),
398 
                                        .addr_out               (address1_in),
399 
                                        .addr_in                (address_in),
400 
                                        .base_addr              (pci_base_addr1_in),
401 
                                        .mask_addr              (pci_addr_mask1_in),
402 
                                        .tran_addr              (pci_tran_addr1_in),
403 
                                        .at_en                  (addr_tran_en1_in),
404 
                                        .mem_io_space   (mem_io_addr_space1_in),
405 
                                        .mem_en                 (mem_enable_in),
406 
                                        .io_en                  (io_enable_in)
407 
                                        ) ;
408 
`ifdef          PCI_IMAGE2
409 
        PCI_DECODER   #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder2
410 
                                   (.hit                        (hit2_in),
411 
                                        .addr_out               (address2_in),
412 
                                        .addr_in                (address_in),
413 
                                        .base_addr              (pci_base_addr2_in),
414 
                                        .mask_addr              (pci_addr_mask2_in),
415 
                                        .tran_addr              (pci_tran_addr2_in),
416 
                                        .at_en                  (addr_tran_en2_in),
417 
                                        .mem_io_space   (mem_io_addr_space2_in),
418 
                                        .mem_en                 (mem_enable_in),
419 
                                        .io_en                  (io_enable_in)
420 
                                        ) ;
421 
`endif
422 
`ifdef          PCI_IMAGE3
423 
        PCI_DECODER   #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder2
424 
                                   (.hit                        (hit2_in),
425 
                                        .addr_out               (address2_in),
426 
                                        .addr_in                (address_in),
427 
                                        .base_addr              (pci_base_addr2_in),
428 
                                        .mask_addr              (pci_addr_mask2_in),
429 
                                        .tran_addr              (pci_tran_addr2_in),
430 
                                        .at_en                  (addr_tran_en2_in),
431 
                                        .mem_io_space   (mem_io_addr_space2_in),
432 
                                        .mem_en                 (mem_enable_in),
433 
                                        .io_en                  (io_enable_in)
434 
                                        ) ;
435 
        PCI_DECODER   #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder3
436 
                                   (.hit                        (hit3_in),
437 
                                        .addr_out               (address3_in),
438 
                                        .addr_in                (address_in),
439 
                                        .base_addr              (pci_base_addr3_in),
440 
                                        .mask_addr              (pci_addr_mask3_in),
441 
                                        .tran_addr              (pci_tran_addr3_in),
442 
                                        .at_en                  (addr_tran_en3_in),
443 
                                        .mem_io_space   (mem_io_addr_space3_in),
444 
                                        .mem_en                 (mem_enable_in),
445 
                                        .io_en                  (io_enable_in)
446 
                                        ) ;
447 
`endif
448 
`ifdef          PCI_IMAGE4
449 
        PCI_DECODER   #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder2
450 
                                   (.hit                        (hit2_in),
451 
                                        .addr_out               (address2_in),
452 
                                        .addr_in                (address_in),
453 
                                        .base_addr              (pci_base_addr2_in),
454 
                                        .mask_addr              (pci_addr_mask2_in),
455 
                                        .tran_addr              (pci_tran_addr2_in),
456 
                                        .at_en                  (addr_tran_en2_in),
457 
                                        .mem_io_space   (mem_io_addr_space2_in),
458 
                                        .mem_en                 (mem_enable_in),
459 
                                        .io_en                  (io_enable_in)
460 
                                        ) ;
461 
        PCI_DECODER   #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder3
462 
                                   (.hit                        (hit3_in),
463 
                                        .addr_out               (address3_in),
464 
                                        .addr_in                (address_in),
465 
                                        .base_addr              (pci_base_addr3_in),
466 
                                        .mask_addr              (pci_addr_mask3_in),
467 
                                        .tran_addr              (pci_tran_addr3_in),
468 
                                        .at_en                  (addr_tran_en3_in),
469 
                                        .mem_io_space   (mem_io_addr_space3_in),
470 
                                        .mem_en                 (mem_enable_in),
471 
                                        .io_en                  (io_enable_in)
472 
                                        ) ;
473 
        PCI_DECODER   #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder4
474 
                                   (.hit                        (hit4_in),
475 
                                        .addr_out               (address4_in),
476 
                                        .addr_in                (address_in),
477 
                                        .base_addr              (pci_base_addr4_in),
478 
                                        .mask_addr              (pci_addr_mask4_in),
479 
                                        .tran_addr              (pci_tran_addr4_in),
480 
                                        .at_en                  (addr_tran_en4_in),
481 
                                        .mem_io_space   (mem_io_addr_space4_in),
482 
                                        .mem_en                 (mem_enable_in),
483 
                                        .io_en                  (io_enable_in)
484 
                                        ) ;
485 
`endif
486 
`ifdef          PCI_IMAGE5
487 
        PCI_DECODER   #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder2
488 
                                   (.hit                        (hit2_in),
489 
                                        .addr_out               (address2_in),
490 
                                        .addr_in                (address_in),
491 
                                        .base_addr              (pci_base_addr2_in),
492 
                                        .mask_addr              (pci_addr_mask2_in),
493 
                                        .tran_addr              (pci_tran_addr2_in),
494 
                                        .at_en                  (addr_tran_en2_in),
495 
                                        .mem_io_space   (mem_io_addr_space2_in),
496 
                                        .mem_en                 (mem_enable_in),
497 
                                        .io_en                  (io_enable_in)
498 
                                        ) ;
499 
        PCI_DECODER   #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder3
500 
                                   (.hit                        (hit3_in),
501 
                                        .addr_out               (address3_in),
502 
                                        .addr_in                (address_in),
503 
                                        .base_addr              (pci_base_addr3_in),
504 
                                        .mask_addr              (pci_addr_mask3_in),
505 
                                        .tran_addr              (pci_tran_addr3_in),
506 
                                        .at_en                  (addr_tran_en3_in),
507 
                                        .mem_io_space   (mem_io_addr_space3_in),
508 
                                        .mem_en                 (mem_enable_in),
509 
                                        .io_en                  (io_enable_in)
510 
                                        ) ;
511 
        PCI_DECODER   #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder4
512 
                                   (.hit                        (hit4_in),
513 
                                        .addr_out               (address4_in),
514 
                                        .addr_in                (address_in),
515 
                                        .base_addr              (pci_base_addr4_in),
516 
                                        .mask_addr              (pci_addr_mask4_in),
517 
                                        .tran_addr              (pci_tran_addr4_in),
518 
                                        .at_en                  (addr_tran_en4_in),
519 
                                        .mem_io_space   (mem_io_addr_space4_in),
520 
                                        .mem_en                 (mem_enable_in),
521 
                                        .io_en                  (io_enable_in)
522 
                                        ) ;
523 
        PCI_DECODER   #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder5
524 
                                   (.hit                        (hit5_in),
525 
                                        .addr_out               (address5_in),
526 
                                        .addr_in                (address_in),
527 
                                        .base_addr              (pci_base_addr5_in),
528 
                                        .mask_addr              (pci_addr_mask5_in),
529 
                                        .tran_addr              (pci_tran_addr5_in),
530 
                                        .at_en                  (addr_tran_en5_in),
531 
                                        .mem_io_space   (mem_io_addr_space5_in),
532 
                                        .mem_en                 (mem_enable_in),
533 
                                        .io_en                  (io_enable_in)
534 
                                        ) ;
535 
`endif
536 
`ifdef          PCI_IMAGE6
537 
        PCI_DECODER   #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder2
538 
                                   (.hit                        (hit2_in),
539 
                                        .addr_out               (address2_in),
540 
                                        .addr_in                (address_in),
541 
                                        .base_addr              (pci_base_addr2_in),
542 
                                        .mask_addr              (pci_addr_mask2_in),
543 
                                        .tran_addr              (pci_tran_addr2_in),
544 
                                        .at_en                  (addr_tran_en2_in),
545 
                                        .mem_io_space   (mem_io_addr_space2_in),
546 
                                        .mem_en                 (mem_enable_in),
547 
                                        .io_en                  (io_enable_in)
548 
                                        ) ;
549 
        PCI_DECODER   #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder3
550 
                                   (.hit                        (hit3_in),
551 
                                        .addr_out               (address3_in),
552 
                                        .addr_in                (address_in),
553 
                                        .base_addr              (pci_base_addr3_in),
554 
                                        .mask_addr              (pci_addr_mask3_in),
555 
                                        .tran_addr              (pci_tran_addr3_in),
556 
                                        .at_en                  (addr_tran_en3_in),
557 
                                        .mem_io_space   (mem_io_addr_space3_in),
558 
                                        .mem_en                 (mem_enable_in),
559 
                                        .io_en                  (io_enable_in)
560 
                                        ) ;
561 
        PCI_DECODER   #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder4
562 
                                   (.hit                        (hit4_in),
563 
                                        .addr_out               (address4_in),
564 
                                        .addr_in                (address_in),
565 
                                        .base_addr              (pci_base_addr4_in),
566 
                                        .mask_addr              (pci_addr_mask4_in),
567 
                                        .tran_addr              (pci_tran_addr4_in),
568 
                                        .at_en                  (addr_tran_en4_in),
569 
                                        .mem_io_space   (mem_io_addr_space4_in),
570 
                                        .mem_en                 (mem_enable_in),
571 
                                        .io_en                  (io_enable_in)
572 
                                        ) ;
573 
        PCI_DECODER   #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder5
574 
                                   (.hit                        (hit5_in),
575 
                                        .addr_out               (address5_in),
576 
                                        .addr_in                (address_in),
577 
                                        .base_addr              (pci_base_addr5_in),
578 
                                        .mask_addr              (pci_addr_mask5_in),
579 
                                        .tran_addr              (pci_tran_addr5_in),
580 
                                        .at_en                  (addr_tran_en5_in),
581 
                                        .mem_io_space   (mem_io_addr_space5_in),
582 
                                        .mem_en                 (mem_enable_in),
583 
                                        .io_en                  (io_enable_in)
584 
                                        ) ;
585 
`endif
586 
 
587 
// Internal signals for image hit determination
588 
reg                             addr_claim ;// address claim signal is asinchronous set for addr_claim_out signal to PCI Target SM
589 
 
590 
// Determining if image 0 is assigned to configuration space or as normal pci to wb access!
591 
//   if normal access is allowed to configuration space, then hit0 is hit0_conf
592 
`ifdef          HOST
593 
        `ifdef  PCI_IMAGE6
594 
                parameter       hit0_conf = 1'b0 ;
595 
        `else
596 
                parameter       hit0_conf = 1'b1 ;      // if normal access is allowed to configuration space, then hit0 is hit0_conf
597 
        `endif
598 
`else
599 
                parameter       hit0_conf = 1'b1 ;      // if normal access is allowed to configuration space, then hit0 is hit0_conf
600 
`endif
601 
 
602 
// Logic with address mux, determining if address is still in the same image space and if it is prefetced or not
603 
`ifdef          PCI_IMAGE6
604 
        always@(hit5_in or     hit4_in or     hit3_in or     hit2_in or     hit1_in or     hit0_in or
605 
                        address5_in or address4_in or address3_in or address2_in or address1_in or address0_in or
606 
                        pre_fetch_en5_in or
607 
                        pre_fetch_en4_in or
608 
                        pre_fetch_en3_in or
609 
                        pre_fetch_en2_in or
610 
                        pre_fetch_en1_in or
611 
                        pre_fetch_en0_in
612 
                        )
613 
        begin
614 
                addr_claim <= (hit5_in || hit4_in || hit3_in || hit2_in) || (hit1_in || hit0_in) ;
615 
                case ({hit5_in, hit4_in, hit3_in, hit2_in, hit1_in, hit0_in})
616 
                6'b010000 :
617 
                begin
618 
                        address <= address4_in ;
619 
                        pre_fetch_en <= pre_fetch_en4_in ;
620 
                end
621 
                6'b001000 :
622 
                begin
623 
                        address <= address3_in ;
624 
                        pre_fetch_en <= pre_fetch_en3_in ;
625 
                end
626 
                6'b000100 :
627 
                begin
628 
                        address <= address2_in ;
629 
                        pre_fetch_en <= pre_fetch_en2_in ;
630 
                end
631 
                6'b000010 :
632 
                begin
633 
                        address <= address1_in ;
634 
                        pre_fetch_en <= pre_fetch_en1_in ;
635 
                end
636 
                6'b000001 :
637 
                begin
638 
                        address <= address0_in ;
639 
                        pre_fetch_en <= pre_fetch_en0_in ;
640 
                end
641 
                default :
642 
                begin
643 
                        address <= address5_in ;
644 
                        pre_fetch_en <= pre_fetch_en5_in ;
645 
                end
646 
                endcase
647 
        end
648 
`else
649 
        `ifdef          PCI_IMAGE5
650 
                always@(hit5_in or     hit4_in or     hit3_in or     hit2_in or     hit1_in or     hit0_in or
651 
                                address5_in or address4_in or address3_in or address2_in or address1_in or address0_in or
652 
                                pre_fetch_en5_in or
653 
                                pre_fetch_en4_in or
654 
                                pre_fetch_en3_in or
655 
                                pre_fetch_en2_in or
656 
                                pre_fetch_en1_in or
657 
                                pre_fetch_en0_in
658 
                                )
659 
                begin
660 
                        addr_claim <= (hit5_in || hit4_in || hit3_in || hit2_in) || (hit1_in || hit0_in) ;
661 
                        case ({hit5_in, hit4_in, hit3_in, hit2_in, hit1_in, hit0_in})
662 
                        6'b010000 :
663 
                        begin
664 
                                address <= address4_in ;
665 
                                pre_fetch_en <= pre_fetch_en4_in ;
666 
                        end
667 
                        6'b001000 :
668 
                        begin
669 
                                address <= address3_in ;
670 
                                pre_fetch_en <= pre_fetch_en3_in ;
671 
                        end
672 
                        6'b000100 :
673 
                        begin
674 
                                address <= address2_in ;
675 
                                pre_fetch_en <= pre_fetch_en2_in ;
676 
                        end
677 
                        6'b000010 :
678 
                        begin
679 
                                address <= address1_in ;
680 
                                pre_fetch_en <= pre_fetch_en1_in ;
681 
                        end
682 
                        6'b000001 :
683 
                        begin
684 
                                address <= address0_in ;
685 
                                pre_fetch_en <= pre_fetch_en0_in ;
686 
                        end
687 
                        default :
688 
                        begin
689 
                                address <= address5_in ;
690 
                                pre_fetch_en <= pre_fetch_en5_in ;
691 
                        end
692 
                        endcase
693 
                end
694 
        `else
695 
                `ifdef          PCI_IMAGE4
696 
                        always@(hit4_in or     hit3_in or     hit2_in or     hit1_in or     hit0_in or
697 
                                        address4_in or address3_in or address2_in or address1_in or address0_in or
698 
                                        pre_fetch_en4_in or
699 
                                        pre_fetch_en3_in or
700 
                                        pre_fetch_en2_in or
701 
                                        pre_fetch_en1_in or
702 
                                        pre_fetch_en0_in
703 
                                        )
704 
                        begin
705 
                                addr_claim <= hit4_in || (hit3_in || hit2_in || hit1_in || hit0_in) ;
706 
                                case ({hit4_in, hit3_in, hit2_in, hit1_in, hit0_in})
707 
                                5'b01000 :
708 
                                begin
709 
                                        address <= address3_in ;
710 
                                        pre_fetch_en <= pre_fetch_en3_in ;
711 
                                end
712 
                                5'b00100 :
713 
                                begin
714 
                                        address <= address2_in ;
715 
                                        pre_fetch_en <= pre_fetch_en2_in ;
716 
                                end
717 
                                5'b00010 :
718 
                                begin
719 
                                        address <= address1_in ;
720 
                                        pre_fetch_en <= pre_fetch_en1_in ;
721 
                                end
722 
                                5'b00001 :
723 
                                begin
724 
                                        address <= address0_in ;
725 
                                        pre_fetch_en <= pre_fetch_en0_in ;
726 
                                end
727 
                                default :
728 
                                begin
729 
                                        address <= address4_in ;
730 
                                        pre_fetch_en <= pre_fetch_en4_in ;
731 
                                end
732 
                                endcase
733 
                        end
734 
                `else
735 
                        `ifdef          PCI_IMAGE3
736 
                                always@(hit3_in or     hit2_in or     hit1_in or     hit0_in or
737 
                                                address3_in or address2_in or address1_in or address0_in or
738 
                                                pre_fetch_en3_in or
739 
                                                pre_fetch_en2_in or
740 
                                                pre_fetch_en1_in or
741 
                                                pre_fetch_en0_in
742 
                                                )
743 
                                begin
744 
                                        addr_claim <= (hit3_in || hit2_in || hit1_in || hit0_in) ;
745 
                                        case ({hit3_in, hit2_in, hit1_in, hit0_in})
746 
                                        4'b0100 :
747 
                                        begin
748 
                                                address <= address2_in ;
749 
                                                pre_fetch_en <= pre_fetch_en2_in ;
750 
                                        end
751 
                                        4'b0010 :
752 
                                        begin
753 
                                                address <= address1_in ;
754 
                                                pre_fetch_en <= pre_fetch_en1_in ;
755 
                                        end
756 
                                        4'b0001 :
757 
                                        begin
758 
                                                address <= address0_in ;
759 
                                                pre_fetch_en <= pre_fetch_en0_in ;
760 
                                        end
761 
                                        default :
762 
                                        begin
763 
                                                address <= address3_in ;
764 
                                                pre_fetch_en <= pre_fetch_en3_in ;
765 
                                        end
766 
                                        endcase
767 
                                end
768 
                        `else
769 
                                `ifdef          PCI_IMAGE2
770 
                                        always@(hit2_in or     hit1_in or     hit0_in or
771 
                                                        address2_in or address1_in or address0_in or
772 
                                                        pre_fetch_en2_in or
773 
                                                        pre_fetch_en1_in or
774 
                                                        pre_fetch_en0_in
775 
                                                        )
776 
                                        begin
777 
                                                addr_claim <= (hit2_in || hit1_in || hit0_in) ;
778 
                                                case ({hit2_in, hit1_in, hit0_in})
779 
                                                3'b010 :
780 
                                                begin
781 
                                                        address <= address1_in ;
782 
                                                        pre_fetch_en <= pre_fetch_en1_in ;
783 
                                                end
784 
                                                3'b001 :
785 
                                                begin
786 
                                                        address <= address0_in ;
787 
                                                        pre_fetch_en <= pre_fetch_en0_in ;
788 
                                                end
789 
                                                default :
790 
                                                begin
791 
                                                        address <= address2_in ;
792 
                                                        pre_fetch_en <= pre_fetch_en2_in ;
793 
                                                end
794 
                                                endcase
795 
                                        end
796 
                                `else
797 
                                        always@(hit1_in or     hit0_in or
798 
                                                        address1_in or address0_in or
799 
                                                        pre_fetch_en1_in or
800 
                                                        pre_fetch_en0_in
801 
                                                        )
802 
                                        begin
803 
                                                addr_claim <= (hit1_in || hit0_in) ;
804 
                                                case ({hit1_in, hit0_in})
805 
                                                2'b01 :
806 
                                                begin
807 
                                                        address <= address0_in ;
808 
                                                        pre_fetch_en <= pre_fetch_en0_in ;
809 
                                                end
810 
                                                default :
811 
                                                begin
812 
                                                        address <= address1_in ;
813 
                                                        pre_fetch_en <= pre_fetch_en1_in ;
814 
                                                end
815 
                                                endcase
816 
                                        end
817 
                                `endif
818 
                        `endif
819 
                `endif
820 
        `endif
821 
`endif
822 
 
823 
// Address claim output to PCI Target SM
824 
assign  addr_claim_out = addr_claim ;
825 
 
826 
reg             [11:0]   strd_address ;          // stored INPUT address for accessing Configuration space registers
827 
reg             [31:0]   norm_address ;          // stored normal address (decoded and translated) for access to WB
828 
reg                             norm_prf_en ;           // stored pre-fetch enable
829 
reg             [3:0]    norm_bc ;                       // stored bus-command
830 
reg                             same_read_reg ;         // stored SAME_READ information
831 
reg                             bckp_trdy_reg ;         // delayed registered TRDY output equivalent signal
832 
reg                             trdy_asserted_reg ;     // delayed bckp_trdy_reg signal
833 
 
834 
always@(posedge clk_in or posedge reset_in)
835 
begin
836 
    if (reset_in)
837 
        begin
838 
                strd_address <= 12'h000 ;
839 
                norm_address <= 32'h0000_0000 ;
840 
                norm_prf_en <= 1'b0 ;
841 
                norm_bc <= 4'h0 ;
842 
                same_read_reg <= 1'b0 ;
843 
        end
844 
        else
845 
        begin
846 
                if (addr_phase_in)
847 
                begin
848 
                        strd_address <= address_in[11:0] ;
849 
                        norm_address <= address ;
850 
                        norm_prf_en <= pre_fetch_en ;
851 
                        norm_bc <= bc_in ;
852 
                        same_read_reg <= same_read_out ;
853 
                end
854 
        end
855 
end
856 
always@(posedge clk_in or posedge reset_in)
857 
begin
858 
    if (reset_in)
859 
        begin
860 
                bckp_trdy_reg <= 1'b0 ;
861 
                trdy_asserted_reg <= 1'b0 ;
862 
        end
863 
        else
864 
        begin
865 
                bckp_trdy_reg <= bckp_trdy_in ;
866 
                trdy_asserted_reg <= bckp_trdy_reg ;
867 
        end
868 
end
869 
// Signal indicates when target ready is deaserted on PCI bus
870 
wire    trdy_asserted = trdy_asserted_reg && bckp_trdy_reg ;
871 
 
872 
reg                             same_read_request ;
873 
 
874 
// When delayed read is completed on WB, addres and bc must be compered, if there is the same read request
875 
always@(address or strd_addr_in or bc_in or strd_bc_in)
876 
begin
877 
        if ((address == strd_addr_in) & (bc_in == strd_bc_in))
878 
                same_read_request <= 1'b1 ;
879 
        else
880 
                same_read_request <= 1'b0 ;
881 
end
882 
 
883 
assign  same_read_out = (same_read_request) ; // && ~pcir_fifo_empty_in) ;
884 
 
885 
// Signals for byte enable checking
886 
reg                             addr_burst_ok ;
887 
reg                             io_be_ok ;
888 
reg                             conf_be_ok ;
889 
 
890 
// Byte enable checking for IO, MEMORY and CONFIGURATION spaces - be_in is active low!
891 
always@(strd_address or be_in)
892 
begin
893 
        case (strd_address[1:0])
894 
        2'b11 :
895 
        begin
896 
                addr_burst_ok <= 1'b0 ;
897 
                io_be_ok <= (be_in[2] && be_in[1] && be_in[0]) ; // only be3 can be active
898 
                conf_be_ok <= 1'b0 ;
899 
        end
900 
        2'b10 :
901 
        begin
902 
                addr_burst_ok <= 1'b0 ;
903 
                io_be_ok <= (~be_in[2] && be_in[1] && be_in[0]) || (be_in[3] && be_in[2] && be_in[1] && be_in[0]) ;
904 
                conf_be_ok <= 1'b0 ;
905 
        end
906 
        2'b01 :
907 
        begin
908 
                addr_burst_ok <= 1'b0 ;
909 
                io_be_ok <= (~be_in[1] && be_in[0]) || (be_in[3] && be_in[2] && be_in[1] && be_in[0]) ;
910 
                conf_be_ok <= 1'b0 ;
911 
        end
912 
        default :       // 2'b00
913 
        begin
914 
                addr_burst_ok <= 1'b1 ;
915 
                io_be_ok <= (~be_in[0]) || (be_in[3] && be_in[2] && be_in[1] && be_in[0]) ;
916 
                conf_be_ok <= 1'b1 ;
917 
        end
918 
        endcase
919 
end
920 
 
921 
reg                             calc_target_abort ;
922 
// Target abort indication regarding the registered bus command and current signals for byte enable checking
923 
always@(bc_in or hit0_in or io_be_ok or conf_be_ok)
924 
begin
925 
        case (bc_in)
926 
        // READ COMMANDS
927 
        `BC_IO_READ :
928 
        begin
929 
                case ({hit0_in, hit0_conf})
930 
                2'b11 :
931 
                begin
932 
                        calc_target_abort <= 1'b1 ;
933 
                end
934 
                default :
935 
                begin
936 
                        if (io_be_ok)
937 
                        begin
938 
                                calc_target_abort <= 1'b0 ;
939 
                        end
940 
                        else
941 
                        begin
942 
                                calc_target_abort <= 1'b1 ;
943 
                        end
944 
                end
945 
                endcase
946 
        end
947 
        `BC_MEM_READ :
948 
        begin
949 
                case ({hit0_in, hit0_conf})
950 
                2'b11 :
951 
                begin
952 
                        calc_target_abort <= 1'b0 ;
953 
                end
954 
                default :
955 
                begin
956 
                        calc_target_abort <= 1'b0 ;
957 
                end
958 
                endcase
959 
        end
960 
        `BC_CONF_READ :
961 
        begin
962 
                case (conf_be_ok)
963 
                1'b1 :
964 
                begin
965 
                        calc_target_abort <= 1'b0 ;
966 
                end
967 
                default :
968 
                begin
969 
                        calc_target_abort <= 1'b1 ;
970 
                end
971 
                endcase
972 
        end
973 
        `BC_MEM_READ_LN,
974 
        `BC_MEM_READ_MUL :
975 
        begin
976 
                case ({hit0_in, hit0_conf})
977 
                2'b11 :
978 
                begin
979 
                        calc_target_abort <= 1'b1 ;
980 
                end
981 
                default :
982 
                begin
983 
                        calc_target_abort <= 1'b0 ;
984 
                end
985 
                endcase
986 
        end
987 
        // WRITE COMMANDS
988 
        `BC_IO_WRITE :
989 
        begin
990 
                case ({hit0_in, hit0_conf})
991 
                2'b11 :
992 
                begin
993 
                        calc_target_abort <= 1'b1 ;
994 
                end
995 
                default :
996 
                begin
997 
                        if (io_be_ok)
998 
                        begin
999 
                                calc_target_abort <= 1'b0 ;
1000 
                        end
1001 
                        else
1002 
                        begin
1003 
                                calc_target_abort <= 1'b1 ;
1004 
                        end
1005 
                end
1006 
                endcase
1007 
        end
1008 
        `BC_MEM_WRITE :
1009 
        begin
1010 
                case ({hit0_in, hit0_conf})
1011 
                2'b11 :
1012 
                begin
1013 
                        calc_target_abort <= 1'b0 ;
1014 
                end
1015 
                default :
1016 
                begin
1017 
                        calc_target_abort <= 1'b0 ;
1018 
                end
1019 
                endcase
1020 
        end
1021 
        `BC_CONF_WRITE :
1022 
        begin
1023 
                case (conf_be_ok)
1024 
                1'b1 :
1025 
                begin
1026 
                        calc_target_abort <= 1'b0 ;
1027 
                end
1028 
                default :
1029 
                begin
1030 
                        calc_target_abort <= 1'b1 ;
1031 
                end
1032 
                endcase
1033 
        end
1034 
        `BC_MEM_WRITE_INVAL :
1035 
        begin
1036 
                case ({hit0_in, hit0_conf})
1037 
                2'b11 :
1038 
                begin
1039 
                        calc_target_abort <= 1'b1 ;
1040 
                end
1041 
                default :
1042 
                begin
1043 
                        calc_target_abort <= 1'b0 ;
1044 
                end
1045 
                endcase
1046 
        end
1047 
        default :
1048 
        begin
1049 
                calc_target_abort <= 1'b0 ;
1050 
        end
1051 
        endcase
1052 
end
1053 
 
1054 
// Medium registers for data and control busses from PCIR_FIFO
1055 
reg             [31:0]   pcir_fifo_data_reg ;
1056 
reg             [3:0]    pcir_fifo_ctrl_reg ;
1057 
 
1058 
always@(posedge clk_in or posedge reset_in)
1059 
begin
1060 
    if (reset_in)
1061 
    begin
1062 
        pcir_fifo_data_reg <= 32'h0000_0000 ;
1063 
        pcir_fifo_ctrl_reg <=  4'h0 ;
1064 
    end
1065 
    else
1066 
    begin
1067 
        if (load_medium_reg_in)
1068 
        begin
1069 
                pcir_fifo_data_reg <= pcir_fifo_data_in ;
1070 
                pcir_fifo_ctrl_reg <= pcir_fifo_control_in ;
1071 
        end
1072 
    end
1073 
end
1074 
 
1075 
// selecting "fifo data" from medium registers or from PCIR_FIFO
1076 
wire [31:0]      pcir_fifo_data = sel_fifo_mreg_in ? pcir_fifo_data_in : pcir_fifo_data_reg ;
1077 
wire [3:0]       pcir_fifo_ctrl = sel_fifo_mreg_in ? pcir_fifo_control_in : pcir_fifo_ctrl_reg ;
1078 
 
1079 
// signal assignments to PCI Target FSM
1080 
assign  norm_access_to_config_out = (hit0_in && hit0_conf) ;
1081 
assign  read_completed_out = req_comp_pending_in ; // completion pending input for requesting side of the bridge
1082 
assign  read_processing_out = req_req_pending_in ; // request pending input for requesting side
1083 
assign  disconect_wo_data_out = (
1084 
        ((pcir_fifo_ctrl[`LAST_CTRL_BIT] || pcir_fifo_empty_in || ~addr_burst_ok) && ~bc0_in && ~frame_reg_in) ||
1085 
        ((pciw_fifo_full_in || pciw_fifo_almost_full_in || pciw_fifo_two_left_in || ~addr_burst_ok) && bc0_in && ~frame_reg_in)
1086 
                                                                ) ;
1087 
assign  target_abort_out = (addr_phase_in && calc_target_abort) ;
1088 
 
1089 
// control signal assignments to read request sinchronization module
1090 
assign  done_out = (~sel_conf_fifo_in && same_read_reg && ~trdy_asserted && last_reg_in) ;
1091 
assign  in_progress_out = (~sel_conf_fifo_in && same_read_reg && ~bckp_trdy_in) ;
1092 
 
1093 
// signal used for PCIR_FIFO flush (with comp_flush_in signal)
1094 
wire    pcir_fifo_flush = (~sel_conf_fifo_in && same_read_reg && ~trdy_asserted && last_reg_in && ~pcir_fifo_empty_in) ;
1095 
// flush signal for PCIR_FIFO must be registered, since it asinchronously resets some status registers
1096 
reg             pcir_fifo_flush_reg ;
1097 
always@(posedge clk_in or posedge reset_in)
1098 
begin
1099 
    if (reset_in)
1100 
    begin
1101 
        pcir_fifo_flush_reg <=  1'b0 ;
1102 
    end
1103 
    else
1104 
    begin
1105 
        pcir_fifo_flush_reg <= comp_flush_in || pcir_fifo_flush ;
1106 
    end
1107 
end
1108 
 
1109 
// signal assignments from fifo to PCI Target FSM
1110 
assign  wbw_fifo_empty_out = wbw_fifo_empty_in ;
1111 
assign  pciw_fifo_full_out = (pciw_fifo_full_in || pciw_fifo_almost_full_in || pciw_fifo_two_left_in) ;
1112 
assign  pcir_fifo_data_err_out = pcir_fifo_ctrl[`DATA_ERROR_CTRL_BIT] ;
1113 
// signal assignments to fifo
1114 
assign  pcir_fifo_flush_out                                                     = pcir_fifo_flush_reg ;
1115 
assign  pcir_fifo_renable_out                                           = fetch_pcir_fifo_in ;
1116 
assign  pciw_fifo_wenable_out                                           = load_to_pciw_fifo_in ;
1117 
assign  pciw_fifo_control_out[`ADDR_CTRL_BIT]           = 1'b0 ;
1118 
assign  pciw_fifo_control_out[`BURST_BIT]                       = rdy_in ? 1'b0 : ~frame_reg_in ;
1119 
assign  pciw_fifo_control_out[`DATA_ERROR_CTRL_BIT]     = 1'b0 ;
1120 
assign  pciw_fifo_control_out[`LAST_CTRL_BIT]           = rdy_in ? (last_reg_in || pciw_fifo_almost_full_in) : 1'b0 ;
1121 
 
1122 
// data and address outputs assignments to PCI Target FSM
1123 
assign  data_out = sel_conf_fifo_in ? conf_data_in : pcir_fifo_data ;
1124 
// data and address outputs assignments to read request sinchronization module
1125 
assign  req_out = req_in ;
1126 
assign  addr_out = norm_address ;
1127 
assign  be_out = be_in ;
1128 
assign  we_out = 1'b0 ;
1129 
assign  bc_out = norm_bc ;
1130 
assign  burst_out = ~frame_reg_in && norm_prf_en ;
1131 
// data and address outputs assignments to PCIW_FIFO
1132 
assign  pciw_fifo_addr_data_out = rdy_in ? data_in : norm_address ;
1133 
assign  pciw_fifo_cbe_out = rdy_in ? be_in : norm_bc ;
1134 
// data and address outputs assignments to Configuration space
1135 
assign  conf_data_out = data_in ;
1136 
assign  conf_addr_out = strd_address[11:0] ;
1137 
assign  conf_be_out = be_in ;
1138 
assign  conf_we_out = load_to_conf_in ;
1139 
assign  conf_re_out = fetch_conf_in ;
1140 
 
1141 
 
1142 
endmodule

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