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mihad |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// File name "pciw_pcir_fifos.v" ////
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//// ////
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//// This file is part of the "PCI bridge" project ////
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//// http://www.opencores.org/cores/pci/ ////
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//// ////
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//// Author(s): ////
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//// - Miha Dolenc (mihad@opencores.org) ////
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//// ////
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//// All additional information is avaliable in the README ////
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//// file. ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 Miha Dolenc, mihad@opencores.org ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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mihad |
// Revision 1.1.1.1 2001/10/02 15:33:47 mihad
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// New project directory structure
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mihad |
//
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mihad |
//
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mihad |
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`include "constants.v"
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mihad |
`include "timescale.v"
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mihad |
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module PCIW_PCIR_FIFOS
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(
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wb_clock_in,
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pci_clock_in,
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reset_in,
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pciw_wenable_in,
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pciw_addr_data_in,
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pciw_cbe_in,
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pciw_control_in,
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pciw_renable_in,
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pciw_addr_data_out,
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pciw_cbe_out,
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pciw_control_out,
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pciw_flush_in,
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pciw_two_left_out,
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pciw_almost_full_out,
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pciw_full_out,
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pciw_almost_empty_out,
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pciw_empty_out,
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pciw_transaction_ready_out,
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pcir_wenable_in,
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pcir_data_in,
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pcir_be_in,
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pcir_control_in,
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pcir_renable_in,
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pcir_data_out,
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pcir_be_out,
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pcir_control_out,
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pcir_flush_in,
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pcir_almost_full_out,
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pcir_full_out,
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pcir_almost_empty_out,
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pcir_empty_out,
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pcir_transaction_ready_out
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) ;
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/*-----------------------------------------------------------------------------------------------------------
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System inputs:
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wb_clock_in - WISHBONE bus clock
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pci_clock_in - PCI bus clock
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reset_in - reset from control logic
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-------------------------------------------------------------------------------------------------------------*/
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input wb_clock_in, pci_clock_in, reset_in ;
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/*-----------------------------------------------------------------------------------------------------------
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PCI WRITE FIFO interface signals prefixed with pciw_ - FIFO is used for posted writes initiated by external
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PCI master through PCI target interface, traveling through FIFO and are completed on WISHBONE by
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WISHBONE master interface
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write enable signal:
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pciw_wenable_in = write enable input for PCIW_FIFO - driven by PCI TARGET interface
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data input signals:
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pciw_addr_data_in = data input - data from PCI bus - first entry of transaction is address others are data entries
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pciw_cbe_in = bus command/byte enable(~#BE[3:0]) input - first entry of transaction is bus command, other are byte enables
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pciw_control_in = control input - encoded control bus input
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read enable signal:
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pciw_renable_in = read enable input driven by WISHBONE master interface
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data output signals:
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pciw_addr_data_out = data output - data from PCI bus - first entry of transaction is address, others are data entries
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pciw_cbe_out = bus command/byte enable output - first entry of transaction is bus command, others are byte enables
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pciw_control_out = control input - encoded control bus input
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status signals - monitored by various resources in the core
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pciw_flush_in = flush signal input for PCIW_FIFO - when asserted, fifo is flushed(emptied)
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pciw_almost_full_out = almost full output from PCIW_FIFO
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pciw_full_out = full output from PCIW_FIFO
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pciw_almost_empty_out = almost empty output from PCIW_FIFO
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pciw_empty_out = empty output from PCIW_FIFO
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pciw_transaction_ready_out = output indicating that one complete transaction is waiting in PCIW_FIFO
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-----------------------------------------------------------------------------------------------------------*/
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// input control and data
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input pciw_wenable_in ;
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input [31:0] pciw_addr_data_in ;
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input [3:0] pciw_cbe_in ;
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input [3:0] pciw_control_in ;
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// output control and data
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input pciw_renable_in ;
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output [31:0] pciw_addr_data_out ;
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output [3:0] pciw_cbe_out ;
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output [3:0] pciw_control_out ;
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// flush input
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input pciw_flush_in ;
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// status outputs
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output pciw_two_left_out ;
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output pciw_almost_full_out ;
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output pciw_full_out ;
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output pciw_almost_empty_out ;
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output pciw_empty_out ;
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output pciw_transaction_ready_out ;
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/*-----------------------------------------------------------------------------------------------------------
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PCI READ FIFO interface signals prefixed with pcir_ - FIFO is used for holding delayed read completions
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initiated by master on PCI bus and completed on WISHBONE bus,
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write enable signal:
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pcir_wenable_in = write enable input for PCIR_FIFO - driven by WISHBONE master interface
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data input signals:
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pcir_data_in = data input - data from WISHBONE bus - there is no address entry here, since address is stored in separate register
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pcir_be_in = byte enable(~SEL[3:0]) input - byte enables - same through one transaction
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pcir_control_in = control input - encoded control bus input
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read enable signal:
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pcir_renable_in = read enable input driven by PCI target interface
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data output signals:
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pcir_data_out = data output - data from WISHBONE bus
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pcir_be_out = byte enable output(~SEL)
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pcir_control_out = control output - encoded control bus output
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status signals - monitored by various resources in the core
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pcir_flush_in = flush signal input for PCIR_FIFO - when asserted, fifo is flushed(emptied)
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pcir_almost_full_out = almost full output from PCIR_FIFO
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pcir full_out = full output from PCIR_FIFO
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pcir_almost_empty_out = almost empty output from PCIR_FIFO
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pcir_empty_out = empty output from PCIR_FIFO
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pcir_transaction_ready_out = output indicating that one complete transaction is waiting in PCIR_FIFO
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-----------------------------------------------------------------------------------------------------------*/
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// input control and data
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input pcir_wenable_in ;
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input [31:0] pcir_data_in ;
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input [3:0] pcir_be_in ;
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input [3:0] pcir_control_in ;
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// output control and data
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input pcir_renable_in ;
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output [31:0] pcir_data_out ;
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output [3:0] pcir_be_out ;
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output [3:0] pcir_control_out ;
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// flush input
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input pcir_flush_in ;
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// status outputs
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output pcir_almost_full_out ;
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output pcir_full_out ;
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output pcir_almost_empty_out ;
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output pcir_empty_out ;
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output pcir_transaction_ready_out ;
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/*-----------------------------------------------------------------------------------------------------------
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Address length parameters:
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PCIW_DEPTH = defines PCIW_FIFO depth
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PCIR_DEPTH = defines PCIR_FIFO depth
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PCIW_ADDR_LENGTH = defines PCIW_FIFO's location address length - log2(PCIW_DEPTH)
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PCIR_ADDR_LENGTH = defines PCIR_FIFO's location address length - log2(PCIR_DEPTH)
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-----------------------------------------------------------------------------------------------------------*/
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parameter PCIW_DEPTH = `PCIW_DEPTH ;
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parameter PCIW_ADDR_LENGTH = `PCIW_ADDR_LENGTH ;
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parameter PCIR_DEPTH = `PCIR_DEPTH ;
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parameter PCIR_ADDR_LENGTH = `PCIR_ADDR_LENGTH ;
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// obvious
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wire vcc = 1'b1 ;
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wire gnd = 1'b0 ;
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/*-----------------------------------------------------------------------------------------------------------
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pciw_wallow = PCIW_FIFO write allow wire - writes to FIFO are allowed when FIFO isn't full and write enable is 1
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pciw_rallow = PCIW_FIFO read allow wire - reads from FIFO are allowed when FIFO isn't empty and read enable is 1
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-----------------------------------------------------------------------------------------------------------*/
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wire pciw_wallow ;
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wire pciw_rallow ;
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/*-----------------------------------------------------------------------------------------------------------
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pcir_wallow = PCIR_FIFO write allow wire - writes to FIFO are allowed when FIFO isn't full and write enable is 1
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pcir_rallow = PCIR_FIFO read allow wire - reads from FIFO are allowed when FIFO isn't empty and read enable is 1
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-----------------------------------------------------------------------------------------------------------*/
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wire pcir_wallow ;
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wire pcir_rallow ;
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/*-----------------------------------------------------------------------------------------------------------
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wires for address port conections from PCIW_FIFO control logic to RAM blocks used for PCIW_FIFO
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-----------------------------------------------------------------------------------------------------------*/
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wire [(PCIW_ADDR_LENGTH - 1):0] pciw_raddr ;
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wire [(PCIW_ADDR_LENGTH - 1):0] pciw_waddr ;
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/*-----------------------------------------------------------------------------------------------------------
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wires for address port conections from PCIR_FIFO control logic to RAM blocks used for PCIR_FIFO
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-----------------------------------------------------------------------------------------------------------*/
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wire [(PCIR_ADDR_LENGTH - 1):0] pcir_raddr ;
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wire [(PCIR_ADDR_LENGTH - 1):0] pcir_waddr ;
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/*-----------------------------------------------------------------------------------------------------------
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PCIW_FIFO transaction counters: used to count incoming transactions and outgoing transactions. When number of
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input transactions is equal to number of output transactions, it means that there isn't any complete transaction
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currently present in the FIFO.
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-----------------------------------------------------------------------------------------------------------*/
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reg [(PCIW_ADDR_LENGTH - 1):0] pciw_inTransactionCount ;
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reg [(PCIW_ADDR_LENGTH - 1):0] pciw_outTransactionCount ;
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/*-----------------------------------------------------------------------------------------------------------
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FlipFlops for indicating if complete delayed read completion is present in the FIFO
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-----------------------------------------------------------------------------------------------------------*/
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/*reg pcir_inTransactionCount ;
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reg pcir_outTransactionCount ;*/
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/*-----------------------------------------------------------------------------------------------------------
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wires monitoring control bus. When control bus on a write transaction has a value of `LAST, it means that
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complete transaction is in the FIFO. When control bus on a read transaction has a value of `LAST,
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it means that there was one complete transaction taken out of FIFO.
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-----------------------------------------------------------------------------------------------------------*/
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wire pciw_last_in = pciw_control_in[`LAST_CTRL_BIT] ;
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wire pciw_last_out = pciw_control_out[`LAST_CTRL_BIT] ;
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/*wire pcir_last_in = pcir_wallow && (pcir_control_in == `LAST) ;
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wire pcir_last_out = pcir_rallow && (pcir_control_out == `LAST) ;*/
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wire pciw_empty ;
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wire pcir_empty ;
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assign pciw_empty_out = pciw_empty ;
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assign pcir_empty_out = pcir_empty ;
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// clear wires for clearing FFs and registers
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wire pciw_clear = reset_in || pciw_flush_in ; // PCIW_FIFO's clear signal
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wire pcir_clear = reset_in || pcir_flush_in ; // PCIR_FIFO's clear signal
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`ifdef FPGA
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/*-----------------------------------------------------------------------------------------------------------
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this code is included only for FPGA core usage - somewhat different logic because of sharing
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278 |
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one block selectRAM+ between two FIFOs
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-----------------------------------------------------------------------------------------------------------*/
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`ifdef BIG
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/*-----------------------------------------------------------------------------------------------------------
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282 |
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Big FPGAs
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283 |
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PCIW_FIFO and PCIR_FIFO address prefixes - used for extending read and write addresses because of varible
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284 |
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FIFO depth and fixed SelectRAM+ size. Addresses are zero paded on the left to form long enough address
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285 |
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-----------------------------------------------------------------------------------------------------------*/
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wire [(7 - PCIW_ADDR_LENGTH):0] pciw_addr_prefix = {( 8 - PCIW_ADDR_LENGTH){1'b0}} ;
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wire [(7 - PCIR_ADDR_LENGTH):0] pcir_addr_prefix = {( 8 - PCIR_ADDR_LENGTH){1'b0}} ;
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288 |
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289 |
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// compose addresses
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wire [7:0] pciw_whole_waddr = {pciw_addr_prefix, pciw_waddr} ;
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wire [7:0] pciw_whole_raddr = {pciw_addr_prefix, pciw_raddr} ;
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292 |
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293 |
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wire [7:0] pcir_whole_waddr = {pcir_addr_prefix, pcir_waddr} ;
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294 |
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wire [7:0] pcir_whole_raddr = {pcir_addr_prefix, pcir_raddr} ;
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295 |
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296 |
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/*-----------------------------------------------------------------------------------------------------------
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297 |
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Only 8 bits out of 16 are used in ram3 and ram6 - wires for referencing them
|
298 |
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-----------------------------------------------------------------------------------------------------------*/
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299 |
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wire [15:0] dpram3_portB_output ;
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300 |
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wire [15:0] dpram6_portA_output ;
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301 |
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302 |
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/*-----------------------------------------------------------------------------------------------------------
|
303 |
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Control out assignements from ram3 output
|
304 |
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-----------------------------------------------------------------------------------------------------------*/
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assign pciw_control_out = dpram3_portB_output[15:12] ;
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assign pcir_control_out = dpram6_portA_output[15:12] ;
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307 |
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308 |
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assign pciw_cbe_out = dpram3_portB_output[3:0] ;
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assign pcir_be_out = dpram6_portA_output[3:0] ;
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310 |
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wire pciw_read_enable = pciw_rallow || pciw_empty ;
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wire pcir_read_enable = pcir_rallow || pcir_empty ;
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313 |
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314 |
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// Block SelectRAM+ cells instantiation
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315 |
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RAMB4_S16_S16 dpram16_1 (.ADDRA(pciw_whole_waddr), .DIA(pciw_addr_data_in[15:0]),
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.ENA(vcc), .RSTA(reset_in),
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317 |
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.CLKA(pci_clock_in), .WEA(pciw_wallow),
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318 |
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.DOA(),
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319 |
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.ADDRB(pciw_whole_raddr), .DIB(16'h0000),
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.ENB(pciw_read_enable), .RSTB(reset_in),
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321 |
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.CLKB(wb_clock_in), .WEB(gnd),
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322 |
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.DOB(pciw_addr_data_out[15:0])) ;
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323 |
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|
|
324 |
|
|
RAMB4_S16_S16 dpram16_2 (.ADDRA(pciw_whole_waddr), .DIA(pciw_addr_data_in[31:16]),
|
325 |
|
|
.ENA(vcc), .RSTA(reset_in),
|
326 |
|
|
.CLKA(pci_clock_in), .WEA(pciw_wallow),
|
327 |
|
|
.DOA(),
|
328 |
|
|
.ADDRB(pciw_whole_raddr), .DIB(16'h0000),
|
329 |
|
|
.ENB(pciw_read_enable), .RSTB(reset_in),
|
330 |
|
|
.CLKB(wb_clock_in), .WEB(gnd),
|
331 |
|
|
.DOB(pciw_addr_data_out[31:16])) ;
|
332 |
|
|
|
333 |
|
|
RAMB4_S16_S16 dpram16_3 (.ADDRA(pciw_whole_waddr), .DIA({pciw_control_in, 8'h00, pciw_cbe_in}),
|
334 |
|
|
.ENA(vcc), .RSTA(reset_in),
|
335 |
|
|
.CLKA(pci_clock_in), .WEA(pciw_wallow),
|
336 |
|
|
.DOA(),
|
337 |
|
|
.ADDRB(pciw_whole_raddr), .DIB(16'h0000),
|
338 |
|
|
.ENB(pciw_read_enable), .RSTB(reset_in),
|
339 |
|
|
.CLKB(wb_clock_in), .WEB(gnd),
|
340 |
|
|
.DOB(dpram3_portB_output)) ;
|
341 |
|
|
|
342 |
|
|
RAMB4_S16_S16 dpram16_4 (.ADDRA(pcir_whole_raddr), .DIA(16'h0000),
|
343 |
|
|
.ENA(pcir_read_enable), .RSTA(reset_in),
|
344 |
|
|
.CLKA(pci_clock_in), .WEA(gnd),
|
345 |
|
|
.DOA(pcir_data_out[15:0]),
|
346 |
|
|
.ADDRB(pcir_whole_waddr), .DIB(pcir_data_in[15:0]),
|
347 |
|
|
.ENB(vcc), .RSTB(reset_in),
|
348 |
|
|
.CLKB(wb_clock_in), .WEB(pcir_wallow),
|
349 |
|
|
.DOB()) ;
|
350 |
|
|
|
351 |
|
|
RAMB4_S16_S16 dpram16_5 (.ADDRA(pcir_whole_raddr), .DIA(16'h0000),
|
352 |
|
|
.ENA(pcir_read_enable), .RSTA(reset_in),
|
353 |
|
|
.CLKA(pci_clock_in), .WEA(gnd),
|
354 |
|
|
.DOA(pcir_data_out[31:16]),
|
355 |
|
|
.ADDRB(pcir_whole_waddr), .DIB(pcir_data_in[31:16]),
|
356 |
|
|
.ENB(vcc), .RSTB(reset_in),
|
357 |
|
|
.CLKB(wb_clock_in), .WEB(pcir_wallow),
|
358 |
|
|
.DOB()) ;
|
359 |
|
|
|
360 |
|
|
RAMB4_S16_S16 dpram16_6 (.ADDRA(pcir_whole_raddr), .DIA(16'h0000),
|
361 |
|
|
.ENA(pcir_read_enable), .RSTA(reset_in),
|
362 |
|
|
.CLKA(pci_clock_in), .WEA(gnd),
|
363 |
|
|
.DOA(dpram6_portA_output),
|
364 |
|
|
.ADDRB(pcir_whole_waddr), .DIB({pcir_control_in, 8'h00, pcir_be_in}),
|
365 |
|
|
.ENB(vcc), .RSTB(reset_in),
|
366 |
|
|
.CLKB(wb_clock_in), .WEB(pcir_wallow),
|
367 |
|
|
.DOB()) ;
|
368 |
|
|
|
369 |
|
|
`else // SMALL FPGAs
|
370 |
|
|
|
371 |
|
|
/*-----------------------------------------------------------------------------------------------------------
|
372 |
|
|
Small FPGAs
|
373 |
|
|
PCIW_FIFO and PCIR_FIFO address prefixes - used for extending read and write addresses because of varible
|
374 |
|
|
FIFO depth and fixed SelectRAM+ size. Addresses are always paded, because of RAM sharing between FIFOs
|
375 |
|
|
PCIW addresses are zero padded on the left, PCIR addresses are padded
|
376 |
|
|
with ones on the left
|
377 |
|
|
-----------------------------------------------------------------------------------------------------------*/
|
378 |
|
|
wire [(7 - PCIW_ADDR_LENGTH):0] pciw_addr_prefix = {( 8 - PCIW_ADDR_LENGTH){1'b0}} ;
|
379 |
|
|
wire [(7 - PCIR_ADDR_LENGTH):0] pcir_addr_prefix = {( 8 - PCIR_ADDR_LENGTH){1'b1}} ;
|
380 |
|
|
|
381 |
|
|
/*-----------------------------------------------------------------------------------------------------------
|
382 |
|
|
Only 8 bits out of 16 are used in ram3 - wires for referencing them
|
383 |
|
|
-----------------------------------------------------------------------------------------------------------*/
|
384 |
|
|
wire [15:0] dpram3_portA_output ;
|
385 |
|
|
wire [15:0] dpram3_portB_output ;
|
386 |
|
|
|
387 |
|
|
/*-----------------------------------------------------------------------------------------------------------
|
388 |
|
|
Control out assignements from ram3 output
|
389 |
|
|
-----------------------------------------------------------------------------------------------------------*/
|
390 |
|
|
assign pciw_control_out = dpram3_portB_output[15:12] ;
|
391 |
|
|
assign pcir_control_out = dpram3_portA_output[15:12] ;
|
392 |
|
|
|
393 |
|
|
assign pciw_cbe_out = dpram3_portB_output[3:0] ;
|
394 |
|
|
assign pcir_be_out = dpram3_portA_output[3:0] ;
|
395 |
|
|
|
396 |
|
|
/*-----------------------------------------------------------------------------------------------------------
|
397 |
|
|
Logic used for extending port's enable input for one clock cycle to allow address and date change from
|
398 |
|
|
PCI write fifo's write address and data back to PCI read fifo's address and data ( turnaround cycle )
|
399 |
|
|
-----------------------------------------------------------------------------------------------------------*/
|
400 |
|
|
reg pciw_write_performed ;
|
401 |
|
|
always@(posedge pci_clock_in or posedge reset_in)
|
402 |
|
|
begin
|
403 |
|
|
if (reset_in)
|
404 |
|
|
pciw_write_performed <= #`FF_DELAY 1'b0 ;
|
405 |
|
|
else
|
406 |
|
|
pciw_write_performed <= #`FF_DELAY pciw_wallow ;
|
407 |
|
|
end
|
408 |
|
|
|
409 |
|
|
/*-----------------------------------------------------------------------------------------------------------
|
410 |
|
|
Logic used for extending port's enable input for one clock cycle to allow address and date change from
|
411 |
|
|
PCI read fifo's write address and data back to PCI write fifo's address and data ( turnaround cycle )
|
412 |
|
|
-----------------------------------------------------------------------------------------------------------*/
|
413 |
|
|
reg pcir_write_performed ;
|
414 |
|
|
always@(posedge wb_clock_in or posedge reset_in)
|
415 |
|
|
begin
|
416 |
|
|
if (reset_in)
|
417 |
|
|
pcir_write_performed <= #`FF_DELAY 1'b0 ;
|
418 |
|
|
else
|
419 |
|
|
pcir_write_performed <= #`FF_DELAY pcir_wallow ;
|
420 |
|
|
end
|
421 |
|
|
|
422 |
|
|
/*-----------------------------------------------------------------------------------------------------------
|
423 |
|
|
Additional register storing actual PCIW read address. It must be applied to port B during turnaround cycle
|
424 |
|
|
-----------------------------------------------------------------------------------------------------------*/
|
425 |
|
|
reg [(PCIW_ADDR_LENGTH - 1):0] pciw_raddr_0 ;
|
426 |
|
|
|
427 |
|
|
always@(posedge wb_clock_in or posedge pciw_clear)
|
428 |
|
|
begin
|
429 |
|
|
if (pciw_clear)
|
430 |
|
|
pciw_raddr_0 <= #`FF_DELAY {PCIW_ADDR_LENGTH{1'b0}} ;
|
431 |
|
|
else
|
432 |
|
|
if(pciw_rallow)
|
433 |
|
|
pciw_raddr_0 <= #`FF_DELAY pciw_raddr ;
|
434 |
|
|
end
|
435 |
|
|
|
436 |
|
|
wire [(PCIW_ADDR_LENGTH - 1):0] pciw_raddr_calc = pcir_write_performed ? pciw_raddr_0 : pciw_raddr ;
|
437 |
|
|
|
438 |
|
|
/*-----------------------------------------------------------------------------------------------------------
|
439 |
|
|
Additional register storing actual PCIR read address. It must be applied to port A during turnaround cycle
|
440 |
|
|
-----------------------------------------------------------------------------------------------------------*/
|
441 |
|
|
reg [(PCIR_ADDR_LENGTH - 1):0] pcir_raddr_0 ;
|
442 |
|
|
|
443 |
|
|
always@(posedge pci_clock_in or posedge pcir_clear)
|
444 |
|
|
begin
|
445 |
|
|
if(pcir_clear)
|
446 |
|
|
pcir_raddr_0 <= #`FF_DELAY {PCIR_ADDR_LENGTH{1'b0}} ;
|
447 |
|
|
else
|
448 |
|
|
if(pcir_rallow)
|
449 |
|
|
pcir_raddr_0 <= #`FF_DELAY pcir_raddr ;
|
450 |
|
|
end
|
451 |
|
|
|
452 |
|
|
wire [(PCIR_ADDR_LENGTH - 1):0] pcir_raddr_calc = pciw_write_performed ? pcir_raddr_0 : pcir_raddr ;
|
453 |
|
|
|
454 |
|
|
/*-----------------------------------------------------------------------------------------------------------
|
455 |
|
|
Port A and B enables
|
456 |
|
|
-----------------------------------------------------------------------------------------------------------*/
|
457 |
|
|
wire portA_enable = pciw_wallow || pcir_rallow || pcir_empty || pciw_write_performed ;
|
458 |
|
|
wire portB_enable = pcir_wallow || pciw_rallow || pciw_empty || pcir_write_performed ;
|
459 |
|
|
|
460 |
|
|
/*-----------------------------------------------------------------------------------------------------------
|
461 |
|
|
Port A address generation for block SelectRam+ in SpartanII or Virtex
|
462 |
|
|
Port A is clocked by PCI clock, DIA is input for pciw_fifo, DOA is output for pcir_fifo. Address is multiplexed
|
463 |
|
|
between two values.
|
464 |
|
|
Address multiplexing:
|
465 |
|
|
pciw_wenable == 1 => ADDRA = pciw_waddr (write pointer of PCIW_FIFO)
|
466 |
|
|
else ADDRA = pcir_raddr (read pointer of PCIR_FIFO)
|
467 |
|
|
-----------------------------------------------------------------------------------------------------------*/
|
468 |
|
|
wire [7:0] portA_addr = pciw_wallow ? {pciw_addr_prefix, pciw_waddr} : {pcir_addr_prefix, pcir_raddr_calc} ;
|
469 |
|
|
|
470 |
|
|
/*-----------------------------------------------------------------------------------------------------------
|
471 |
|
|
Port B address generation for block SelectRam+ in SpartanII or Virtex
|
472 |
|
|
Port B is clocked by PCI clock, DIB is input for pcir_fifo, DOB is output for pciw_fifo. Address is multiplexed
|
473 |
|
|
between two values.
|
474 |
|
|
Address multiplexing:
|
475 |
|
|
pcir_wenable == 1 => ADDRB = pcir_waddr (write pointer of PCIR_FIFO)
|
476 |
|
|
else ADDRB = pciw_raddr (read pointer of PCIW_FIFO)
|
477 |
|
|
-----------------------------------------------------------------------------------------------------------*/
|
478 |
|
|
wire [7:0] portB_addr = pcir_wallow ? {pcir_addr_prefix, pcir_waddr} : {pciw_addr_prefix, pciw_raddr_calc} ;
|
479 |
|
|
|
480 |
|
|
// Block SelectRAM+ cells instantiation
|
481 |
|
|
RAMB4_S16_S16 dpram16_1 (.ADDRA(portA_addr), .DIA(pciw_addr_data_in[15:0]),
|
482 |
|
|
.ENA(portA_enable), .RSTA(reset_in),
|
483 |
|
|
.CLKA(pci_clock_in), .WEA(pciw_wallow),
|
484 |
|
|
.DOA(pcir_data_out[15:0]),
|
485 |
|
|
.ADDRB(portB_addr), .DIB(pcir_data_in[15:0]),
|
486 |
|
|
.ENB(portB_enable), .RSTB(reset_in),
|
487 |
|
|
.CLKB(wb_clock_in), .WEB(pcir_wallow),
|
488 |
|
|
.DOB(pciw_addr_data_out[15:0])) ;
|
489 |
|
|
|
490 |
|
|
RAMB4_S16_S16 dpram16_2 (.ADDRA(portA_addr), .DIA(pciw_addr_data_in[31:16]),
|
491 |
|
|
.ENA(portA_enable), .RSTA(reset_in),
|
492 |
|
|
.CLKA(pci_clock_in), .WEA(pciw_wallow),
|
493 |
|
|
.DOA(pcir_data_out[31:16]),
|
494 |
|
|
.ADDRB(portB_addr), .DIB(pcir_data_in[31:16]),
|
495 |
|
|
.ENB(portB_enable), .RSTB(reset_in),
|
496 |
|
|
.CLKB(wb_clock_in), .WEB(pcir_wallow),
|
497 |
|
|
.DOB(pciw_addr_data_out[31:16])) ;
|
498 |
|
|
|
499 |
|
|
RAMB4_S16_S16 dpram16_3 (.ADDRA(portA_addr), .DIA({pciw_control_in, 8'h00, pciw_cbe_in}),
|
500 |
|
|
.ENA(portA_enable), .RSTA(reset_in),
|
501 |
|
|
.CLKA(pci_clock_in), .WEA(pciw_wallow),
|
502 |
|
|
.DOA(dpram3_portA_output),
|
503 |
|
|
.ADDRB(portB_addr), .DIB({pcir_control_in, 8'h00, pcir_be_in}),
|
504 |
|
|
.ENB(portB_enable), .RSTB(reset_in),
|
505 |
|
|
.CLKB(wb_clock_in), .WEB(pcir_wallow),
|
506 |
|
|
.DOB(dpram3_portB_output)) ;
|
507 |
|
|
`endif
|
508 |
|
|
|
509 |
|
|
|
510 |
|
|
|
511 |
|
|
|
512 |
|
|
|
513 |
|
|
`else
|
514 |
|
|
wire [39:0] pciw_ram_data_out ;
|
515 |
|
|
wire [39:0] pciw_ram_data_in = {pciw_control_in, pciw_cbe_in, pciw_addr_data_in} ;
|
516 |
|
|
wire [39:0] pcir_ram_data_in = {pcir_control_in, pcir_be_in, pcir_data_in} ;
|
517 |
|
|
wire [39:0] pcir_ram_data_out ;
|
518 |
|
|
assign pciw_control_out = pciw_ram_data_out[39:36] ;
|
519 |
|
|
assign pciw_cbe_out = pciw_ram_data_out[35:32] ;
|
520 |
|
|
assign pciw_addr_data_out = pciw_ram_data_out [31:0] ;
|
521 |
|
|
|
522 |
|
|
assign pcir_control_out = pcir_ram_data_out[39:36] ;
|
523 |
|
|
assign pcir_be_out = pcir_ram_data_out[35:32] ;
|
524 |
|
|
assign pcir_data_out = pcir_ram_data_out [31:0] ;
|
525 |
|
|
|
526 |
|
|
`ifdef SYNCHRONOUS
|
527 |
|
|
/*-----------------------------------------------------------------------------------------------------------
|
528 |
|
|
ASIC memory primitives will be added here in the near future - currently there is only some generic,
|
529 |
|
|
behavioral dual port ram here
|
530 |
|
|
-----------------------------------------------------------------------------------------------------------*/
|
531 |
|
|
|
532 |
|
|
wire pciw_read_enable = pciw_rallow || pciw_empty ;
|
533 |
|
|
wire pcir_read_enable = pcir_rallow || pcir_empty ;
|
534 |
|
|
|
535 |
|
|
DP_SRAM #(PCIW_ADDR_LENGTH, PCIW_DEPTH) pciw_ram (.reset_in(reset_in), .wclock_in(pci_clock_in), .rclock_in(wb_clock_in), .data_in(pciw_ram_data_in),
|
536 |
|
|
.raddr_in(pciw_raddr), .waddr_in(pciw_waddr), .data_out(pciw_ram_data_out), .renable_in(pciw_read_enable), .wenable_in(pciw_wallow));
|
537 |
|
|
|
538 |
|
|
DP_SRAM #(PCIR_ADDR_LENGTH, PCIR_DEPTH) pcir_ram (.reset_in(reset_in), .wclock_in(wb_clock_in), .rclock_in(pci_clock_in), .data_in(pcir_ram_data_in),
|
539 |
|
|
.raddr_in(pcir_raddr), .waddr_in(pcir_waddr), .data_out(pcir_ram_data_out), .renable_in(pcir_read_enable), .wenable_in(pcir_wallow));
|
540 |
|
|
|
541 |
|
|
`else //ASYNCHRONOUS RAM
|
542 |
|
|
DP_ASYNC_RAM #(PCIW_ADDR_LENGTH, PCIW_DEPTH) pciw_ram (.reset_in(reset_in), .wclock_in(pci_clock_in), .data_in(pciw_ram_data_in),
|
543 |
|
|
.raddr_in(pciw_raddr), .waddr_in(pciw_waddr), .data_out(pciw_ram_data_out), .wenable_in(pciw_wallow));
|
544 |
|
|
|
545 |
|
|
DP_ASYNC_RAM #(PCIR_ADDR_LENGTH, PCIR_DEPTH) pcir_ram (.reset_in(reset_in), .wclock_in(wb_clock_in), .data_in(pcir_ram_data_in),
|
546 |
|
|
.raddr_in(pcir_raddr), .waddr_in(pcir_waddr), .data_out(pcir_ram_data_out), .wenable_in(pcir_wallow));
|
547 |
|
|
`endif
|
548 |
|
|
`endif
|
549 |
|
|
|
550 |
|
|
/*-----------------------------------------------------------------------------------------------------------
|
551 |
|
|
Instantiation of two control logic modules - one for PCIW_FIFO and one for PCIR_FIFO
|
552 |
|
|
-----------------------------------------------------------------------------------------------------------*/
|
553 |
|
|
PCIW_FIFO_CONTROL #(PCIW_ADDR_LENGTH) pciw_fifo_ctrl
|
554 |
|
|
(
|
555 |
|
|
.rclock_in(wb_clock_in),
|
556 |
|
|
.wclock_in(pci_clock_in),
|
557 |
|
|
.renable_in(pciw_renable_in),
|
558 |
|
|
.wenable_in(pciw_wenable_in),
|
559 |
|
|
.reset_in(reset_in),
|
560 |
|
|
.flush_in(pciw_flush_in),
|
561 |
|
|
.two_left_out(pciw_two_left_out),
|
562 |
|
|
.almost_full_out(pciw_almost_full_out),
|
563 |
|
|
.full_out(pciw_full_out),
|
564 |
|
|
.almost_empty_out(pciw_almost_empty_out),
|
565 |
|
|
.empty_out(pciw_empty),
|
566 |
|
|
.waddr_out(pciw_waddr),
|
567 |
|
|
.raddr_out(pciw_raddr),
|
568 |
|
|
.rallow_out(pciw_rallow),
|
569 |
|
|
.wallow_out(pciw_wallow)
|
570 |
|
|
);
|
571 |
|
|
|
572 |
|
|
FIFO_CONTROL #(PCIR_ADDR_LENGTH) pcir_fifo_ctrl
|
573 |
|
|
(
|
574 |
|
|
.rclock_in(pci_clock_in),
|
575 |
|
|
.wclock_in(wb_clock_in),
|
576 |
|
|
.renable_in(pcir_renable_in),
|
577 |
|
|
.wenable_in(pcir_wenable_in),
|
578 |
|
|
.reset_in(reset_in),
|
579 |
|
|
.flush_in(pcir_flush_in),
|
580 |
|
|
.almost_full_out(pcir_almost_full_out),
|
581 |
|
|
.full_out(pcir_full_out),
|
582 |
|
|
.almost_empty_out(pcir_almost_empty_out),
|
583 |
|
|
.empty_out(pcir_empty),
|
584 |
|
|
.waddr_out(pcir_waddr),
|
585 |
|
|
.raddr_out(pcir_raddr),
|
586 |
|
|
.rallow_out(pcir_rallow),
|
587 |
|
|
.wallow_out(pcir_wallow)
|
588 |
|
|
);
|
589 |
|
|
|
590 |
|
|
|
591 |
|
|
// in and out transaction counters and grey codes
|
592 |
|
|
reg [(PCIW_ADDR_LENGTH-2):0] inGreyCount ;
|
593 |
|
|
reg [(PCIW_ADDR_LENGTH-2):0] outGreyCount ;
|
594 |
|
|
wire [(PCIW_ADDR_LENGTH-2):0] inNextGreyCount = {pciw_inTransactionCount[(PCIW_ADDR_LENGTH-2)], pciw_inTransactionCount[(PCIW_ADDR_LENGTH-2):1] ^ pciw_inTransactionCount[(PCIW_ADDR_LENGTH-3):0]} ;
|
595 |
|
|
wire [(PCIW_ADDR_LENGTH-2):0] outNextGreyCount = {pciw_outTransactionCount[(PCIW_ADDR_LENGTH-2)], pciw_outTransactionCount[(PCIW_ADDR_LENGTH-2):1] ^ pciw_outTransactionCount[(PCIW_ADDR_LENGTH-3):0]} ;
|
596 |
|
|
|
597 |
|
|
wire in_count_en = pciw_wallow && pciw_last_in ;
|
598 |
|
|
wire out_count_en = pciw_renable_in && pciw_last_out ;
|
599 |
|
|
|
600 |
|
|
always@(posedge pci_clock_in or posedge pciw_clear)
|
601 |
|
|
begin
|
602 |
|
|
if (pciw_clear)
|
603 |
|
|
begin
|
604 |
|
|
inGreyCount[(PCIW_ADDR_LENGTH-2)] <= #`FF_DELAY 1'b1 ;
|
605 |
|
|
inGreyCount[(PCIW_ADDR_LENGTH-3):0] <= #`FF_DELAY {(PCIW_ADDR_LENGTH-2),1'b0} ;
|
606 |
|
|
end
|
607 |
|
|
else
|
608 |
|
|
if (in_count_en)
|
609 |
|
|
inGreyCount <= #`FF_DELAY inNextGreyCount ;
|
610 |
|
|
end
|
611 |
|
|
|
612 |
|
|
always@(posedge wb_clock_in or posedge pciw_clear)
|
613 |
|
|
begin
|
614 |
|
|
if (pciw_clear)
|
615 |
|
|
begin
|
616 |
|
|
outGreyCount[(PCIW_ADDR_LENGTH-2)] <= #`FF_DELAY 1'b1 ;
|
617 |
|
|
outGreyCount[(PCIW_ADDR_LENGTH-3):0] <= #`FF_DELAY {(PCIW_ADDR_LENGTH-2),1'b0} ;
|
618 |
|
|
end
|
619 |
|
|
else
|
620 |
|
|
if (out_count_en)
|
621 |
|
|
outGreyCount <= #`FF_DELAY outNextGreyCount ;
|
622 |
|
|
end
|
623 |
|
|
|
624 |
|
|
always@(posedge pci_clock_in or posedge pciw_clear)
|
625 |
|
|
begin
|
626 |
|
|
if (pciw_clear)
|
627 |
|
|
pciw_inTransactionCount <= #`FF_DELAY {(PCIW_ADDR_LENGTH-1){1'b0}} ;
|
628 |
|
|
else
|
629 |
|
|
if (in_count_en)
|
630 |
|
|
pciw_inTransactionCount <= #`FF_DELAY pciw_inTransactionCount + 1'b1 ;
|
631 |
|
|
end
|
632 |
|
|
|
633 |
|
|
always@(posedge wb_clock_in or posedge pciw_clear)
|
634 |
|
|
begin
|
635 |
|
|
if (pciw_clear)
|
636 |
|
|
pciw_outTransactionCount <= #`FF_DELAY {(PCIW_ADDR_LENGTH-1){1'b0}} ;
|
637 |
|
|
else
|
638 |
|
|
if (out_count_en)
|
639 |
|
|
pciw_outTransactionCount <= #`FF_DELAY pciw_outTransactionCount + 1'b1 ;
|
640 |
|
|
end
|
641 |
|
|
|
642 |
|
|
/*always@(posedge wb_clock_in or posedge pcir_clear)
|
643 |
|
|
begin
|
644 |
|
|
if (pcir_clear)
|
645 |
|
|
pcir_inTransactionCount <= #`FF_DELAY 1'b0 ;
|
646 |
|
|
else
|
647 |
|
|
if (pcir_last_in && pcir_wallow)
|
648 |
|
|
pcir_inTransactionCount <= #`FF_DELAY ~pcir_inTransactionCount ;
|
649 |
|
|
end
|
650 |
|
|
|
651 |
|
|
always@(posedge pci_clock_in or posedge pcir_clear)
|
652 |
|
|
begin
|
653 |
|
|
if (pcir_clear)
|
654 |
|
|
pcir_outTransactionCount <= #`FF_DELAY 1'b0 ;
|
655 |
|
|
else
|
656 |
|
|
if (pcir_last_out)
|
657 |
|
|
pcir_outTransactionCount <= #`FF_DELAY ~pcir_outTransactionCount ;
|
658 |
|
|
end
|
659 |
|
|
*/
|
660 |
|
|
|
661 |
|
|
reg pciw_transaction_ready_out ;
|
662 |
|
|
always@(posedge wb_clock_in or posedge pciw_clear)
|
663 |
|
|
begin
|
664 |
|
|
if (pciw_clear)
|
665 |
|
|
pciw_transaction_ready_out <= #`FF_DELAY 1'b0 ;
|
666 |
|
|
else
|
667 |
|
|
if ( out_count_en )
|
668 |
|
|
pciw_transaction_ready_out <= #`FF_DELAY 1'b0 ;
|
669 |
|
|
else
|
670 |
|
|
pciw_transaction_ready_out <= #`FF_DELAY inGreyCount != outGreyCount ;
|
671 |
|
|
end
|
672 |
|
|
|
673 |
|
|
assign pcir_transaction_ready_out = 1'b0 ;
|
674 |
|
|
|
675 |
|
|
endmodule
|
676 |
|
|
|