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[/] [pci/] [tags/] [working_demo/] [rtl/] [verilog/] [pciw_pcir_fifos.v] - Blame information for rev 154

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1 2 mihad
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  File name "pciw_pcir_fifos.v"                               ////
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////                                                              ////
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////  This file is part of the "PCI bridge" project               ////
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////  http://www.opencores.org/cores/pci/                         ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Miha Dolenc (mihad@opencores.org)                     ////
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////                                                              ////
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////  All additional information is avaliable in the README       ////
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////  file.                                                       ////
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////                                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Miha Dolenc, mihad@opencores.org          ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
41
//
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// CVS Revision History
43
//
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// $Log: not supported by cvs2svn $
45 6 mihad
// Revision 1.1.1.1  2001/10/02 15:33:47  mihad
46
// New project directory structure
47 2 mihad
//
48 6 mihad
//
49 2 mihad
 
50
`include "constants.v"
51 6 mihad
`include "timescale.v"
52 2 mihad
 
53
module PCIW_PCIR_FIFOS
54
(
55
    wb_clock_in,
56
    pci_clock_in,
57
    reset_in,
58
    pciw_wenable_in,
59
    pciw_addr_data_in,
60
    pciw_cbe_in,
61
    pciw_control_in,
62
    pciw_renable_in,
63
    pciw_addr_data_out,
64
    pciw_cbe_out,
65
    pciw_control_out,
66
    pciw_flush_in,
67
    pciw_two_left_out,
68
    pciw_almost_full_out,
69
    pciw_full_out,
70
    pciw_almost_empty_out,
71
    pciw_empty_out,
72
    pciw_transaction_ready_out,
73
    pcir_wenable_in,
74
    pcir_data_in,
75
    pcir_be_in,
76
    pcir_control_in,
77
    pcir_renable_in,
78
    pcir_data_out,
79
    pcir_be_out,
80
    pcir_control_out,
81
    pcir_flush_in,
82
    pcir_almost_full_out,
83
    pcir_full_out,
84
    pcir_almost_empty_out,
85
    pcir_empty_out,
86
    pcir_transaction_ready_out
87
) ;
88
 
89
/*-----------------------------------------------------------------------------------------------------------
90
System inputs:
91
wb_clock_in - WISHBONE bus clock
92
pci_clock_in - PCI bus clock
93
reset_in - reset from control logic
94
-------------------------------------------------------------------------------------------------------------*/
95
input wb_clock_in, pci_clock_in, reset_in ;
96
 
97
/*-----------------------------------------------------------------------------------------------------------
98
PCI WRITE FIFO interface signals prefixed with pciw_ - FIFO is used for posted writes initiated by external
99
PCI master through PCI target interface, traveling through FIFO and are completed on WISHBONE by
100
WISHBONE master interface
101
 
102
write enable signal:
103
pciw_wenable_in = write enable input for PCIW_FIFO - driven by PCI TARGET interface
104
 
105
data input signals:
106
pciw_addr_data_in = data input - data from PCI bus - first entry of transaction is address others are data entries
107
pciw_cbe_in       = bus command/byte enable(~#BE[3:0]) input - first entry of transaction is bus command, other are byte enables
108
pciw_control_in   = control input - encoded control bus input
109
 
110
read enable signal:
111
pciw_renable_in = read enable input driven by WISHBONE master interface
112
 
113
data output signals:
114
pciw_addr_data_out = data output - data from PCI bus - first entry of transaction is address, others are data entries
115
pciw_cbe_out      = bus command/byte enable output - first entry of transaction is bus command, others are byte enables
116
pciw_control_out = control input - encoded control bus input
117
 
118
status signals - monitored by various resources in the core
119
pciw_flush_in = flush signal input for PCIW_FIFO - when asserted, fifo is flushed(emptied)
120
pciw_almost_full_out = almost full output from PCIW_FIFO
121
pciw_full_out = full output from PCIW_FIFO
122
pciw_almost_empty_out = almost empty output from PCIW_FIFO
123
pciw_empty_out = empty output from PCIW_FIFO
124
pciw_transaction_ready_out = output indicating that one complete transaction is waiting in PCIW_FIFO
125
-----------------------------------------------------------------------------------------------------------*/
126
// input control and data
127
input        pciw_wenable_in ;
128
input [31:0] pciw_addr_data_in ;
129
input [3:0]  pciw_cbe_in ;
130
input [3:0]  pciw_control_in ;
131
 
132
// output control and data
133
input         pciw_renable_in ;
134
output [31:0] pciw_addr_data_out ;
135
output [3:0]  pciw_cbe_out ;
136
output [3:0]  pciw_control_out ;
137
 
138
// flush input
139
input pciw_flush_in ;
140
 
141
// status outputs
142
output pciw_two_left_out ;
143
output pciw_almost_full_out ;
144
output pciw_full_out ;
145
output pciw_almost_empty_out ;
146
output pciw_empty_out ;
147
output pciw_transaction_ready_out ;
148
 
149
/*-----------------------------------------------------------------------------------------------------------
150
PCI READ FIFO interface signals prefixed with pcir_ - FIFO is used for holding delayed read completions
151
initiated by master on PCI bus and completed on WISHBONE bus,
152
 
153
write enable signal:
154
pcir_wenable_in = write enable input for PCIR_FIFO - driven by WISHBONE master interface
155
 
156
data input signals:
157
pcir_data_in      = data input - data from WISHBONE bus - there is no address entry here, since address is stored in separate register
158
pcir_be_in        = byte enable(~SEL[3:0]) input - byte enables - same through one transaction
159
pcir_control_in   = control input - encoded control bus input
160
 
161
read enable signal:
162
pcir_renable_in = read enable input driven by PCI target interface
163
 
164
data output signals:
165
pcir_data_out = data output - data from WISHBONE bus
166
pcir_be_out      = byte enable output(~SEL)
167
pcir_control_out = control output - encoded control bus output
168
 
169
status signals - monitored by various resources in the core
170
pcir_flush_in = flush signal input for PCIR_FIFO - when asserted, fifo is flushed(emptied)
171
pcir_almost_full_out = almost full output from PCIR_FIFO
172
pcir full_out = full output from PCIR_FIFO
173
pcir_almost_empty_out = almost empty output from PCIR_FIFO
174
pcir_empty_out = empty output from PCIR_FIFO
175
pcir_transaction_ready_out = output indicating that one complete transaction is waiting in PCIR_FIFO
176
-----------------------------------------------------------------------------------------------------------*/
177
// input control and data
178
input        pcir_wenable_in ;
179
input [31:0] pcir_data_in ;
180
input [3:0]  pcir_be_in ;
181
input [3:0]  pcir_control_in ;
182
 
183
// output control and data
184
input         pcir_renable_in ;
185
output [31:0] pcir_data_out ;
186
output [3:0]  pcir_be_out ;
187
output [3:0]  pcir_control_out ;
188
 
189
// flush input
190
input pcir_flush_in ;
191
 
192
// status outputs
193
output pcir_almost_full_out ;
194
output pcir_full_out ;
195
output pcir_almost_empty_out ;
196
output pcir_empty_out ;
197
output pcir_transaction_ready_out ;
198
 
199
/*-----------------------------------------------------------------------------------------------------------
200
Address length parameters:
201
PCIW_DEPTH = defines PCIW_FIFO depth
202
PCIR_DEPTH = defines PCIR_FIFO depth
203
PCIW_ADDR_LENGTH = defines PCIW_FIFO's location address length - log2(PCIW_DEPTH)
204
PCIR_ADDR_LENGTH = defines PCIR_FIFO's location address length - log2(PCIR_DEPTH)
205
-----------------------------------------------------------------------------------------------------------*/
206
parameter PCIW_DEPTH = `PCIW_DEPTH ;
207
parameter PCIW_ADDR_LENGTH = `PCIW_ADDR_LENGTH ;
208
parameter PCIR_DEPTH = `PCIR_DEPTH ;
209
parameter PCIR_ADDR_LENGTH = `PCIR_ADDR_LENGTH ;
210
 
211
// obvious
212
wire vcc = 1'b1 ;
213
wire gnd = 1'b0 ;
214
 
215
/*-----------------------------------------------------------------------------------------------------------
216
pciw_wallow = PCIW_FIFO write allow wire - writes to FIFO are allowed when FIFO isn't full and write enable is 1
217
pciw_rallow = PCIW_FIFO read allow wire - reads from FIFO are allowed when FIFO isn't empty and read enable is 1
218
-----------------------------------------------------------------------------------------------------------*/
219
wire pciw_wallow ;
220
wire pciw_rallow ;
221
 
222
/*-----------------------------------------------------------------------------------------------------------
223
pcir_wallow = PCIR_FIFO write allow wire - writes to FIFO are allowed when FIFO isn't full and write enable is 1
224
pcir_rallow = PCIR_FIFO read allow wire - reads from FIFO are allowed when FIFO isn't empty and read enable is 1
225
-----------------------------------------------------------------------------------------------------------*/
226
wire pcir_wallow ;
227
wire pcir_rallow ;
228
 
229
/*-----------------------------------------------------------------------------------------------------------
230
wires for address port conections from PCIW_FIFO control logic to RAM blocks used for PCIW_FIFO
231
-----------------------------------------------------------------------------------------------------------*/
232
wire [(PCIW_ADDR_LENGTH - 1):0] pciw_raddr ;
233
wire [(PCIW_ADDR_LENGTH - 1):0] pciw_waddr ;
234
 
235
/*-----------------------------------------------------------------------------------------------------------
236
wires for address port conections from PCIR_FIFO control logic to RAM blocks used for PCIR_FIFO
237
-----------------------------------------------------------------------------------------------------------*/
238
wire [(PCIR_ADDR_LENGTH - 1):0] pcir_raddr ;
239
wire [(PCIR_ADDR_LENGTH - 1):0] pcir_waddr ;
240
 
241
/*-----------------------------------------------------------------------------------------------------------
242
PCIW_FIFO transaction counters: used to count incoming transactions and outgoing transactions. When number of
243
input transactions is equal to number of output transactions, it means that there isn't any complete transaction
244
currently present in the FIFO.
245
-----------------------------------------------------------------------------------------------------------*/
246
reg [(PCIW_ADDR_LENGTH - 1):0] pciw_inTransactionCount ;
247
reg [(PCIW_ADDR_LENGTH - 1):0] pciw_outTransactionCount ;
248
 
249
/*-----------------------------------------------------------------------------------------------------------
250
FlipFlops for indicating if complete delayed read completion is present in the FIFO
251
-----------------------------------------------------------------------------------------------------------*/
252
/*reg pcir_inTransactionCount ;
253
reg pcir_outTransactionCount ;*/
254
/*-----------------------------------------------------------------------------------------------------------
255
wires monitoring control bus. When control bus on a write transaction has a value of `LAST, it means that
256
complete transaction is in the FIFO. When control bus on a read transaction has a value of `LAST,
257
it means that there was one complete transaction taken out of FIFO.
258
-----------------------------------------------------------------------------------------------------------*/
259
wire pciw_last_in  = pciw_control_in[`LAST_CTRL_BIT] ;
260
wire pciw_last_out = pciw_control_out[`LAST_CTRL_BIT] ;
261
 
262
/*wire pcir_last_in  = pcir_wallow && (pcir_control_in == `LAST) ;
263
wire pcir_last_out = pcir_rallow && (pcir_control_out == `LAST) ;*/
264
 
265
wire pciw_empty ;
266
wire pcir_empty ;
267
 
268
assign pciw_empty_out = pciw_empty ;
269
assign pcir_empty_out = pcir_empty ;
270
 
271
// clear wires for clearing FFs and registers
272
wire pciw_clear = reset_in || pciw_flush_in ; // PCIW_FIFO's clear signal
273
wire pcir_clear = reset_in || pcir_flush_in ; // PCIR_FIFO's clear signal
274
 
275
`ifdef FPGA
276
/*-----------------------------------------------------------------------------------------------------------
277
this code is included only for FPGA core usage - somewhat different logic because of sharing
278
one block selectRAM+ between two FIFOs
279
-----------------------------------------------------------------------------------------------------------*/
280
    `ifdef BIG
281
        /*-----------------------------------------------------------------------------------------------------------
282
        Big FPGAs
283
        PCIW_FIFO and PCIR_FIFO address prefixes - used for extending read and write addresses because of varible
284
        FIFO depth and fixed SelectRAM+ size. Addresses are zero paded on the left to form long enough address
285
        -----------------------------------------------------------------------------------------------------------*/
286
        wire [(7 - PCIW_ADDR_LENGTH):0] pciw_addr_prefix = {( 8 - PCIW_ADDR_LENGTH){1'b0}} ;
287
        wire [(7 - PCIR_ADDR_LENGTH):0] pcir_addr_prefix = {( 8 - PCIR_ADDR_LENGTH){1'b0}} ;
288
 
289
        // compose addresses
290
        wire [7:0] pciw_whole_waddr = {pciw_addr_prefix, pciw_waddr} ;
291
        wire [7:0] pciw_whole_raddr = {pciw_addr_prefix, pciw_raddr} ;
292
 
293
        wire [7:0] pcir_whole_waddr = {pcir_addr_prefix, pcir_waddr} ;
294
        wire [7:0] pcir_whole_raddr = {pcir_addr_prefix, pcir_raddr} ;
295
 
296
        /*-----------------------------------------------------------------------------------------------------------
297
        Only 8 bits out of 16 are used in ram3 and ram6 - wires for referencing them
298
        -----------------------------------------------------------------------------------------------------------*/
299
        wire [15:0] dpram3_portB_output ;
300
        wire [15:0] dpram6_portA_output ;
301
 
302
        /*-----------------------------------------------------------------------------------------------------------
303
        Control out assignements from ram3 output
304
        -----------------------------------------------------------------------------------------------------------*/
305
        assign pciw_control_out = dpram3_portB_output[15:12] ;
306
        assign pcir_control_out = dpram6_portA_output[15:12] ;
307
 
308
        assign pciw_cbe_out = dpram3_portB_output[3:0] ;
309
        assign pcir_be_out  = dpram6_portA_output[3:0] ;
310
 
311
        wire pciw_read_enable = pciw_rallow || pciw_empty ;
312
        wire pcir_read_enable = pcir_rallow || pcir_empty ;
313
 
314
        // Block SelectRAM+ cells instantiation
315
        RAMB4_S16_S16 dpram16_1 (.ADDRA(pciw_whole_waddr), .DIA(pciw_addr_data_in[15:0]),
316
                                 .ENA(vcc), .RSTA(reset_in),
317
                                 .CLKA(pci_clock_in), .WEA(pciw_wallow),
318
                                 .DOA(),
319
                                 .ADDRB(pciw_whole_raddr), .DIB(16'h0000),
320
                                 .ENB(pciw_read_enable), .RSTB(reset_in),
321
                                 .CLKB(wb_clock_in), .WEB(gnd),
322
                                 .DOB(pciw_addr_data_out[15:0])) ;
323
 
324
        RAMB4_S16_S16 dpram16_2 (.ADDRA(pciw_whole_waddr), .DIA(pciw_addr_data_in[31:16]),
325
                                 .ENA(vcc), .RSTA(reset_in),
326
                                 .CLKA(pci_clock_in), .WEA(pciw_wallow),
327
                                 .DOA(),
328
                                 .ADDRB(pciw_whole_raddr), .DIB(16'h0000),
329
                                 .ENB(pciw_read_enable), .RSTB(reset_in),
330
                                 .CLKB(wb_clock_in), .WEB(gnd),
331
                                 .DOB(pciw_addr_data_out[31:16])) ;
332
 
333
        RAMB4_S16_S16 dpram16_3 (.ADDRA(pciw_whole_waddr), .DIA({pciw_control_in, 8'h00, pciw_cbe_in}),
334
                                 .ENA(vcc), .RSTA(reset_in),
335
                                 .CLKA(pci_clock_in), .WEA(pciw_wallow),
336
                                 .DOA(),
337
                                 .ADDRB(pciw_whole_raddr), .DIB(16'h0000),
338
                                 .ENB(pciw_read_enable), .RSTB(reset_in),
339
                                 .CLKB(wb_clock_in), .WEB(gnd),
340
                                 .DOB(dpram3_portB_output)) ;
341
 
342
        RAMB4_S16_S16 dpram16_4 (.ADDRA(pcir_whole_raddr), .DIA(16'h0000),
343
                                 .ENA(pcir_read_enable), .RSTA(reset_in),
344
                                 .CLKA(pci_clock_in), .WEA(gnd),
345
                                 .DOA(pcir_data_out[15:0]),
346
                                 .ADDRB(pcir_whole_waddr), .DIB(pcir_data_in[15:0]),
347
                                 .ENB(vcc), .RSTB(reset_in),
348
                                 .CLKB(wb_clock_in), .WEB(pcir_wallow),
349
                                 .DOB()) ;
350
 
351
        RAMB4_S16_S16 dpram16_5 (.ADDRA(pcir_whole_raddr), .DIA(16'h0000),
352
                                 .ENA(pcir_read_enable), .RSTA(reset_in),
353
                                 .CLKA(pci_clock_in), .WEA(gnd),
354
                                 .DOA(pcir_data_out[31:16]),
355
                                 .ADDRB(pcir_whole_waddr), .DIB(pcir_data_in[31:16]),
356
                                 .ENB(vcc), .RSTB(reset_in),
357
                                 .CLKB(wb_clock_in), .WEB(pcir_wallow),
358
                                 .DOB()) ;
359
 
360
        RAMB4_S16_S16 dpram16_6 (.ADDRA(pcir_whole_raddr), .DIA(16'h0000),
361
                                 .ENA(pcir_read_enable), .RSTA(reset_in),
362
                                 .CLKA(pci_clock_in), .WEA(gnd),
363
                                 .DOA(dpram6_portA_output),
364
                                 .ADDRB(pcir_whole_waddr), .DIB({pcir_control_in, 8'h00, pcir_be_in}),
365
                                 .ENB(vcc), .RSTB(reset_in),
366
                                 .CLKB(wb_clock_in), .WEB(pcir_wallow),
367
                                 .DOB()) ;
368
 
369
    `else // SMALL FPGAs
370
 
371
        /*-----------------------------------------------------------------------------------------------------------
372
        Small FPGAs
373
        PCIW_FIFO and PCIR_FIFO address prefixes - used for extending read and write addresses because of varible
374
        FIFO depth and fixed SelectRAM+ size. Addresses are always paded, because of RAM sharing between FIFOs
375
        PCIW addresses are zero padded on the left, PCIR addresses are padded
376
        with ones on the left
377
        -----------------------------------------------------------------------------------------------------------*/
378
        wire [(7 - PCIW_ADDR_LENGTH):0] pciw_addr_prefix = {( 8 - PCIW_ADDR_LENGTH){1'b0}} ;
379
        wire [(7 - PCIR_ADDR_LENGTH):0] pcir_addr_prefix = {( 8 - PCIR_ADDR_LENGTH){1'b1}} ;
380
 
381
        /*-----------------------------------------------------------------------------------------------------------
382
        Only 8 bits out of 16 are used in ram3 - wires for referencing them
383
        -----------------------------------------------------------------------------------------------------------*/
384
        wire [15:0] dpram3_portA_output ;
385
        wire [15:0] dpram3_portB_output ;
386
 
387
        /*-----------------------------------------------------------------------------------------------------------
388
        Control out assignements from ram3 output
389
        -----------------------------------------------------------------------------------------------------------*/
390
        assign pciw_control_out = dpram3_portB_output[15:12] ;
391
        assign pcir_control_out = dpram3_portA_output[15:12] ;
392
 
393
        assign pciw_cbe_out = dpram3_portB_output[3:0] ;
394
        assign pcir_be_out  = dpram3_portA_output[3:0] ;
395
 
396
        /*-----------------------------------------------------------------------------------------------------------
397
        Logic used for extending port's enable input for one clock cycle to allow address and date change from
398
        PCI write fifo's write address and data back to PCI read fifo's address and data ( turnaround cycle )
399
        -----------------------------------------------------------------------------------------------------------*/
400
        reg pciw_write_performed ;
401
        always@(posedge pci_clock_in or posedge reset_in)
402
        begin
403
            if (reset_in)
404
                pciw_write_performed <= #`FF_DELAY 1'b0 ;
405
            else
406
                pciw_write_performed <= #`FF_DELAY pciw_wallow ;
407
        end
408
 
409
        /*-----------------------------------------------------------------------------------------------------------
410
        Logic used for extending port's enable input for one clock cycle to allow address and date change from
411
        PCI read fifo's write address and data back to PCI write fifo's address and data ( turnaround cycle )
412
        -----------------------------------------------------------------------------------------------------------*/
413
        reg pcir_write_performed ;
414
        always@(posedge wb_clock_in or posedge reset_in)
415
        begin
416
            if (reset_in)
417
                pcir_write_performed <= #`FF_DELAY 1'b0 ;
418
            else
419
                pcir_write_performed <= #`FF_DELAY pcir_wallow ;
420
        end
421
 
422
        /*-----------------------------------------------------------------------------------------------------------
423
        Additional register storing actual PCIW read address. It must be applied to port B during turnaround cycle
424
        -----------------------------------------------------------------------------------------------------------*/
425
        reg [(PCIW_ADDR_LENGTH - 1):0] pciw_raddr_0 ;
426
 
427
        always@(posedge wb_clock_in or posedge pciw_clear)
428
        begin
429
            if (pciw_clear)
430
                pciw_raddr_0 <= #`FF_DELAY {PCIW_ADDR_LENGTH{1'b0}} ;
431
            else
432
                if(pciw_rallow)
433
                    pciw_raddr_0 <= #`FF_DELAY pciw_raddr ;
434
        end
435
 
436
        wire [(PCIW_ADDR_LENGTH - 1):0] pciw_raddr_calc = pcir_write_performed ? pciw_raddr_0 : pciw_raddr ;
437
 
438
        /*-----------------------------------------------------------------------------------------------------------
439
        Additional register storing actual PCIR read address. It must be applied to port A during turnaround cycle
440
        -----------------------------------------------------------------------------------------------------------*/
441
        reg [(PCIR_ADDR_LENGTH - 1):0] pcir_raddr_0 ;
442
 
443
        always@(posedge pci_clock_in or posedge pcir_clear)
444
        begin
445
            if(pcir_clear)
446
                pcir_raddr_0 <= #`FF_DELAY {PCIR_ADDR_LENGTH{1'b0}} ;
447
            else
448
                if(pcir_rallow)
449
                    pcir_raddr_0 <= #`FF_DELAY pcir_raddr ;
450
        end
451
 
452
        wire [(PCIR_ADDR_LENGTH - 1):0] pcir_raddr_calc = pciw_write_performed ? pcir_raddr_0 : pcir_raddr ;
453
 
454
        /*-----------------------------------------------------------------------------------------------------------
455
        Port A and B enables
456
        -----------------------------------------------------------------------------------------------------------*/
457
        wire portA_enable = pciw_wallow || pcir_rallow || pcir_empty || pciw_write_performed ;
458
        wire portB_enable = pcir_wallow || pciw_rallow || pciw_empty || pcir_write_performed ;
459
 
460
        /*-----------------------------------------------------------------------------------------------------------
461
        Port A address generation for block SelectRam+ in SpartanII or Virtex
462
        Port A is clocked by PCI clock, DIA is input for pciw_fifo, DOA is output for pcir_fifo. Address is multiplexed
463
        between two values.
464
        Address multiplexing:
465
        pciw_wenable == 1 => ADDRA = pciw_waddr (write pointer of PCIW_FIFO)
466
        else                ADDRA = pcir_raddr (read pointer of PCIR_FIFO)
467
        -----------------------------------------------------------------------------------------------------------*/
468
        wire [7:0] portA_addr = pciw_wallow ? {pciw_addr_prefix, pciw_waddr} : {pcir_addr_prefix, pcir_raddr_calc} ;
469
 
470
        /*-----------------------------------------------------------------------------------------------------------
471
        Port B address generation for block SelectRam+ in SpartanII or Virtex
472
        Port B is clocked by PCI clock, DIB is input for pcir_fifo, DOB is output for pciw_fifo. Address is multiplexed
473
        between two values.
474
        Address multiplexing:
475
        pcir_wenable == 1 => ADDRB = pcir_waddr (write pointer of PCIR_FIFO)
476
        else                ADDRB = pciw_raddr (read pointer of PCIW_FIFO)
477
        -----------------------------------------------------------------------------------------------------------*/
478
        wire [7:0] portB_addr = pcir_wallow ? {pcir_addr_prefix, pcir_waddr} : {pciw_addr_prefix, pciw_raddr_calc} ;
479
 
480
        // Block SelectRAM+ cells instantiation
481
        RAMB4_S16_S16 dpram16_1 (.ADDRA(portA_addr), .DIA(pciw_addr_data_in[15:0]),
482
                                 .ENA(portA_enable), .RSTA(reset_in),
483
                                 .CLKA(pci_clock_in), .WEA(pciw_wallow),
484
                                 .DOA(pcir_data_out[15:0]),
485
                                 .ADDRB(portB_addr), .DIB(pcir_data_in[15:0]),
486
                                 .ENB(portB_enable), .RSTB(reset_in),
487
                                 .CLKB(wb_clock_in), .WEB(pcir_wallow),
488
                                 .DOB(pciw_addr_data_out[15:0])) ;
489
 
490
        RAMB4_S16_S16 dpram16_2 (.ADDRA(portA_addr), .DIA(pciw_addr_data_in[31:16]),
491
                                 .ENA(portA_enable), .RSTA(reset_in),
492
                                 .CLKA(pci_clock_in), .WEA(pciw_wallow),
493
                                 .DOA(pcir_data_out[31:16]),
494
                                 .ADDRB(portB_addr), .DIB(pcir_data_in[31:16]),
495
                                 .ENB(portB_enable), .RSTB(reset_in),
496
                                 .CLKB(wb_clock_in), .WEB(pcir_wallow),
497
                                 .DOB(pciw_addr_data_out[31:16])) ;
498
 
499
        RAMB4_S16_S16 dpram16_3 (.ADDRA(portA_addr), .DIA({pciw_control_in, 8'h00, pciw_cbe_in}),
500
                                 .ENA(portA_enable), .RSTA(reset_in),
501
                                 .CLKA(pci_clock_in), .WEA(pciw_wallow),
502
                                 .DOA(dpram3_portA_output),
503
                                 .ADDRB(portB_addr), .DIB({pcir_control_in, 8'h00, pcir_be_in}),
504
                                 .ENB(portB_enable), .RSTB(reset_in),
505
                                 .CLKB(wb_clock_in), .WEB(pcir_wallow),
506
                                 .DOB(dpram3_portB_output)) ;
507
    `endif
508
 
509
 
510
 
511
 
512
 
513
`else
514
    wire [39:0] pciw_ram_data_out ;
515
    wire [39:0] pciw_ram_data_in = {pciw_control_in, pciw_cbe_in, pciw_addr_data_in} ;
516
    wire [39:0] pcir_ram_data_in = {pcir_control_in, pcir_be_in, pcir_data_in} ;
517
    wire [39:0] pcir_ram_data_out ;
518
    assign pciw_control_out   = pciw_ram_data_out[39:36] ;
519
    assign pciw_cbe_out       = pciw_ram_data_out[35:32] ;
520
    assign pciw_addr_data_out = pciw_ram_data_out [31:0] ;
521
 
522
    assign pcir_control_out   = pcir_ram_data_out[39:36] ;
523
    assign pcir_be_out        = pcir_ram_data_out[35:32] ;
524
    assign pcir_data_out      = pcir_ram_data_out [31:0] ;
525
 
526
    `ifdef SYNCHRONOUS
527
    /*-----------------------------------------------------------------------------------------------------------
528
    ASIC memory primitives will be added here in the near future - currently there is only some generic,
529
    behavioral dual port ram here
530
    -----------------------------------------------------------------------------------------------------------*/
531
 
532
    wire pciw_read_enable = pciw_rallow || pciw_empty ;
533
    wire pcir_read_enable = pcir_rallow || pcir_empty ;
534
 
535
    DP_SRAM #(PCIW_ADDR_LENGTH, PCIW_DEPTH) pciw_ram (.reset_in(reset_in), .wclock_in(pci_clock_in), .rclock_in(wb_clock_in), .data_in(pciw_ram_data_in),
536
                    .raddr_in(pciw_raddr), .waddr_in(pciw_waddr), .data_out(pciw_ram_data_out), .renable_in(pciw_read_enable), .wenable_in(pciw_wallow));
537
 
538
    DP_SRAM #(PCIR_ADDR_LENGTH, PCIR_DEPTH) pcir_ram (.reset_in(reset_in), .wclock_in(wb_clock_in), .rclock_in(pci_clock_in), .data_in(pcir_ram_data_in),
539
                    .raddr_in(pcir_raddr), .waddr_in(pcir_waddr), .data_out(pcir_ram_data_out), .renable_in(pcir_read_enable), .wenable_in(pcir_wallow));
540
 
541
    `else //ASYNCHRONOUS RAM
542
        DP_ASYNC_RAM #(PCIW_ADDR_LENGTH, PCIW_DEPTH) pciw_ram (.reset_in(reset_in), .wclock_in(pci_clock_in), .data_in(pciw_ram_data_in),
543
                    .raddr_in(pciw_raddr), .waddr_in(pciw_waddr), .data_out(pciw_ram_data_out), .wenable_in(pciw_wallow));
544
 
545
        DP_ASYNC_RAM #(PCIR_ADDR_LENGTH, PCIR_DEPTH) pcir_ram (.reset_in(reset_in), .wclock_in(wb_clock_in), .data_in(pcir_ram_data_in),
546
                    .raddr_in(pcir_raddr), .waddr_in(pcir_waddr), .data_out(pcir_ram_data_out), .wenable_in(pcir_wallow));
547
    `endif
548
`endif
549
 
550
/*-----------------------------------------------------------------------------------------------------------
551
Instantiation of two control logic modules - one for PCIW_FIFO and one for PCIR_FIFO
552
-----------------------------------------------------------------------------------------------------------*/
553
PCIW_FIFO_CONTROL #(PCIW_ADDR_LENGTH) pciw_fifo_ctrl
554
(
555
    .rclock_in(wb_clock_in),
556
    .wclock_in(pci_clock_in),
557
    .renable_in(pciw_renable_in),
558
    .wenable_in(pciw_wenable_in),
559
    .reset_in(reset_in),
560
    .flush_in(pciw_flush_in),
561
    .two_left_out(pciw_two_left_out),
562
    .almost_full_out(pciw_almost_full_out),
563
    .full_out(pciw_full_out),
564
    .almost_empty_out(pciw_almost_empty_out),
565
    .empty_out(pciw_empty),
566
    .waddr_out(pciw_waddr),
567
    .raddr_out(pciw_raddr),
568
    .rallow_out(pciw_rallow),
569
    .wallow_out(pciw_wallow)
570
);
571
 
572
FIFO_CONTROL #(PCIR_ADDR_LENGTH) pcir_fifo_ctrl
573
(
574
    .rclock_in(pci_clock_in),
575
    .wclock_in(wb_clock_in),
576
    .renable_in(pcir_renable_in),
577
    .wenable_in(pcir_wenable_in),
578
    .reset_in(reset_in),
579
    .flush_in(pcir_flush_in),
580
    .almost_full_out(pcir_almost_full_out),
581
    .full_out(pcir_full_out),
582
    .almost_empty_out(pcir_almost_empty_out),
583
    .empty_out(pcir_empty),
584
    .waddr_out(pcir_waddr),
585
    .raddr_out(pcir_raddr),
586
    .rallow_out(pcir_rallow),
587
    .wallow_out(pcir_wallow)
588
);
589
 
590
 
591
// in and out transaction counters and grey codes
592
reg  [(PCIW_ADDR_LENGTH-2):0] inGreyCount ;
593
reg  [(PCIW_ADDR_LENGTH-2):0] outGreyCount ;
594
wire [(PCIW_ADDR_LENGTH-2):0] inNextGreyCount  = {pciw_inTransactionCount[(PCIW_ADDR_LENGTH-2)], pciw_inTransactionCount[(PCIW_ADDR_LENGTH-2):1] ^ pciw_inTransactionCount[(PCIW_ADDR_LENGTH-3):0]} ;
595
wire [(PCIW_ADDR_LENGTH-2):0] outNextGreyCount = {pciw_outTransactionCount[(PCIW_ADDR_LENGTH-2)], pciw_outTransactionCount[(PCIW_ADDR_LENGTH-2):1] ^ pciw_outTransactionCount[(PCIW_ADDR_LENGTH-3):0]} ;
596
 
597
wire in_count_en  = pciw_wallow     && pciw_last_in ;
598
wire out_count_en = pciw_renable_in && pciw_last_out ;
599
 
600
always@(posedge pci_clock_in or posedge pciw_clear)
601
begin
602
    if (pciw_clear)
603
    begin
604
        inGreyCount[(PCIW_ADDR_LENGTH-2)] <= #`FF_DELAY 1'b1 ;
605
        inGreyCount[(PCIW_ADDR_LENGTH-3):0] <= #`FF_DELAY {(PCIW_ADDR_LENGTH-2),1'b0} ;
606
    end
607
    else
608
    if (in_count_en)
609
        inGreyCount <= #`FF_DELAY inNextGreyCount ;
610
end
611
 
612
always@(posedge wb_clock_in or posedge pciw_clear)
613
begin
614
    if (pciw_clear)
615
    begin
616
        outGreyCount[(PCIW_ADDR_LENGTH-2)]   <= #`FF_DELAY 1'b1 ;
617
        outGreyCount[(PCIW_ADDR_LENGTH-3):0] <= #`FF_DELAY {(PCIW_ADDR_LENGTH-2),1'b0} ;
618
    end
619
    else
620
    if (out_count_en)
621
        outGreyCount <= #`FF_DELAY outNextGreyCount ;
622
end
623
 
624
always@(posedge pci_clock_in or posedge pciw_clear)
625
begin
626
    if (pciw_clear)
627
        pciw_inTransactionCount <= #`FF_DELAY {(PCIW_ADDR_LENGTH-1){1'b0}} ;
628
    else
629
    if (in_count_en)
630
        pciw_inTransactionCount <= #`FF_DELAY pciw_inTransactionCount + 1'b1 ;
631
end
632
 
633
always@(posedge wb_clock_in or posedge pciw_clear)
634
begin
635
    if (pciw_clear)
636
        pciw_outTransactionCount <= #`FF_DELAY {(PCIW_ADDR_LENGTH-1){1'b0}} ;
637
    else
638
    if (out_count_en)
639
        pciw_outTransactionCount <= #`FF_DELAY pciw_outTransactionCount + 1'b1 ;
640
end
641
 
642
/*always@(posedge wb_clock_in or posedge pcir_clear)
643
begin
644
    if (pcir_clear)
645
        pcir_inTransactionCount <= #`FF_DELAY 1'b0 ;
646
    else
647
        if (pcir_last_in && pcir_wallow)
648
            pcir_inTransactionCount <= #`FF_DELAY ~pcir_inTransactionCount ;
649
end
650
 
651
always@(posedge pci_clock_in or posedge pcir_clear)
652
begin
653
    if (pcir_clear)
654
        pcir_outTransactionCount <= #`FF_DELAY 1'b0 ;
655
    else
656
        if (pcir_last_out)
657
            pcir_outTransactionCount <= #`FF_DELAY ~pcir_outTransactionCount ;
658
end
659
*/
660
 
661
reg pciw_transaction_ready_out ;
662
always@(posedge wb_clock_in or posedge pciw_clear)
663
begin
664
    if (pciw_clear)
665
        pciw_transaction_ready_out <= #`FF_DELAY 1'b0 ;
666
    else
667
    if ( out_count_en )
668
        pciw_transaction_ready_out <= #`FF_DELAY 1'b0 ;
669
    else
670
        pciw_transaction_ready_out <= #`FF_DELAY inGreyCount != outGreyCount ;
671
end
672
 
673
assign pcir_transaction_ready_out  = 1'b0 ;
674
 
675
endmodule
676
 

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