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[/] [pci/] [trunk/] [rtl/] [verilog/] [pci_frame_crit.v] - Blame information for rev 154

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1 77 mihad
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  File name "frame_crit.v"                                    ////
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////                                                              ////
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////  This file is part of the "PCI bridge" project               ////
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////  http://www.opencores.org/cores/pci/                         ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Miha Dolenc (mihad@opencores.org)                     ////
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////                                                              ////
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////  All additional information is avaliable in the README       ////
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////  file.                                                       ////
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////                                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org          ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.3  2002/02/01 15:25:12  mihad
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// Repaired a few bugs, updated specification, added test bench files and design document
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//
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// Revision 1.2  2001/10/05 08:14:28  mihad
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// Updated all files with inclusion of timescale file for simulation purposes.
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//
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// Revision 1.1.1.1  2001/10/02 15:33:46  mihad
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// New project directory structure
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//
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//
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// module is used to separate logic which uses criticaly constrained inputs from slower logic.
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// It is used to synthesize critical timing logic separately with faster cells or without optimization
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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// this one is used in master state machine for driving correct value of frame output
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module pci_frame_crit
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(
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    pci_frame_out,
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    force_frame_in,
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    slow_frame_in,
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    pci_stop_in
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) ;
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output  pci_frame_out ;
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input   force_frame_in,
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        slow_frame_in,
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        pci_stop_in ;
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assign  pci_frame_out   = force_frame_in && (slow_frame_in || ~pci_stop_in) ;
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endmodule

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