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[/] [pci/] [trunk/] [rtl/] [verilog/] [pci_io_mux_ad_load_crit.v] - Blame information for rev 77

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1 18 mihad
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  File name "pci_io_mux_ad_load_crit.v"                       ////
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////                                                              ////
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////  This file is part of the "PCI bridge" project               ////
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////  http://www.opencores.org/cores/pci/                         ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Miha Dolenc (mihad@opencores.org)                     ////
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////                                                              ////
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////  All additional information is avaliable in the README       ////
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////  file.                                                       ////
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////                                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org          ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
45 77 mihad
// Revision 1.1  2002/02/01 14:43:31  mihad
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// *** empty log message ***
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//
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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// module is provided for last level of logic for loading AD output flip-flops
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// and output backup flip - flops
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module pci_io_mux_ad_load_crit
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(
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    load_in,
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    load_on_transfer_in,
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    pci_irdy_in,
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    pci_trdy_in,
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    load_out
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);
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input  load_in,
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       load_on_transfer_in,
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       pci_irdy_in,
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       pci_trdy_in ;
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output load_out ;
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assign load_out = load_in || (load_on_transfer_in && ~pci_irdy_in && ~pci_trdy_in) ;
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endmodule

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