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[/] [pci/] [trunk/] [rtl/] [verilog/] [pci_spoci_ctrl.v] - Blame information for rev 154

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  File name: pci_spoci_ctrl                                   ////
////                                                              ////
////  This file is part of the "PCI bridge" project               ////
////  http://www.opencores.org/cores/pci/                         ////
////                                                              ////
////  Author(s):                                                  ////
////      - Miha Dolenc (mihad@opencores.org)                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2004 Miha Dolenc, mihad@opencores.org          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free; you can redistribute it            ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
`include "pci_constants.v"
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
module pci_spoci_ctrl
(
    reset_i             ,
    clk_i               ,
 
    do_rnd_read_i       ,
    do_seq_read_i       ,
    do_write_i          ,
 
    write_done_o        ,
    dat_rdy_o           ,
    no_ack_o            ,
 
    adr_i               ,
    dat_i               ,
    dat_o               ,
 
    pci_spoci_sda_i     ,
    pci_spoci_sda_oe_o  ,
    pci_spoci_scl_oe_o
);
 
parameter tx_rx_state_width = 9     ;
parameter tx_rx_idle        = 'h1   ;
parameter tx_rx_start       = 'h2   ;
parameter tx_rx_restart     = 'h4   ;
parameter tx_rx_send_bits   = 'h8   ;
parameter tx_rx_rec_bits    = 'h10  ;
parameter tx_rx_send_ack    = 'h20  ;
parameter tx_rx_rec_ack     = 'h40  ;
parameter tx_rx_send_nack   = 'h80  ;
parameter tx_rx_stop        = 'h100 ;
 
parameter rw_seq_state_width    = 5     ;
parameter rw_seq_idle           = 'h1   ;
parameter rw_seq_tx_ctrl        = 'h2   ;
parameter rw_seq_tx_adr         = 'h4   ;
parameter rw_seq_tx_byte        = 'h8   ;
parameter rw_seq_rx_byte        = 'h10  ;
 
`ifdef PCI33
parameter cnt_width     = 9     ;
parameter period_cnt    = 334   ;
`endif
 
`ifdef PCI66
parameter cnt_width     = 10    ;
parameter period_cnt    = 667   ;
`endif
 
input   reset_i ,
        clk_i   ;
 
input   do_rnd_read_i   ,
        do_seq_read_i   ,
        do_write_i      ;
 
output  write_done_o    ,
        dat_rdy_o       ,
        no_ack_o        ;
 
input   [10: 0] adr_i   ;
input   [ 7: 0] dat_i   ;
output  [ 7: 0] dat_o   ;
 
input   pci_spoci_sda_i     ;
 
output  pci_spoci_sda_oe_o  ,
        pci_spoci_scl_oe_o  ;
 
reg write_done_o    ,
    dat_rdy_o       ,
    no_ack_o        ;
 
reg [ 7: 0] dat_o   ;
 
reg pci_spoci_sda_oe_o  ,
    pci_spoci_scl_oe_o  ;
 
reg clk_gen_cnt_en  ;
reg clk_gen_cnt_clr ;
reg [cnt_width - 1:0] clk_gen_cnt   ;
 
reg [tx_rx_state_width - 1:0] tx_rx_state       ;
reg [tx_rx_state_width - 1:0] tx_rx_next_state  ;
reg tx_rx_sm_idle ;
 
reg scl_oe      ;
reg scl_oe_en   ;
reg sda_oe      ;
reg sda_oe_en   ;
 
reg sda_i_reg_en    ;
reg sda_i_reg       ;
 
always@(posedge clk_i or posedge reset_i)
begin
    if (reset_i)
    begin
        clk_gen_cnt <= 'h0  ;
 
        tx_rx_state <= tx_rx_idle   ;
 
    `ifdef ACTIVE_LOW_OE
        pci_spoci_sda_oe_o <= 1'b1 ;
        pci_spoci_scl_oe_o <= 1'b1 ;
    `endif
 
    `ifdef ACTIVE_HIGH_OE
        pci_spoci_sda_oe_o <= 1'b0 ;
        pci_spoci_scl_oe_o <= 1'b0 ;
    `endif
 
        sda_i_reg <= 1'b1 ;
    end
    else
    begin
        tx_rx_state <= tx_rx_next_state ;
 
        if (clk_gen_cnt_clr)
            clk_gen_cnt <= 'h0  ;
        else if (clk_gen_cnt_en)
            clk_gen_cnt <= clk_gen_cnt + 1'b1 ;
 
 
        if (sda_oe_en)
        begin
        `ifdef ACTIVE_LOW_OE
            pci_spoci_sda_oe_o <= ~sda_oe   ;
        `endif
 
        `ifdef ACTIVE_HIGH_OE
            pci_spoci_sda_oe_o <= sda_oe    ;
        `endif
        end
 
        if (scl_oe_en)
        begin
        `ifdef ACTIVE_LOW_OE
            pci_spoci_scl_oe_o <= ~scl_oe   ;
        `endif
 
        `ifdef ACTIVE_HIGH_OE
            pci_spoci_scl_oe_o <= scl_oe    ;
        `endif
        end
 
        if (sda_i_reg_en)
            sda_i_reg <= pci_spoci_sda_i ;
    end
end
 
reg [ 7: 0] tx_shift_reg ;
 
reg send_start  ;
reg start_sent  ;
 
reg send_bit    ;
reg bit_sent    ;
 
reg rec_bit     ;
reg bit_rec     ;
 
reg rec_ack     ;
reg ack_rec     ;
reg nack_rec    ;
 
reg send_ack    ;
reg ack_sent    ;
reg send_nack   ;
reg nack_sent   ;
 
reg send_stop   ;
reg stop_sent   ;
 
always@
(
    tx_rx_state     or
    clk_gen_cnt     or
    send_start      or
    send_bit        or
    tx_shift_reg    or
    send_stop       or
    rec_ack         or
    sda_i_reg       or
    rec_bit         or
    send_ack        or
    send_nack
)
begin
    clk_gen_cnt_clr     = 1'b0          ;
    clk_gen_cnt_en      = 1'b0          ;
    tx_rx_next_state    = tx_rx_state   ;
    tx_rx_sm_idle       = 1'b0          ;
    scl_oe              = 1'b0          ;
    sda_oe              = 1'b0          ;
    scl_oe_en           = 1'b0          ;
    sda_oe_en           = 1'b0          ;
    start_sent          = 1'b0          ;
    bit_sent            = 1'b0          ;
    ack_rec             = 1'b0          ;
    nack_rec            = 1'b0          ;
    sda_i_reg_en        = 1'b0          ;
    stop_sent           = 1'b0          ;
    bit_rec             = 1'b0          ;
    ack_sent            = 1'b0          ;
    nack_sent           = 1'b0          ;
 
    case (tx_rx_state)
 
    tx_rx_idle:
    begin
        tx_rx_sm_idle = 1'b1 ;
 
        // from idle state, the only transition can be to the send start bit
        if (send_start)
        begin
            tx_rx_next_state = tx_rx_start  ;
            clk_gen_cnt_clr  = 1'b1         ;
        end
    end
 
    tx_rx_start:
    begin
        clk_gen_cnt_en  = 1'b1  ;
        sda_oe          = 1'b1  ;
 
        // start bit is sent by transmiting 0 on the sda line
        if (clk_gen_cnt == (period_cnt >> 1))
        begin
            start_sent = 1'b1 ;
            sda_oe_en  = 1'b1 ;
        end
 
        // after half clock period of driving the sda low, the only possible
        // transition is to send state.
        // if send bit is not active, stop the procedure - undrive sda
        if (clk_gen_cnt == period_cnt)
        begin
            clk_gen_cnt_clr = 1'b1 ;
            if (send_bit)
            begin
                tx_rx_next_state = tx_rx_send_bits ;
            end
            else
            begin
                sda_oe              = 1'b0          ;
                sda_oe_en           = 1'b1          ;
                tx_rx_next_state    = tx_rx_idle    ;
            end
        end
    end
 
    tx_rx_send_bits:
    begin
        clk_gen_cnt_en = 1'b1 ;
 
        // generate high to low transition on the scl line immediately
        if (clk_gen_cnt == 'h0)
        begin
            scl_oe      = 1'b1  ;
            scl_oe_en   = 1'b1  ;
        end
 
        // after half of clock low time, load new value for sda oe, depending on the
        // msb bit in the shift register
        if (clk_gen_cnt == (period_cnt >> 2))
        begin
            sda_oe      = ~tx_shift_reg[7]  ;
            sda_oe_en   = 1'b1              ;
            bit_sent    = 1'b1              ;
        end
 
        // after clock low time, generate low to high transition on the scl line
        if (clk_gen_cnt == (period_cnt >> 1))
        begin
            scl_oe      = 1'b0  ;
            scl_oe_en   = 1'b1  ;
        end
 
        // after clock high time, check what to do next
        if (clk_gen_cnt == (period_cnt))
        begin
            clk_gen_cnt_clr = 1'b1 ;
 
            if (~send_bit)
            begin
                // after transmiting all the bits, the only possible transition is to the state
                // that checks the eprom acknowledge
                if (rec_ack)
                    tx_rx_next_state = tx_rx_rec_ack ;
                else
                begin
                    sda_oe              = 1'b0          ;
                    sda_oe_en           = 1'b1          ;
                    tx_rx_next_state    = tx_rx_idle    ;
                end
            end
        end
    end
 
    tx_rx_rec_bits:
    begin
        clk_gen_cnt_en = 1'b1 ;
        sda_i_reg_en   = 1'b1 ;
 
        // generate high to low transition on the scl line immediately
        if (clk_gen_cnt == 'h0)
        begin
            scl_oe      = 1'b1  ;
            scl_oe_en   = 1'b1  ;
        end
 
        // after half of clock low time, disable sda driver
        if (clk_gen_cnt == (period_cnt >> 2))
        begin
            sda_oe      = 1'b0  ;
            sda_oe_en   = 1'b1  ;
        end
 
        // after clock low time, generate low to high transition on the scl line
        if (clk_gen_cnt == (period_cnt >> 1))
        begin
            scl_oe      = 1'b0  ;
            scl_oe_en   = 1'b1  ;
        end
 
        // after half of clock high time, report received bit
        if (clk_gen_cnt == ((period_cnt >> 1) + (period_cnt >> 2)) )
        begin
            bit_rec = 1'b1  ;
        end
 
        // after clock period is finished, check the next operation
        if (clk_gen_cnt == (period_cnt))
        begin
            clk_gen_cnt_clr = 1'b1 ;
 
            if (~rec_bit)
            begin
                // when all bits are received, only nack or ack next states are possible
                if (send_ack)
                    tx_rx_next_state = tx_rx_send_ack   ;
                else if (send_nack)
                    tx_rx_next_state = tx_rx_send_nack  ;
                else
                begin
                    tx_rx_next_state = tx_rx_idle    ;
                end
            end
        end
    end
 
    tx_rx_send_ack:
    begin
        clk_gen_cnt_en  = 1'b1  ;
 
        // generate high to low transition on the scl line
        if (clk_gen_cnt == 'h0)
        begin
            scl_oe      = 1'b1  ;
            scl_oe_en   = 1'b1  ;
        end
 
        // after half of clock low time, enable the sda driver
        if (clk_gen_cnt == (period_cnt >> 2))
        begin
            sda_oe      = 1'b1  ;
            sda_oe_en   = 1'b1  ;
            ack_sent    = 1'b1  ;
        end
 
        // after clock low time, disable the scl driver - generate low to high transition on the scl line
        if (clk_gen_cnt == (period_cnt >> 1))
        begin
            scl_oe      = 1'b0  ;
            scl_oe_en   = 1'b1  ;
        end
 
        // after clock period time expires, check what to do next
        if (clk_gen_cnt == period_cnt)
        begin
            clk_gen_cnt_clr = 1'b1 ;
 
            // after the byte is acknowledged, the only possible next state is receive bits
            // state
            if (rec_bit)
                tx_rx_next_state = tx_rx_rec_bits   ;
            else
            begin
                // this should never happen
                sda_oe      = 1'b0  ;
                sda_oe_en   = 1'b1  ;
 
                tx_rx_next_state = tx_rx_idle ;
            end
        end
    end
 
    tx_rx_rec_ack:
    begin
 
        clk_gen_cnt_en  = 1'b1  ;
        sda_i_reg_en    = 1'b1  ;
 
        // generate high to low transition on the scl line
        if (clk_gen_cnt == 'h0)
        begin
            scl_oe      = 1'b1  ;
            scl_oe_en   = 1'b1  ;
        end
 
        // after half of clock low time, disable the sda driver
        if (clk_gen_cnt == (period_cnt >> 2))
        begin
            sda_oe      = 1'b0  ;
            sda_oe_en   = 1'b1  ;
        end
 
        // after clock low time, disable the scl driver - generate low to high transition on the scl line
        if (clk_gen_cnt == (period_cnt >> 1))
        begin
            scl_oe      = 1'b0  ;
            scl_oe_en   = 1'b1  ;
        end
 
        // after 1/2 clock high time, report ack or nack condition, depending on the sda input state
        if (clk_gen_cnt == ((period_cnt >> 1) + (period_cnt >> 2)) )
        begin
            ack_rec     = ~sda_i_reg ;
            nack_rec    =  sda_i_reg ;
        end
 
        // after clock period time expires, check what to do next
        if (clk_gen_cnt == period_cnt)
        begin
            clk_gen_cnt_clr = 1'b1 ;
 
            if (send_bit)
                tx_rx_next_state = tx_rx_send_bits  ;
            else if (rec_bit)
                tx_rx_next_state = tx_rx_rec_bits   ;
            else if (send_stop)
                tx_rx_next_state = tx_rx_stop       ;
            else if (send_start)
                tx_rx_next_state = tx_rx_restart    ;
            else
            begin
                // this should never happen
                tx_rx_next_state = tx_rx_idle ;
            end
        end
    end
 
    tx_rx_send_nack:
    begin
        clk_gen_cnt_en  = 1'b1  ;
 
        // generate high to low transition on the scl line
        if (clk_gen_cnt == 'h0)
        begin
            scl_oe      = 1'b1  ;
            scl_oe_en   = 1'b1  ;
        end
 
        // after half of clock low time, disable the sda driver
        if (clk_gen_cnt == (period_cnt >> 2))
        begin
            sda_oe      = 1'b0  ;
            sda_oe_en   = 1'b1  ;
            nack_sent   = 1'b1  ;
        end
 
        // after clock low time, disable the scl driver - generate low to high transition on the scl line
        if (clk_gen_cnt == (period_cnt >> 1))
        begin
            scl_oe      = 1'b0  ;
            scl_oe_en   = 1'b1  ;
        end
 
        // after clock period time expires, check what to do next
        if (clk_gen_cnt == period_cnt)
        begin
            clk_gen_cnt_clr = 1'b1 ;
 
            // after the no acknowledge is sent, the only possible next state is stop
            // state
            if (send_stop)
                tx_rx_next_state = tx_rx_stop   ;
            else
            begin
                // this should never happen
                tx_rx_next_state = tx_rx_idle ;
            end
        end
    end
 
    tx_rx_restart:
    begin
        clk_gen_cnt_en = 1'b1 ;
 
        // generate high to low transition
        if (clk_gen_cnt == 'h0)
        begin
            scl_oe      = 1'b1  ;
            scl_oe_en   = 1'b1  ;
        end
 
        // after half of clock low time, release sda line
        if (clk_gen_cnt == (period_cnt >> 2))
        begin
            sda_oe      = 1'b0  ;
            sda_oe_en   = 1'b1  ;
        end
 
        // generate low to high transition
        if (clk_gen_cnt == (period_cnt >> 1))
        begin
            clk_gen_cnt_clr = 1'b1 ;
 
            scl_oe      = 1'b0  ;
            scl_oe_en   = 1'b1  ;
 
            if (send_start)
                tx_rx_next_state = tx_rx_start ;
            else
                tx_rx_next_state = tx_rx_idle ;
        end
    end
 
    tx_rx_stop:
    begin
        clk_gen_cnt_en = 1'b1 ;
 
        // generate high to low transition
        if (clk_gen_cnt == 'h0)
        begin
            scl_oe      = 1'b1  ;
            scl_oe_en   = 1'b1  ;
        end
 
        // after half of clock low time, drive sda line low
        if (clk_gen_cnt == (period_cnt >> 2))
        begin
            sda_oe      = 1'b1  ;
            sda_oe_en   = 1'b1  ;
        end
 
        // generate low to high transition
        if (clk_gen_cnt == (period_cnt >> 1))
        begin
            scl_oe      = 1'b0  ;
            scl_oe_en   = 1'b1  ;
        end
 
        // after full clock period, release the sda line
        if (clk_gen_cnt == period_cnt)
        begin
            sda_oe      = 1'b0  ;
            sda_oe_en   = 1'b1  ;
            stop_sent   = 1'b1  ;
 
            tx_rx_next_state = tx_rx_idle ;
        end
    end
 
    endcase
end
 
reg [rw_seq_state_width - 1:0]  rw_seq_state    ;
 
reg doing_read      ,
    doing_write     ,
    doing_seq_read  ,
    adr_set         ;
 
reg [ 3: 0] bits_transfered ;
 
always@(posedge clk_i or posedge reset_i)
begin
    if (reset_i)
    begin
        rw_seq_state    <= rw_seq_idle  ;
        adr_set         <= 1'b0         ;
        doing_read      <= 1'b0         ;
        doing_write     <= 1'b0         ;
        doing_seq_read  <= 1'b0         ;
        dat_o           <= 'h0          ;
        tx_shift_reg    <= 'h0          ;
        send_start      <= 'h0          ;
        send_stop       <= 'h0          ;
        send_bit        <= 'h0          ;
        send_nack       <= 'h0          ;
        rec_ack         <= 'h0          ;
        no_ack_o        <= 'h0          ;
        bits_transfered <= 'h0          ;
        write_done_o    <= 'h0          ;
        dat_rdy_o       <= 'h0          ;
        send_ack        <= 'h0          ;
        rec_bit         <= 'h0          ;
    end
    else
    begin
 
        case (rw_seq_state)
 
        rw_seq_idle:
        begin
            tx_shift_reg <= {4'b1010, adr_i[10: 8], 1'b0} ;
            adr_set      <= 1'b0                          ;
 
            if ( tx_rx_sm_idle & ~(doing_write | doing_read | doing_seq_read) )
            begin
                if (do_write_i | do_rnd_read_i | do_seq_read_i)
                begin
                    rw_seq_state <= rw_seq_tx_ctrl  ;
                    send_start   <= 1'b1            ;
                end
 
                if (do_write_i)
                    doing_write     <= 1'b1 ;
                else if (do_rnd_read_i)
                    doing_read      <= 1'b1 ;
                else if (do_seq_read_i)
                    doing_seq_read  <= 1'b1 ;
            end
            else
            begin
                doing_write     <= 1'b0 ;
                doing_read      <= 1'b0 ;
                doing_seq_read  <= 1'b0 ;
            end
        end
 
        rw_seq_tx_ctrl:
        begin
            if (send_start)
            begin
                bits_transfered <= 'h0 ;
 
                if (start_sent)
                begin
                    send_start <= 1'b0 ;
                    send_bit   <= 1'b1 ;
                end
            end
            else if (send_bit)
            begin
                if (bit_sent)
                begin
                    bits_transfered <= bits_transfered + 1'b1 ;
                    tx_shift_reg <= {tx_shift_reg[6:0], tx_shift_reg[0]} ;
                end
 
                if (bits_transfered == 'h8)
                begin
                    send_bit <= 1'b0 ;
                    rec_ack  <= 1'b1 ;
                end
            end
            else if (rec_ack)
            begin
                bits_transfered <= 'h0 ;
 
                if (ack_rec | nack_rec)
                    rec_ack <= 1'b0 ;
 
                if (ack_rec)
                begin
                    if (doing_write | ~adr_set)
                    begin
                        rw_seq_state    <= rw_seq_tx_adr    ;
                        tx_shift_reg    <= adr_i[ 7: 0]     ;
                        send_bit        <= 1'b1             ;
                    end
                    else
                    begin
                        rw_seq_state    <= rw_seq_rx_byte   ;
                        rec_bit         <= 1'b1             ;
                    end
                end
                else if (nack_rec)
                begin
                    no_ack_o    <= 1'b1 ;
                    send_stop   <= 1'b1 ;
                end
            end
            else if (send_stop)
            begin
                no_ack_o <= 1'b0 ;
 
                if (stop_sent)
                begin
                    send_stop       <= 1'b0         ;
                    rw_seq_state    <= rw_seq_idle  ;
                end
            end
        end
 
        rw_seq_tx_adr:
        begin
            if (send_bit)
            begin
                if (bit_sent)
                begin
                    bits_transfered <= bits_transfered + 1'b1 ;
                    tx_shift_reg <= {tx_shift_reg[6:0], tx_shift_reg[0]} ;
                end
 
                if (bits_transfered == 'h8)
                begin
                    send_bit <= 1'b0 ;
                    rec_ack  <= 1'b1 ;
                end
            end
            else if (rec_ack)
            begin
                bits_transfered <= 'h0 ;
 
                if (ack_rec | nack_rec)
                    rec_ack <= 1'b0 ;
 
                if (ack_rec)
                begin
 
                    adr_set <= 1'b1 ;
 
                    if (doing_write)
                    begin
                        send_bit        <= 1'b1             ;
                        rw_seq_state    <= rw_seq_tx_byte   ;
                        tx_shift_reg    <= dat_i            ;
                    end
                    else if (doing_read | doing_seq_read)
                    begin
                        send_start      <= 1'b1             ;
                        rw_seq_state    <= rw_seq_tx_ctrl   ;
                        tx_shift_reg    <= 8'b10100001      ;
                    end
                end
                else if (nack_rec)
                begin
                    no_ack_o    <= 1'b1 ;
                    send_stop   <= 1'b1 ;
                end
            end
            else if (send_stop)
            begin
                no_ack_o    <= 1'b0 ;
 
                if (stop_sent)
                begin
                    send_stop       <= 1'b0         ;
                    rw_seq_state    <= rw_seq_idle  ;
                end
            end
        end
 
        rw_seq_tx_byte:
        begin
            if (send_bit)
            begin
                if (bit_sent)
                begin
                    bits_transfered <= bits_transfered + 1'b1 ;
                    tx_shift_reg <= {tx_shift_reg[6:0], tx_shift_reg[0]} ;
                end
 
                if (bits_transfered == 'h8)
                begin
                    send_bit <= 1'b0 ;
                    rec_ack  <= 1'b1 ;
                end
            end
            else if (rec_ack)
            begin
                bits_transfered <= 'h0 ;
 
                if (ack_rec | nack_rec)
                begin
                    rec_ack   <= 1'b0   ;
                    send_stop <= 1'b1   ;
                end
 
                if (nack_rec)
                    no_ack_o <= 1'b1 ;
 
                if (ack_rec)
                    write_done_o <= 1'b1 ;
            end
            else if (send_stop)
            begin
                no_ack_o        <= 1'b0 ;
                write_done_o    <= 1'b0 ;
 
                if (stop_sent)
                begin
                    send_stop       <= 1'b0         ;
                    rw_seq_state    <= rw_seq_idle  ;
                end
            end
        end
 
        rw_seq_rx_byte:
        begin
            if (rec_bit)
            begin
                if (bit_rec)
                begin
                    bits_transfered <= bits_transfered + 1'b1   ;
                    dat_o           <= {dat_o[6:0], sda_i_reg}  ;
                end
 
                if (bits_transfered == 'h8)
                begin
                    rec_bit   <= 1'b0 ;
                    dat_rdy_o <= 1'b1 ;
                    if (doing_read)
                        send_nack <= 1'b1 ;
                    else
                        send_ack  <= 1'b1 ;
                end
            end
            else if (send_nack)
            begin
                dat_rdy_o       <= 1'b0 ;
                bits_transfered <= 'h0  ;
 
                if (nack_sent)
                begin
                    send_stop <= 1'b1 ;
                    send_nack <= 1'b0 ;
                end
            end
            else if (send_ack)
            begin
                dat_rdy_o       <= 1'b0 ;
                bits_transfered <= 'h0  ;
 
                if (~do_seq_read_i)
                begin
                    send_ack    <= 1'b0 ;
                    send_nack   <= 1'b1 ;
                end
                else if (ack_sent)
                begin
                    send_ack <= 1'b0 ;
                    rec_bit  <= 1'b1 ;
                end
            end
            else if (send_stop)
            begin
                if (stop_sent)
                begin
                    send_stop       <= 1'b0         ;
                    rw_seq_state    <= rw_seq_idle  ;
                end
            end
        end
        endcase
    end
end
 
endmodule // pci_spoci_ctrl

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[/] [pci/] [trunk/] [rtl/] [verilog/] [pci_spoci_ctrl.v] - Blame information for rev 154

Line No.	Rev	Author	Line
1	140	mihad	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// File name: pci_spoci_ctrl ////`
4			`//// ////`
5			`//// This file is part of the "PCI bridge" project ////`
6			`//// http://www.opencores.org/cores/pci/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Miha Dolenc (mihad@opencores.org) ////`
10			`//// ////`
11			`//// ////`
12			`//////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2004 Miha Dolenc, mihad@opencores.org ////`
15			`//// ////`
16			`//// This source file may be used and distributed without ////`
17			`//// restriction provided that this copyright statement is not ////`
18			`//// removed from the file and that any derivative work contains ////`
19			`//// the original copyright notice and the associated disclaimer. ////`
20			`//// ////`
21			`//// This source file is free; you can redistribute it ////`
22			`//// and/or modify it under the terms of the GNU Lesser General ////`
23			`//// Public License as published by the Free Software Foundation; ////`
24			`//// either version 2.1 of the License, or (at your option) any ////`
25			`//// later version. ////`
26			`//// ////`
27			`//// This source is distributed in the hope that it will be ////`
28			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
29			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
30			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
31			`//// details. ////`
32			`//// ////`
33			`//// You should have received a copy of the GNU Lesser General ////`
34			`//// Public License along with this source; if not, download it ////`
35			`//// from http://www.opencores.org/lgpl.shtml ////`
36			`//// ////`
37			`//////////////////////////////////////////////////////////////////////`
38			`//`
39			`// CVS Revision History`
40			`//`
41			`// $Log: not supported by cvs2svn $`
42			`//`
43
44			`include "pci_constants.v"
45
46			`// synopsys translate_off`
47			`include "timescale.v"
48			`// synopsys translate_on`
49
50			`module pci_spoci_ctrl`
51			`(`
52			`reset_i ,`
53			`clk_i ,`
54
55			`do_rnd_read_i ,`
56			`do_seq_read_i ,`
57			`do_write_i ,`
58
59			`write_done_o ,`
60			`dat_rdy_o ,`
61			`no_ack_o ,`
62
63			`adr_i ,`
64			`dat_i ,`
65			`dat_o ,`
66
67			`pci_spoci_sda_i ,`
68			`pci_spoci_sda_oe_o ,`
69			`pci_spoci_scl_oe_o`
70			`);`
71
72			`parameter tx_rx_state_width = 9 ;`
73			`parameter tx_rx_idle = 'h1 ;`
74			`parameter tx_rx_start = 'h2 ;`
75			`parameter tx_rx_restart = 'h4 ;`
76			`parameter tx_rx_send_bits = 'h8 ;`
77			`parameter tx_rx_rec_bits = 'h10 ;`
78			`parameter tx_rx_send_ack = 'h20 ;`
79			`parameter tx_rx_rec_ack = 'h40 ;`
80			`parameter tx_rx_send_nack = 'h80 ;`
81			`parameter tx_rx_stop = 'h100 ;`
82
83			`parameter rw_seq_state_width = 5 ;`
84			`parameter rw_seq_idle = 'h1 ;`
85			`parameter rw_seq_tx_ctrl = 'h2 ;`
86			`parameter rw_seq_tx_adr = 'h4 ;`
87			`parameter rw_seq_tx_byte = 'h8 ;`
88			`parameter rw_seq_rx_byte = 'h10 ;`
89
90			`ifdef PCI33
91			`parameter cnt_width = 9 ;`
92			`parameter period_cnt = 334 ;`
93			`endif
94
95			`ifdef PCI66
96			`parameter cnt_width = 10 ;`
97			`parameter period_cnt = 667 ;`
98			`endif
99
100			`input reset_i ,`
101			`clk_i ;`
102
103			`input do_rnd_read_i ,`
104			`do_seq_read_i ,`
105			`do_write_i ;`
106
107			`output write_done_o ,`
108			`dat_rdy_o ,`
109			`no_ack_o ;`
110
111			`input [10: 0] adr_i ;`
112			`input [ 7: 0] dat_i ;`
113			`output [ 7: 0] dat_o ;`
114
115			`input pci_spoci_sda_i ;`
116
117			`output pci_spoci_sda_oe_o ,`
118			`pci_spoci_scl_oe_o ;`
119
120			`reg write_done_o ,`
121			`dat_rdy_o ,`
122			`no_ack_o ;`
123
124			`reg [ 7: 0] dat_o ;`
125
126			`reg pci_spoci_sda_oe_o ,`
127			`pci_spoci_scl_oe_o ;`
128
129			`reg clk_gen_cnt_en ;`
130			`reg clk_gen_cnt_clr ;`
131			`reg [cnt_width - 1:0] clk_gen_cnt ;`
132
133			`reg [tx_rx_state_width - 1:0] tx_rx_state ;`
134			`reg [tx_rx_state_width - 1:0] tx_rx_next_state ;`
135			`reg tx_rx_sm_idle ;`
136
137			`reg scl_oe ;`
138			`reg scl_oe_en ;`
139			`reg sda_oe ;`
140			`reg sda_oe_en ;`
141
142			`reg sda_i_reg_en ;`
143			`reg sda_i_reg ;`
144
145			`always@(posedge clk_i or posedge reset_i)`
146			`begin`
147			`if (reset_i)`
148			`begin`
149			`clk_gen_cnt <= 'h0 ;`
150
151			`tx_rx_state <= tx_rx_idle ;`
152
153			`ifdef ACTIVE_LOW_OE
154			`pci_spoci_sda_oe_o <= 1'b1 ;`
155			`pci_spoci_scl_oe_o <= 1'b1 ;`
156			`endif
157
158			`ifdef ACTIVE_HIGH_OE
159			`pci_spoci_sda_oe_o <= 1'b0 ;`
160			`pci_spoci_scl_oe_o <= 1'b0 ;`
161			`endif
162
163			`sda_i_reg <= 1'b1 ;`
164			`end`
165			`else`
166			`begin`
167			`tx_rx_state <= tx_rx_next_state ;`
168
169			`if (clk_gen_cnt_clr)`
170			`clk_gen_cnt <= 'h0 ;`
171			`else if (clk_gen_cnt_en)`
172			`clk_gen_cnt <= clk_gen_cnt + 1'b1 ;`
173
174
175			`if (sda_oe_en)`
176			`begin`
177			`ifdef ACTIVE_LOW_OE
178			`pci_spoci_sda_oe_o <= ~sda_oe ;`
179			`endif
180
181			`ifdef ACTIVE_HIGH_OE
182			`pci_spoci_sda_oe_o <= sda_oe ;`
183			`endif
184			`end`
185
186			`if (scl_oe_en)`
187			`begin`
188			`ifdef ACTIVE_LOW_OE
189			`pci_spoci_scl_oe_o <= ~scl_oe ;`
190			`endif
191
192			`ifdef ACTIVE_HIGH_OE
193			`pci_spoci_scl_oe_o <= scl_oe ;`
194			`endif
195			`end`
196
197			`if (sda_i_reg_en)`
198			`sda_i_reg <= pci_spoci_sda_i ;`
199			`end`
200			`end`
201
202			`reg [ 7: 0] tx_shift_reg ;`
203
204			`reg send_start ;`
205			`reg start_sent ;`
206
207			`reg send_bit ;`
208			`reg bit_sent ;`
209
210			`reg rec_bit ;`
211			`reg bit_rec ;`
212
213			`reg rec_ack ;`
214			`reg ack_rec ;`
215			`reg nack_rec ;`
216
217			`reg send_ack ;`
218			`reg ack_sent ;`
219			`reg send_nack ;`
220			`reg nack_sent ;`
221
222			`reg send_stop ;`
223			`reg stop_sent ;`
224
225			`always@`
226			`(`
227			`tx_rx_state or`
228			`clk_gen_cnt or`
229			`send_start or`
230			`send_bit or`
231			`tx_shift_reg or`
232			`send_stop or`
233			`rec_ack or`
234			`sda_i_reg or`
235			`rec_bit or`
236			`send_ack or`
237			`send_nack`
238			`)`
239			`begin`
240			`clk_gen_cnt_clr = 1'b0 ;`
241			`clk_gen_cnt_en = 1'b0 ;`
242			`tx_rx_next_state = tx_rx_state ;`
243			`tx_rx_sm_idle = 1'b0 ;`
244			`scl_oe = 1'b0 ;`
245			`sda_oe = 1'b0 ;`
246			`scl_oe_en = 1'b0 ;`
247			`sda_oe_en = 1'b0 ;`
248			`start_sent = 1'b0 ;`
249			`bit_sent = 1'b0 ;`
250			`ack_rec = 1'b0 ;`
251			`nack_rec = 1'b0 ;`
252			`sda_i_reg_en = 1'b0 ;`
253			`stop_sent = 1'b0 ;`
254			`bit_rec = 1'b0 ;`
255			`ack_sent = 1'b0 ;`
256			`nack_sent = 1'b0 ;`
257
258			`case (tx_rx_state)`
259
260			`tx_rx_idle:`
261			`begin`
262			`tx_rx_sm_idle = 1'b1 ;`
263
264			`// from idle state, the only transition can be to the send start bit`
265			`if (send_start)`
266			`begin`
267			`tx_rx_next_state = tx_rx_start ;`
268			`clk_gen_cnt_clr = 1'b1 ;`
269			`end`
270			`end`
271
272			`tx_rx_start:`
273			`begin`
274			`clk_gen_cnt_en = 1'b1 ;`
275			`sda_oe = 1'b1 ;`
276
277			`// start bit is sent by transmiting 0 on the sda line`
278			`if (clk_gen_cnt == (period_cnt >> 1))`
279			`begin`
280			`start_sent = 1'b1 ;`
281			`sda_oe_en = 1'b1 ;`
282			`end`
283
284			`// after half clock period of driving the sda low, the only possible`
285			`// transition is to send state.`
286			`// if send bit is not active, stop the procedure - undrive sda`
287			`if (clk_gen_cnt == period_cnt)`
288			`begin`
289			`clk_gen_cnt_clr = 1'b1 ;`
290			`if (send_bit)`
291			`begin`
292			`tx_rx_next_state = tx_rx_send_bits ;`
293			`end`
294			`else`
295			`begin`
296			`sda_oe = 1'b0 ;`
297			`sda_oe_en = 1'b1 ;`
298			`tx_rx_next_state = tx_rx_idle ;`
299			`end`
300			`end`
301			`end`
302
303			`tx_rx_send_bits:`
304			`begin`
305			`clk_gen_cnt_en = 1'b1 ;`
306
307			`// generate high to low transition on the scl line immediately`
308			`if (clk_gen_cnt == 'h0)`
309			`begin`
310			`scl_oe = 1'b1 ;`
311			`scl_oe_en = 1'b1 ;`
312			`end`
313
314			`// after half of clock low time, load new value for sda oe, depending on the`
315			`// msb bit in the shift register`
316			`if (clk_gen_cnt == (period_cnt >> 2))`
317			`begin`
318			`sda_oe = ~tx_shift_reg[7] ;`
319			`sda_oe_en = 1'b1 ;`
320			`bit_sent = 1'b1 ;`
321			`end`
322
323			`// after clock low time, generate low to high transition on the scl line`
324			`if (clk_gen_cnt == (period_cnt >> 1))`
325			`begin`
326			`scl_oe = 1'b0 ;`
327			`scl_oe_en = 1'b1 ;`
328			`end`
329
330			`// after clock high time, check what to do next`
331			`if (clk_gen_cnt == (period_cnt))`
332			`begin`
333			`clk_gen_cnt_clr = 1'b1 ;`
334
335			`if (~send_bit)`
336			`begin`
337			`// after transmiting all the bits, the only possible transition is to the state`
338			`// that checks the eprom acknowledge`
339			`if (rec_ack)`
340			`tx_rx_next_state = tx_rx_rec_ack ;`
341			`else`
342			`begin`
343			`sda_oe = 1'b0 ;`
344			`sda_oe_en = 1'b1 ;`
345			`tx_rx_next_state = tx_rx_idle ;`
346			`end`
347			`end`
348			`end`
349			`end`
350
351			`tx_rx_rec_bits:`
352			`begin`
353			`clk_gen_cnt_en = 1'b1 ;`
354			`sda_i_reg_en = 1'b1 ;`
355
356			`// generate high to low transition on the scl line immediately`
357			`if (clk_gen_cnt == 'h0)`
358			`begin`
359			`scl_oe = 1'b1 ;`
360			`scl_oe_en = 1'b1 ;`
361			`end`
362
363			`// after half of clock low time, disable sda driver`
364			`if (clk_gen_cnt == (period_cnt >> 2))`
365			`begin`
366			`sda_oe = 1'b0 ;`
367			`sda_oe_en = 1'b1 ;`
368			`end`
369
370			`// after clock low time, generate low to high transition on the scl line`
371			`if (clk_gen_cnt == (period_cnt >> 1))`
372			`begin`
373			`scl_oe = 1'b0 ;`
374			`scl_oe_en = 1'b1 ;`
375			`end`
376
377			`// after half of clock high time, report received bit`
378			`if (clk_gen_cnt == ((period_cnt >> 1) + (period_cnt >> 2)) )`
379			`begin`
380			`bit_rec = 1'b1 ;`
381			`end`
382
383			`// after clock period is finished, check the next operation`
384			`if (clk_gen_cnt == (period_cnt))`
385			`begin`
386			`clk_gen_cnt_clr = 1'b1 ;`
387
388			`if (~rec_bit)`
389			`begin`
390			`// when all bits are received, only nack or ack next states are possible`
391			`if (send_ack)`
392			`tx_rx_next_state = tx_rx_send_ack ;`
393			`else if (send_nack)`
394			`tx_rx_next_state = tx_rx_send_nack ;`
395			`else`
396			`begin`
397			`tx_rx_next_state = tx_rx_idle ;`
398			`end`
399			`end`
400			`end`
401			`end`
402
403			`tx_rx_send_ack:`
404			`begin`
405			`clk_gen_cnt_en = 1'b1 ;`
406
407			`// generate high to low transition on the scl line`
408			`if (clk_gen_cnt == 'h0)`
409			`begin`
410			`scl_oe = 1'b1 ;`
411			`scl_oe_en = 1'b1 ;`
412			`end`
413
414			`// after half of clock low time, enable the sda driver`
415			`if (clk_gen_cnt == (period_cnt >> 2))`
416			`begin`
417			`sda_oe = 1'b1 ;`
418			`sda_oe_en = 1'b1 ;`
419			`ack_sent = 1'b1 ;`
420			`end`
421
422			`// after clock low time, disable the scl driver - generate low to high transition on the scl line`
423			`if (clk_gen_cnt == (period_cnt >> 1))`
424			`begin`
425			`scl_oe = 1'b0 ;`
426			`scl_oe_en = 1'b1 ;`
427			`end`
428
429			`// after clock period time expires, check what to do next`
430			`if (clk_gen_cnt == period_cnt)`
431			`begin`
432			`clk_gen_cnt_clr = 1'b1 ;`
433
434			`// after the byte is acknowledged, the only possible next state is receive bits`
435			`// state`
436			`if (rec_bit)`
437			`tx_rx_next_state = tx_rx_rec_bits ;`
438			`else`
439			`begin`
440			`// this should never happen`
441			`sda_oe = 1'b0 ;`
442			`sda_oe_en = 1'b1 ;`
443
444			`tx_rx_next_state = tx_rx_idle ;`
445			`end`
446			`end`
447			`end`
448
449			`tx_rx_rec_ack:`
450			`begin`
451
452			`clk_gen_cnt_en = 1'b1 ;`
453			`sda_i_reg_en = 1'b1 ;`
454
455			`// generate high to low transition on the scl line`
456			`if (clk_gen_cnt == 'h0)`
457			`begin`
458			`scl_oe = 1'b1 ;`
459			`scl_oe_en = 1'b1 ;`
460			`end`
461
462			`// after half of clock low time, disable the sda driver`
463			`if (clk_gen_cnt == (period_cnt >> 2))`
464			`begin`
465			`sda_oe = 1'b0 ;`
466			`sda_oe_en = 1'b1 ;`
467			`end`
468
469			`// after clock low time, disable the scl driver - generate low to high transition on the scl line`
470			`if (clk_gen_cnt == (period_cnt >> 1))`
471			`begin`
472			`scl_oe = 1'b0 ;`
473			`scl_oe_en = 1'b1 ;`
474			`end`
475
476			`// after 1/2 clock high time, report ack or nack condition, depending on the sda input state`
477			`if (clk_gen_cnt == ((period_cnt >> 1) + (period_cnt >> 2)) )`
478			`begin`
479			`ack_rec = ~sda_i_reg ;`
480			`nack_rec = sda_i_reg ;`
481			`end`
482
483			`// after clock period time expires, check what to do next`
484			`if (clk_gen_cnt == period_cnt)`
485			`begin`
486			`clk_gen_cnt_clr = 1'b1 ;`
487
488			`if (send_bit)`
489			`tx_rx_next_state = tx_rx_send_bits ;`
490			`else if (rec_bit)`
491			`tx_rx_next_state = tx_rx_rec_bits ;`
492			`else if (send_stop)`
493			`tx_rx_next_state = tx_rx_stop ;`
494			`else if (send_start)`
495			`tx_rx_next_state = tx_rx_restart ;`
496			`else`
497			`begin`
498			`// this should never happen`
499			`tx_rx_next_state = tx_rx_idle ;`
500			`end`
501			`end`
502			`end`
503
504			`tx_rx_send_nack:`
505			`begin`
506			`clk_gen_cnt_en = 1'b1 ;`
507
508			`// generate high to low transition on the scl line`
509			`if (clk_gen_cnt == 'h0)`
510			`begin`
511			`scl_oe = 1'b1 ;`
512			`scl_oe_en = 1'b1 ;`
513			`end`
514
515			`// after half of clock low time, disable the sda driver`
516			`if (clk_gen_cnt == (period_cnt >> 2))`
517			`begin`
518			`sda_oe = 1'b0 ;`
519			`sda_oe_en = 1'b1 ;`
520			`nack_sent = 1'b1 ;`
521			`end`
522
523			`// after clock low time, disable the scl driver - generate low to high transition on the scl line`
524			`if (clk_gen_cnt == (period_cnt >> 1))`
525			`begin`
526			`scl_oe = 1'b0 ;`
527			`scl_oe_en = 1'b1 ;`
528			`end`
529
530			`// after clock period time expires, check what to do next`
531			`if (clk_gen_cnt == period_cnt)`
532			`begin`
533			`clk_gen_cnt_clr = 1'b1 ;`
534
535			`// after the no acknowledge is sent, the only possible next state is stop`
536			`// state`
537			`if (send_stop)`
538			`tx_rx_next_state = tx_rx_stop ;`
539			`else`
540			`begin`
541			`// this should never happen`
542			`tx_rx_next_state = tx_rx_idle ;`
543			`end`
544			`end`
545			`end`
546
547			`tx_rx_restart:`
548			`begin`
549			`clk_gen_cnt_en = 1'b1 ;`
550
551			`// generate high to low transition`
552			`if (clk_gen_cnt == 'h0)`
553			`begin`
554			`scl_oe = 1'b1 ;`
555			`scl_oe_en = 1'b1 ;`
556			`end`
557
558			`// after half of clock low time, release sda line`
559			`if (clk_gen_cnt == (period_cnt >> 2))`
560			`begin`
561			`sda_oe = 1'b0 ;`
562			`sda_oe_en = 1'b1 ;`
563			`end`
564
565			`// generate low to high transition`
566			`if (clk_gen_cnt == (period_cnt >> 1))`
567			`begin`
568			`clk_gen_cnt_clr = 1'b1 ;`
569
570			`scl_oe = 1'b0 ;`
571			`scl_oe_en = 1'b1 ;`
572
573			`if (send_start)`
574			`tx_rx_next_state = tx_rx_start ;`
575			`else`
576			`tx_rx_next_state = tx_rx_idle ;`
577			`end`
578			`end`
579
580			`tx_rx_stop:`
581			`begin`
582			`clk_gen_cnt_en = 1'b1 ;`
583
584			`// generate high to low transition`
585			`if (clk_gen_cnt == 'h0)`
586			`begin`
587			`scl_oe = 1'b1 ;`
588			`scl_oe_en = 1'b1 ;`
589			`end`
590
591			`// after half of clock low time, drive sda line low`
592			`if (clk_gen_cnt == (period_cnt >> 2))`
593			`begin`
594			`sda_oe = 1'b1 ;`
595			`sda_oe_en = 1'b1 ;`
596			`end`
597
598			`// generate low to high transition`
599			`if (clk_gen_cnt == (period_cnt >> 1))`
600			`begin`
601			`scl_oe = 1'b0 ;`
602			`scl_oe_en = 1'b1 ;`
603			`end`
604
605			`// after full clock period, release the sda line`
606			`if (clk_gen_cnt == period_cnt)`
607			`begin`
608			`sda_oe = 1'b0 ;`
609			`sda_oe_en = 1'b1 ;`
610			`stop_sent = 1'b1 ;`
611
612			`tx_rx_next_state = tx_rx_idle ;`
613			`end`
614			`end`
615
616			`endcase`
617			`end`
618
619			`reg [rw_seq_state_width - 1:0] rw_seq_state ;`
620
621			`reg doing_read ,`
622			`doing_write ,`
623			`doing_seq_read ,`
624			`adr_set ;`
625
626			`reg [ 3: 0] bits_transfered ;`
627
628			`always@(posedge clk_i or posedge reset_i)`
629			`begin`
630			`if (reset_i)`
631			`begin`
632			`rw_seq_state <= rw_seq_idle ;`
633			`adr_set <= 1'b0 ;`
634			`doing_read <= 1'b0 ;`
635			`doing_write <= 1'b0 ;`
636			`doing_seq_read <= 1'b0 ;`
637			`dat_o <= 'h0 ;`
638			`tx_shift_reg <= 'h0 ;`
639			`send_start <= 'h0 ;`
640			`send_stop <= 'h0 ;`
641			`send_bit <= 'h0 ;`
642			`send_nack <= 'h0 ;`
643			`rec_ack <= 'h0 ;`
644			`no_ack_o <= 'h0 ;`
645			`bits_transfered <= 'h0 ;`
646			`write_done_o <= 'h0 ;`
647			`dat_rdy_o <= 'h0 ;`
648			`send_ack <= 'h0 ;`
649			`rec_bit <= 'h0 ;`
650			`end`
651			`else`
652			`begin`
653
654			`case (rw_seq_state)`
655
656			`rw_seq_idle:`
657			`begin`
658			`tx_shift_reg <= {4'b1010, adr_i[10: 8], 1'b0} ;`
659			`adr_set <= 1'b0 ;`
660
661			`if ( tx_rx_sm_idle & ~(doing_write \| doing_read \| doing_seq_read) )`
662			`begin`
663			`if (do_write_i \| do_rnd_read_i \| do_seq_read_i)`
664			`begin`
665			`rw_seq_state <= rw_seq_tx_ctrl ;`
666			`send_start <= 1'b1 ;`
667			`end`
668
669			`if (do_write_i)`
670			`doing_write <= 1'b1 ;`
671			`else if (do_rnd_read_i)`
672			`doing_read <= 1'b1 ;`
673			`else if (do_seq_read_i)`
674			`doing_seq_read <= 1'b1 ;`
675			`end`
676			`else`
677			`begin`
678			`doing_write <= 1'b0 ;`
679			`doing_read <= 1'b0 ;`
680			`doing_seq_read <= 1'b0 ;`
681			`end`
682			`end`
683
684			`rw_seq_tx_ctrl:`
685			`begin`
686			`if (send_start)`
687			`begin`
688			`bits_transfered <= 'h0 ;`
689
690			`if (start_sent)`
691			`begin`
692			`send_start <= 1'b0 ;`
693			`send_bit <= 1'b1 ;`
694			`end`
695			`end`
696			`else if (send_bit)`
697			`begin`
698			`if (bit_sent)`
699			`begin`
700			`bits_transfered <= bits_transfered + 1'b1 ;`
701			`tx_shift_reg <= {tx_shift_reg[6:0], tx_shift_reg[0]} ;`
702			`end`
703
704			`if (bits_transfered == 'h8)`
705			`begin`
706			`send_bit <= 1'b0 ;`
707			`rec_ack <= 1'b1 ;`
708			`end`
709			`end`
710			`else if (rec_ack)`
711			`begin`
712			`bits_transfered <= 'h0 ;`
713
714			`if (ack_rec \| nack_rec)`
715			`rec_ack <= 1'b0 ;`
716
717			`if (ack_rec)`
718			`begin`
719			`if (doing_write \| ~adr_set)`
720			`begin`
721			`rw_seq_state <= rw_seq_tx_adr ;`
722			`tx_shift_reg <= adr_i[ 7: 0] ;`
723			`send_bit <= 1'b1 ;`
724			`end`
725			`else`
726			`begin`
727			`rw_seq_state <= rw_seq_rx_byte ;`
728			`rec_bit <= 1'b1 ;`
729			`end`
730			`end`
731			`else if (nack_rec)`
732			`begin`
733			`no_ack_o <= 1'b1 ;`
734			`send_stop <= 1'b1 ;`
735			`end`
736			`end`
737			`else if (send_stop)`
738			`begin`
739			`no_ack_o <= 1'b0 ;`
740
741			`if (stop_sent)`
742			`begin`
743			`send_stop <= 1'b0 ;`
744			`rw_seq_state <= rw_seq_idle ;`
745			`end`
746			`end`
747			`end`
748
749			`rw_seq_tx_adr:`
750			`begin`
751			`if (send_bit)`
752			`begin`
753			`if (bit_sent)`
754			`begin`
755			`bits_transfered <= bits_transfered + 1'b1 ;`
756			`tx_shift_reg <= {tx_shift_reg[6:0], tx_shift_reg[0]} ;`
757			`end`
758
759			`if (bits_transfered == 'h8)`
760			`begin`
761			`send_bit <= 1'b0 ;`
762			`rec_ack <= 1'b1 ;`
763			`end`
764			`end`
765			`else if (rec_ack)`
766			`begin`
767			`bits_transfered <= 'h0 ;`
768
769			`if (ack_rec \| nack_rec)`
770			`rec_ack <= 1'b0 ;`
771
772			`if (ack_rec)`
773			`begin`
774
775			`adr_set <= 1'b1 ;`
776
777			`if (doing_write)`
778			`begin`
779			`send_bit <= 1'b1 ;`
780			`rw_seq_state <= rw_seq_tx_byte ;`
781			`tx_shift_reg <= dat_i ;`
782			`end`
783			`else if (doing_read \| doing_seq_read)`
784			`begin`
785			`send_start <= 1'b1 ;`
786			`rw_seq_state <= rw_seq_tx_ctrl ;`
787			`tx_shift_reg <= 8'b10100001 ;`
788			`end`
789			`end`
790			`else if (nack_rec)`
791			`begin`
792			`no_ack_o <= 1'b1 ;`
793			`send_stop <= 1'b1 ;`
794			`end`
795			`end`
796			`else if (send_stop)`
797			`begin`
798			`no_ack_o <= 1'b0 ;`
799
800			`if (stop_sent)`
801			`begin`
802			`send_stop <= 1'b0 ;`
803			`rw_seq_state <= rw_seq_idle ;`
804			`end`
805			`end`
806			`end`
807
808			`rw_seq_tx_byte:`
809			`begin`
810			`if (send_bit)`
811			`begin`
812			`if (bit_sent)`
813			`begin`
814			`bits_transfered <= bits_transfered + 1'b1 ;`
815			`tx_shift_reg <= {tx_shift_reg[6:0], tx_shift_reg[0]} ;`
816			`end`
817
818			`if (bits_transfered == 'h8)`
819			`begin`
820			`send_bit <= 1'b0 ;`
821			`rec_ack <= 1'b1 ;`
822			`end`
823			`end`
824			`else if (rec_ack)`
825			`begin`
826			`bits_transfered <= 'h0 ;`
827
828			`if (ack_rec \| nack_rec)`
829			`begin`
830			`rec_ack <= 1'b0 ;`
831			`send_stop <= 1'b1 ;`
832			`end`
833
834			`if (nack_rec)`
835			`no_ack_o <= 1'b1 ;`
836
837			`if (ack_rec)`
838			`write_done_o <= 1'b1 ;`
839			`end`
840			`else if (send_stop)`
841			`begin`
842			`no_ack_o <= 1'b0 ;`
843			`write_done_o <= 1'b0 ;`
844
845			`if (stop_sent)`
846			`begin`
847			`send_stop <= 1'b0 ;`
848			`rw_seq_state <= rw_seq_idle ;`
849			`end`
850			`end`
851			`end`
852
853			`rw_seq_rx_byte:`
854			`begin`
855			`if (rec_bit)`
856			`begin`
857			`if (bit_rec)`
858			`begin`
859			`bits_transfered <= bits_transfered + 1'b1 ;`
860			`dat_o <= {dat_o[6:0], sda_i_reg} ;`
861			`end`
862
863			`if (bits_transfered == 'h8)`
864			`begin`
865			`rec_bit <= 1'b0 ;`
866			`dat_rdy_o <= 1'b1 ;`
867			`if (doing_read)`
868			`send_nack <= 1'b1 ;`
869			`else`
870			`send_ack <= 1'b1 ;`
871			`end`
872			`end`
873			`else if (send_nack)`
874			`begin`
875			`dat_rdy_o <= 1'b0 ;`
876			`bits_transfered <= 'h0 ;`
877
878			`if (nack_sent)`
879			`begin`
880			`send_stop <= 1'b1 ;`
881			`send_nack <= 1'b0 ;`
882			`end`
883			`end`
884			`else if (send_ack)`
885			`begin`
886			`dat_rdy_o <= 1'b0 ;`
887			`bits_transfered <= 'h0 ;`
888
889			`if (~do_seq_read_i)`
890			`begin`
891			`send_ack <= 1'b0 ;`
892			`send_nack <= 1'b1 ;`
893			`end`
894			`else if (ack_sent)`
895			`begin`
896			`send_ack <= 1'b0 ;`
897			`rec_bit <= 1'b1 ;`
898			`end`
899			`end`
900			`else if (send_stop)`
901			`begin`
902			`if (stop_sent)`
903			`begin`
904			`send_stop <= 1'b0 ;`
905			`rw_seq_state <= rw_seq_idle ;`
906			`end`
907			`end`
908			`end`
909			`endcase`
910			`end`
911			`end`
912
913			`endmodule // pci_spoci_ctrl`