OpenCores
URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [trunk/] [rtl/] [verilog/] [pci_user_constants.v] - Blame information for rev 18

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 18 mihad
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  File name "pci_user_constants.v"                            ////
4
////                                                              ////
5
////  This file is part of the "PCI bridge" project               ////
6
////  http://www.opencores.org/cores/pci/                         ////
7
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Miha Dolenc (mihad@opencores.org)                     ////
10
////      - Tadej Markovic (tadej@opencores.org)                  ////
11
////                                                              ////
12
//////////////////////////////////////////////////////////////////////
13
////                                                              ////
14
//// Copyright (C) 2000 Miha Dolenc, mihad@opencores.org          ////
15
////                                                              ////
16
//// This source file may be used and distributed without         ////
17
//// restriction provided that this copyright statement is not    ////
18
//// removed from the file and that any derivative work contains  ////
19
//// the original copyright notice and the associated disclaimer. ////
20
////                                                              ////
21
//// This source file is free software; you can redistribute it   ////
22
//// and/or modify it under the terms of the GNU Lesser General   ////
23
//// Public License as published by the Free Software Foundation; ////
24
//// either version 2.1 of the License, or (at your option) any   ////
25
//// later version.                                               ////
26
////                                                              ////
27
//// This source is distributed in the hope that it will be       ////
28
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
29
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
30
//// PURPOSE.  See the GNU Lesser General Public License for more ////
31
//// details.                                                     ////
32
////                                                              ////
33
//// You should have received a copy of the GNU Lesser General    ////
34
//// Public License along with this source; if not, download it   ////
35
//// from http://www.opencores.org/lgpl.shtml                     ////
36
////                                                              ////
37
//////////////////////////////////////////////////////////////////////
38
//
39
// CVS Revision History
40
//
41
// $Log: not supported by cvs2svn $
42
//
43
 
44
// Fifo implementation defines:
45
// If FPGA and XILINX are defined, Xilinx's BlockSelectRAM+ is instantiated for Fifo storage.
46
// 16 bit width is used, so 8 bits of address ( 256 ) locations are available. If RAM_DONT_SHARE is not defined (commented out),
47
// then one block RAM is shared between two FIFOs. That means each Fifo can have a maximum address length of 7 - depth of 128 and only 6 block rams are used
48
// If RAM_DONT_SHARE is defined ( not commented out ), then 12 block RAMs are used and each Fifo can have a maximum address length of 8 ( 256 locations )
49
// If FPGA is not defined, then ASIC RAMs are used. Currently there is only one version of ARTISAN RAM supported. User should generate synchronous RAM with
50
// width of 40 and instantiate it in pci_tpram.v. If RAM_DONT_SHARE is defined, then these can be dual port rams ( write port
51
// in one clock domain, read in other ), otherwise it must be two port RAM ( read and write ports in both clock domains ).
52
// If RAM_DONT_SHARE is defined, then all RAM address lengths must be specified accordingly, otherwise there are two relevant lengths - PCI_FIFO_RAM_ADDR_LENGTH and
53
// WB_FIFO_RAM_ADDR_LENGTH.
54
 
55
`define WBW_ADDR_LENGTH 6
56
`define WBR_ADDR_LENGTH 4
57
`define PCIW_ADDR_LENGTH 6
58
`define PCIR_ADDR_LENGTH 3
59
 
60
`define FPGA
61
`define XILINX
62
 
63
//`define WB_RAM_DONT_SHARE
64
//`define PCI_RAM_DONT_SHARE
65
 
66
`ifdef FPGA
67
    `ifdef XILINX
68
        `define PCI_FIFO_RAM_ADDR_LENGTH 8      // PCI target unit fifo storage definition
69
        `define WB_FIFO_RAM_ADDR_LENGTH 8       // WB slave unit fifo storage definition
70
        `define PCI_XILINX_RAMB4
71
        `define WB_XILINX_RAMB4
72
        //`define PCI_XILINX_DIST_RAM
73
        //`define WB_XILINX_DIST_RAM
74
    `endif
75
`else
76
    `define PCI_FIFO_RAM_ADDR_LENGTH 8      // PCI target unit fifo storage definition when RAM sharing is used ( both pcir and pciw fifo use same instance of RAM )
77
    `define WB_FIFO_RAM_ADDR_LENGTH 8       // WB slave unit fifo storage definition when RAM sharing is used ( both wbr and wbw fifo use same instance of RAM )
78
    `define WB_ARTISAN_SDP
79
    `define PCI_ARTISAN_SDP
80
`endif
81
 
82
// these two defines allow user to select active high or low output enables on PCI bus signals, depending on
83
// output buffers instantiated. Xilinx FPGAs use active low output enables.
84
`define ACTIVE_LOW_OE
85
//`define ACTIVE_HIGH_OE
86
 
87
// HOST/GUEST implementation selection - see design document and specification for description of each implementation
88
// only one can be defined at same time
89
//`define GUEST
90
`define HOST
91
 
92
// if NO_CNF_IMAGE is commented out, then READ-ONLY access to configuration space is ENABLED:
93
// - ENABLED Read-Only access from WISHBONE for GUEST bridges
94
// - ENABLED Read-Only access from PCI for HOST bridges
95
// with defining NO_CNF_IMAGE, one decoder and one multiplexer are saved
96
`define NO_CNF_IMAGE
97
 
98
// number defined here specifies how many MS bits in PCI address are compared with base address, to decode
99
// accesses. Maximum number allows for minimum image size ( number = 20, image size = 4KB ), minimum number
100
// allows for maximum image size ( number = 1, image size = 2GB ). If you intend on using different sizes of PCI images,
101
// you have to define a number of minimum sized image and enlarge others by specifying different address mask.
102
// smaller the number here, faster the decoder operation
103
`define PCI_NUM_OF_DEC_ADDR_LINES 3
104
 
105
// no. of PCI Target IMAGES
106
// - PCI provides 6 base address registers for image implementation.
107
// PCI_IMAGE1 definition is not required and has no effect, since PCI image 1 is always implemented
108
// If GUEST is defined, PCI Image 0 is also always implemented and is used for configuration space
109
// access.
110
// If HOST is defined and NO_CNF_IMAGE is not, then PCI Image 0 is used for Read Only access to configuration
111
// space. If HOST is defined and NO_CNF_IMAGE is defined, then user can define PCI_IMAGE0 as normal image, and there
112
// is no access to Configuration space possible from PCI bus.
113
// Implementation of all other PCI images is selected by defining PCI_IMAGE2 through PCI_IMAGE5 regardles of HOST
114
// or GUEST implementation.
115
`ifdef HOST
116
    `ifdef NO_CNF_IMAGE
117
        `define PCI_IMAGE0
118
    `endif
119
`endif
120
 
121
//`define PCI_IMAGE2
122
`define PCI_IMAGE3
123
//`define PCI_IMAGE4
124
`define PCI_IMAGE5
125
 
126
// initial value for PCI image address masks. Address masks can be defined in enabled state,
127
// to allow device independent software to detect size of image and map base addresses to
128
// memory space. If initial mask for an image is defined as 0, then device independent software
129
// won't detect base address implemented and device dependent software will have to configure
130
// address masks as well as base addresses!
131
`define PCI_AM0 20'hffff_f
132
`define PCI_AM1 20'hffff_f
133
`define PCI_AM2 20'hffff_f
134
`define PCI_AM3 20'hffff_f
135
`define PCI_AM4 20'hffff_f
136
`define PCI_AM5 20'hffff_f
137
 
138
// initial value for PCI image maping to MEMORY or IO spaces.  If initial define is set to 0,
139
// then IMAGE with that base address points to MEMORY space, othervise it points ti IO space. D
140
// Device independent software sets the base addresses acording to MEMORY or IO maping!
141
`define PCI_BA0_MEM_IO 1'b0 // considered only when PCI_IMAGE0 is used as general PCI-WB image!
142
`define PCI_BA1_MEM_IO 1'b0
143
`define PCI_BA2_MEM_IO 1'b0
144
`define PCI_BA3_MEM_IO 1'b0
145
`define PCI_BA4_MEM_IO 1'b0
146
`define PCI_BA5_MEM_IO 1'b0
147
 
148
// number defined here specifies how many MS bits in WB address are compared with base address, to decode
149
// accesses. Maximum number allows for minimum image size ( number = 20, image size = 4KB ), minimum number
150
// allows for maximum image size ( number = 1, image size = 2GB ). If you intend on using different sizes of WB images,
151
// you have to define a number of minimum sized image and enlarge others by specifying different address mask.
152
// smaller the number here, faster the decoder operation
153
`define WB_NUM_OF_DEC_ADDR_LINES 20
154
 
155
// no. of WISHBONE Slave IMAGES
156
// WB image 0 is always used for access to configuration space. In case configuration space access is not implemented,
157
// ( both GUEST and NO_CNF_IMAGE defined ), then WB image 0 is not implemented. User doesn't need to define image 0.
158
// WB Image 1 is always implemented and user doesnt need to specify its definition
159
// WB images' 2 through 5 implementation by defining each one.
160
//`define WB_IMAGE2
161
`define WB_IMAGE3
162
`define WB_IMAGE4
163
//`define WB_IMAGE5
164
 
165
// If this define is commented out, then address translation will not be implemented.
166
// addresses will pass through bridge unchanged, regardles of address translation enable bits.
167
// Address translation also slows down the decoding
168
//`define ADDR_TRAN_IMPL
169
 
170
// decode speed for WISHBONE definition - initial cycle on WISHBONE bus will take 1 WS for FAST, 2 WSs for MEDIUM and 3 WSs for slow.
171
// slower decode speed can be used, to provide enough time for address to be decoded.
172
//`define WB_DECODE_FAST
173
`define WB_DECODE_MEDIUM
174
//`define WB_DECODE_SLOW
175
 
176
// Base address for Configuration space access from WB bus. This value cannot be changed during runtime
177
`define WB_CONFIGURATION_BASE 20'h0000_0
178
 
179
// Turn registered WISHBONE slave outputs on or off
180
// all outputs from WB Slave state machine are registered, if this is defined - WB bus outputs as well as
181
// outputs to internals of the core.
182
`define REGISTER_WBS_OUTPUTS
183
 
184
/*-----------------------------------------------------------------------------------------------------------
185
Core speed definition - used for simulation and 66MHz Capable bit value in status register indicating 66MHz
186
capable device
187
-----------------------------------------------------------------------------------------------------------*/
188
`define PCI33
189
//`define PCI66
190
 
191
/*-----------------------------------------------------------------------------------------------------------
192
[000h-00Ch] First 4 DWORDs (32-bit) of PCI configuration header - the same regardless of the HEADER type !
193
        Vendor_ID is an ID for a specific vendor defined by PCI_SIG - 2321h does not belong to anyone (e.g.
194
        Xilinx's Vendor_ID is 10EEh and Altera's Vendor_ID is 1172h). Device_ID and Revision_ID should be used
195
        together by application.
196
-----------------------------------------------------------------------------------------------------------*/
197
`define HEADER_VENDOR_ID    16'h2321
198
`define HEADER_DEVICE_ID    16'h0001
199
`define HEADER_REVISION_ID  8'h01
200
 
201
// Turn registered WISHBONE master outputs on or off
202
// all outputs from WB Master state machine are registered, if this is defined - WB bus outputs as well as
203
// outputs to internals of the core.
204
//`define REGISTER_WBM_OUTPUTS
205
 
206
// MAX Retry counter value for WISHBONE Master state-machine
207
//      This value is 8-bit because of 8-bit retry counter !!!
208
`define WB_RTY_CNT_MAX                  8'hff

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.