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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  File name "pci_wbs_wbb3_2_wbb2.v"                           ////
////                                                              ////
////  This file is part of the "PCI bridge" project               ////
////  http://www.opencores.org/cores/pci/                         ////
////                                                              ////
////  Author(s):                                                  ////
////      - Miha Dolenc (mihad@opencores.org)                     ////
////                                                              ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2003 Miha Dolenc, mihad@opencores.org          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2003/08/12 13:58:19  mihad
// Module that converts slave WISHBONE B3 accesses to
// WISHBONE B2 accesses with CAB.
//
//
 
module pci_wbs_wbb3_2_wbb2
(
    wb_clk_i,
    wb_rst_i,
 
    wbs_cyc_i,
    wbs_cyc_o,
    wbs_stb_i,
    wbs_stb_o,
    wbs_adr_i,
    wbs_adr_o,
    wbs_dat_i_i,
    wbs_dat_i_o,
    wbs_dat_o_i,
    wbs_dat_o_o,
    wbs_we_i,
    wbs_we_o,
    wbs_sel_i,
    wbs_sel_o,
    wbs_ack_i,
    wbs_ack_o,
    wbs_err_i,
    wbs_err_o,
    wbs_rty_i,
    wbs_rty_o,
    wbs_cti_i,
    wbs_bte_i,
    wbs_cab_o
) ;
 
input       wb_clk_i    ;
input       wb_rst_i    ;
 
input           wbs_cyc_i   ;
output          wbs_cyc_o   ;
input           wbs_stb_i   ;
output          wbs_stb_o   ;
input   [31:0]  wbs_adr_i   ;
output  [31:0]  wbs_adr_o   ;
input   [31:0]  wbs_dat_i_i ;
output  [31:0]  wbs_dat_i_o ;
input   [31:0]  wbs_dat_o_i ;
output  [31:0]  wbs_dat_o_o ;
input           wbs_we_i    ;
output          wbs_we_o    ;
input   [ 3:0]  wbs_sel_i   ;
output  [ 3:0]  wbs_sel_o   ;
input           wbs_ack_i   ;
output          wbs_ack_o   ;
input           wbs_err_i   ;
output          wbs_err_o   ;
input           wbs_rty_i   ;
output          wbs_rty_o   ;
input   [ 2:0]  wbs_cti_i   ;
input   [ 1:0]  wbs_bte_i   ;
output          wbs_cab_o   ;
 
reg             wbs_cyc_o           ;
reg     [31:0]  wbs_adr_o           ;
reg     [31:0]  wbs_dat_i_o         ;
reg             wbs_dat_i_o_valid   ;
reg     [31:0]  wbs_dat_o_o         ;
reg             wbs_we_o            ;
reg     [ 3:0]  wbs_sel_o           ;
reg             wbs_ack_o           ;
reg             wbs_err_o           ;
reg             wbs_rty_o           ;
reg             wbs_cab_o           ;
 
always@(posedge wb_rst_i or posedge wb_clk_i)
begin
    if (wb_rst_i)
    begin
        wbs_cyc_o           <= 1'b0  ;
        wbs_adr_o           <= 32'h0 ;
        wbs_dat_i_o         <= 32'h0 ;
        wbs_dat_o_o         <= 32'h0 ;
        wbs_sel_o           <= 4'h0  ;
        wbs_we_o            <= 1'b0  ;
        wbs_dat_i_o_valid   <= 1'b0  ;
    end
    else
    begin:transfer_and_transfer_adr_ctrl_blk
        reg start_cycle            ;
        reg [3:0] end_cycle        ;
        reg generate_int_adr       ;
 
        start_cycle  = ~wbs_cyc_o & wbs_cyc_i & wbs_stb_i & ~wbs_ack_o & ~wbs_err_o & ~wbs_rty_o ;
 
        // there is a few conditions when cycle must be terminated
        // I've put them into bit array for better readability of the code
 
        // 1st condition - pci bridge is signaling an error
        end_cycle[0] = wbs_err_i ;
 
        // 2nd condition - pci bridge is signaling a retry - that can be ignored via the defines
        end_cycle[1] = wbs_rty_i
            `ifdef PCI_WBS_B3_RTY_DISABLE
                & 1'b0
            `endif
                ;
 
        // 3rd condition - end non burst cycles as soon as pci bridge response is received
        end_cycle[2] = wbs_cyc_i & wbs_stb_i & wbs_ack_i & ~wbs_cab_o ;
 
        // 4th condition - end cycle when acknowledge and strobe are both asserted and master is signaling end of burst
        end_cycle[3] = wbs_cyc_i & wbs_stb_i & wbs_ack_o & wbs_cab_o & (wbs_cti_i == 3'b111) ;
 
        if (wbs_dat_i_o_valid)
        begin
            if (wbs_ack_i | wbs_err_i
                `ifdef PCI_WBS_B3_RTY_DISABLE
                `else
                    | wbs_rty_i
                `endif
                    )
                wbs_dat_i_o_valid <= 1'b0 ;
        end
        else
        begin
            if (wbs_cyc_i & wbs_stb_i & wbs_we_i & ~wbs_ack_o & ~wbs_err_o & ~wbs_rty_o)
            begin
                wbs_dat_i_o       <= wbs_dat_i_i ;
                wbs_dat_i_o_valid <= 1'b1 ;
            end
        end
 
        if (start_cycle)
        begin
            wbs_cyc_o   <= 1'b1         ;
            wbs_sel_o   <= wbs_sel_i    ;
            wbs_we_o    <= wbs_we_i     ;
 
            if (wbs_cti_i == 3'b010)
            begin
                case (wbs_bte_i)
                2'b00:  begin
                            wbs_cab_o <= 1'b1 ;
                        end
                2'b01:  begin
                            if (wbs_adr_i[3:0] == 4'b0000)
                                wbs_cab_o <= 1'b1 ;
                            else
                                wbs_cab_o <= 1'b0 ;
                        end
                2'b10:  begin
                            if (wbs_adr_i[4:0] == 5'b00000)
                                wbs_cab_o <= 1'b1 ;
                            else
                                wbs_cab_o <= 1'b0 ;
                        end
                2'b11:  begin
                            if (wbs_adr_i[5:0] == 6'b000000)
                                wbs_cab_o <= 1'b1 ;
                            else
                                wbs_cab_o <= 1'b0 ;
                        end
                endcase
            end
            else
            begin
                wbs_cab_o <= 1'b0 ;
            end
        end
        else if ( wbs_cyc_o & (|end_cycle) )
        begin
            wbs_cyc_o <= 1'b0 ;
        end
 
        if (start_cycle)
            wbs_adr_o <= wbs_adr_i ;
        else if (wbs_ack_i)
            wbs_adr_o[31:2] <= wbs_adr_o[31:2] + 1'b1 ;
 
        if (~wbs_we_o & wbs_ack_i)
            wbs_dat_o_o <= wbs_dat_o_i ;
    end
end
 
always@(posedge wb_rst_i or posedge wb_clk_i)
begin
    if (wb_rst_i)
    begin
        wbs_ack_o <= 1'b0 ;
        wbs_err_o <= 1'b0 ;
        wbs_rty_o <= 1'b0 ;
    end
    else
    begin
        if (wbs_ack_o)
            wbs_ack_o <= wbs_ack_i | ~wbs_stb_i ;
        else
            wbs_ack_o <= wbs_ack_i ;
 
        if (wbs_err_o)
            wbs_err_o <= ~wbs_stb_i ;
        else
            wbs_err_o <= wbs_err_i ;
 
    `ifdef PCI_WBS_B3_RTY_DISABLE
        wbs_rty_o <= 1'b0 ;
    `else
        if (wbs_rty_o)
            wbs_rty_o <= ~wbs_stb_i ;
        else
            wbs_rty_o <= wbs_rty_i ;
    `endif
    end
end
 
assign wbs_stb_o = (wbs_cyc_o & ~wbs_we_o & ~wbs_ack_o & ~wbs_err_o & ~wbs_rty_o) |
                   (wbs_cyc_o & wbs_stb_i & wbs_cab_o & ~wbs_we_o & wbs_cti_i !== 3'b111) |
                   (wbs_cyc_o & wbs_we_o & wbs_dat_i_o_valid) ;
 
endmodule

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[/] [pci/] [trunk/] [rtl/] [verilog/] [pci_wbs_wbb3_2_wbb2.v] - Blame information for rev 126

Line No.	Rev	Author	Line
1	110	mihad	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// File name "pci_wbs_wbb3_2_wbb2.v" ////`
4			`//// ////`
5			`//// This file is part of the "PCI bridge" project ////`
6			`//// http://www.opencores.org/cores/pci/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Miha Dolenc (mihad@opencores.org) ////`
10			`//// ////`
11			`//// ////`
12			`//// ////`
13			`//////////////////////////////////////////////////////////////////////`
14			`//// ////`
15			`//// Copyright (C) 2003 Miha Dolenc, mihad@opencores.org ////`
16			`//// ////`
17			`//// This source file may be used and distributed without ////`
18			`//// restriction provided that this copyright statement is not ////`
19			`//// removed from the file and that any derivative work contains ////`
20			`//// the original copyright notice and the associated disclaimer. ////`
21			`//// ////`
22			`//// This source file is free software; you can redistribute it ////`
23			`//// and/or modify it under the terms of the GNU Lesser General ////`
24			`//// Public License as published by the Free Software Foundation; ////`
25			`//// either version 2.1 of the License, or (at your option) any ////`
26			`//// later version. ////`
27			`//// ////`
28			`//// This source is distributed in the hope that it will be ////`
29			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
30			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
31			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
32			`//// details. ////`
33			`//// ////`
34			`//// You should have received a copy of the GNU Lesser General ////`
35			`//// Public License along with this source; if not, download it ////`
36			`//// from http://www.opencores.org/lgpl.shtml ////`
37			`//// ////`
38			`//////////////////////////////////////////////////////////////////////`
39			`//`
40			`// CVS Revision History`
41			`//`
42			`// $Log: not supported by cvs2svn $`
43	126	simons	`// Revision 1.1 2003/08/12 13:58:19 mihad`
44			`// Module that converts slave WISHBONE B3 accesses to`
45			`// WISHBONE B2 accesses with CAB.`
46	110	mihad	`//`
47	126	simons	`//`
48	110	mihad
49			`module pci_wbs_wbb3_2_wbb2`
50			`(`
51			`wb_clk_i,`
52			`wb_rst_i,`
53
54			`wbs_cyc_i,`
55			`wbs_cyc_o,`
56			`wbs_stb_i,`
57			`wbs_stb_o,`
58			`wbs_adr_i,`
59			`wbs_adr_o,`
60			`wbs_dat_i_i,`
61			`wbs_dat_i_o,`
62			`wbs_dat_o_i,`
63			`wbs_dat_o_o,`
64			`wbs_we_i,`
65			`wbs_we_o,`
66			`wbs_sel_i,`
67			`wbs_sel_o,`
68			`wbs_ack_i,`
69			`wbs_ack_o,`
70			`wbs_err_i,`
71			`wbs_err_o,`
72			`wbs_rty_i,`
73			`wbs_rty_o,`
74			`wbs_cti_i,`
75			`wbs_bte_i,`
76			`wbs_cab_o`
77			`) ;`
78
79			`input wb_clk_i ;`
80			`input wb_rst_i ;`
81
82			`input wbs_cyc_i ;`
83			`output wbs_cyc_o ;`
84			`input wbs_stb_i ;`
85			`output wbs_stb_o ;`
86			`input [31:0] wbs_adr_i ;`
87			`output [31:0] wbs_adr_o ;`
88			`input [31:0] wbs_dat_i_i ;`
89			`output [31:0] wbs_dat_i_o ;`
90			`input [31:0] wbs_dat_o_i ;`
91			`output [31:0] wbs_dat_o_o ;`
92			`input wbs_we_i ;`
93			`output wbs_we_o ;`
94			`input [ 3:0] wbs_sel_i ;`
95			`output [ 3:0] wbs_sel_o ;`
96			`input wbs_ack_i ;`
97			`output wbs_ack_o ;`
98			`input wbs_err_i ;`
99			`output wbs_err_o ;`
100			`input wbs_rty_i ;`
101			`output wbs_rty_o ;`
102			`input [ 2:0] wbs_cti_i ;`
103			`input [ 1:0] wbs_bte_i ;`
104			`output wbs_cab_o ;`
105
106			`reg wbs_cyc_o ;`
107			`reg [31:0] wbs_adr_o ;`
108			`reg [31:0] wbs_dat_i_o ;`
109			`reg wbs_dat_i_o_valid ;`
110			`reg [31:0] wbs_dat_o_o ;`
111			`reg wbs_we_o ;`
112			`reg [ 3:0] wbs_sel_o ;`
113			`reg wbs_ack_o ;`
114			`reg wbs_err_o ;`
115			`reg wbs_rty_o ;`
116			`reg wbs_cab_o ;`
117
118			`always@(posedge wb_rst_i or posedge wb_clk_i)`
119			`begin`
120			`if (wb_rst_i)`
121			`begin`
122			`wbs_cyc_o <= 1'b0 ;`
123			`wbs_adr_o <= 32'h0 ;`
124			`wbs_dat_i_o <= 32'h0 ;`
125			`wbs_dat_o_o <= 32'h0 ;`
126			`wbs_sel_o <= 4'h0 ;`
127			`wbs_we_o <= 1'b0 ;`
128			`wbs_dat_i_o_valid <= 1'b0 ;`
129			`end`
130			`else`
131			`begin:transfer_and_transfer_adr_ctrl_blk`
132			`reg start_cycle ;`
133			`reg [3:0] end_cycle ;`
134			`reg generate_int_adr ;`
135
136			`start_cycle = ~wbs_cyc_o & wbs_cyc_i & wbs_stb_i & ~wbs_ack_o & ~wbs_err_o & ~wbs_rty_o ;`
137
138			`// there is a few conditions when cycle must be terminated`
139			`// I've put them into bit array for better readability of the code`
140
141			`// 1st condition - pci bridge is signaling an error`
142			`end_cycle[0] = wbs_err_i ;`
143
144			`// 2nd condition - pci bridge is signaling a retry - that can be ignored via the defines`
145	126	simons	`end_cycle[1] = wbs_rty_i`
146			`ifdef PCI_WBS_B3_RTY_DISABLE
147			`& 1'b0`
148			`endif
149			`;`
150	110	mihad
151			`// 3rd condition - end non burst cycles as soon as pci bridge response is received`
152			`end_cycle[2] = wbs_cyc_i & wbs_stb_i & wbs_ack_i & ~wbs_cab_o ;`
153
154			`// 4th condition - end cycle when acknowledge and strobe are both asserted and master is signaling end of burst`
155			`end_cycle[3] = wbs_cyc_i & wbs_stb_i & wbs_ack_o & wbs_cab_o & (wbs_cti_i == 3'b111) ;`
156
157			`if (wbs_dat_i_o_valid)`
158			`begin`
159	126	simons	`if (wbs_ack_i \| wbs_err_i`
160			`ifdef PCI_WBS_B3_RTY_DISABLE
161			`else
162			`\| wbs_rty_i`
163			`endif
164			`)`
165	110	mihad	`wbs_dat_i_o_valid <= 1'b0 ;`
166			`end`
167			`else`
168			`begin`
169			`if (wbs_cyc_i & wbs_stb_i & wbs_we_i & ~wbs_ack_o & ~wbs_err_o & ~wbs_rty_o)`
170			`begin`
171			`wbs_dat_i_o <= wbs_dat_i_i ;`
172			`wbs_dat_i_o_valid <= 1'b1 ;`
173			`end`
174			`end`
175
176			`if (start_cycle)`
177			`begin`
178			`wbs_cyc_o <= 1'b1 ;`
179			`wbs_sel_o <= wbs_sel_i ;`
180			`wbs_we_o <= wbs_we_i ;`
181
182			`if (wbs_cti_i == 3'b010)`
183			`begin`
184			`case (wbs_bte_i)`
185			`2'b00: begin`
186			`wbs_cab_o <= 1'b1 ;`
187			`end`
188			`2'b01: begin`
189			`if (wbs_adr_i[3:0] == 4'b0000)`
190			`wbs_cab_o <= 1'b1 ;`
191			`else`
192			`wbs_cab_o <= 1'b0 ;`
193			`end`
194			`2'b10: begin`
195			`if (wbs_adr_i[4:0] == 5'b00000)`
196			`wbs_cab_o <= 1'b1 ;`
197			`else`
198			`wbs_cab_o <= 1'b0 ;`
199			`end`
200			`2'b11: begin`
201			`if (wbs_adr_i[5:0] == 6'b000000)`
202			`wbs_cab_o <= 1'b1 ;`
203			`else`
204			`wbs_cab_o <= 1'b0 ;`
205			`end`
206			`endcase`
207			`end`
208			`else`
209			`begin`
210			`wbs_cab_o <= 1'b0 ;`
211			`end`
212			`end`
213			`else if ( wbs_cyc_o & (\|end_cycle) )`
214			`begin`
215			`wbs_cyc_o <= 1'b0 ;`
216			`end`
217
218			`if (start_cycle)`
219			`wbs_adr_o <= wbs_adr_i ;`
220			`else if (wbs_ack_i)`
221			`wbs_adr_o[31:2] <= wbs_adr_o[31:2] + 1'b1 ;`
222
223			`if (~wbs_we_o & wbs_ack_i)`
224			`wbs_dat_o_o <= wbs_dat_o_i ;`
225			`end`
226			`end`
227
228			`always@(posedge wb_rst_i or posedge wb_clk_i)`
229			`begin`
230			`if (wb_rst_i)`
231			`begin`
232			`wbs_ack_o <= 1'b0 ;`
233			`wbs_err_o <= 1'b0 ;`
234			`wbs_rty_o <= 1'b0 ;`
235			`end`
236			`else`
237			`begin`
238			`if (wbs_ack_o)`
239			`wbs_ack_o <= wbs_ack_i \| ~wbs_stb_i ;`
240			`else`
241			`wbs_ack_o <= wbs_ack_i ;`
242
243			`if (wbs_err_o)`
244			`wbs_err_o <= ~wbs_stb_i ;`
245			`else`
246			`wbs_err_o <= wbs_err_i ;`
247
248			`ifdef PCI_WBS_B3_RTY_DISABLE
249			`wbs_rty_o <= 1'b0 ;`
250			`else
251			`if (wbs_rty_o)`
252			`wbs_rty_o <= ~wbs_stb_i ;`
253			`else`
254			`wbs_rty_o <= wbs_rty_i ;`
255			`endif
256			`end`
257			`end`
258
259			`assign wbs_stb_o = (wbs_cyc_o & ~wbs_we_o & ~wbs_ack_o & ~wbs_err_o & ~wbs_rty_o) \|`
260			`(wbs_cyc_o & wbs_stb_i & wbs_cab_o & ~wbs_we_o & wbs_cti_i !== 3'b111) \|`
261			`(wbs_cyc_o & wbs_we_o & wbs_dat_i_o_valid) ;`
262
263	126	simons	`endmodule`