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[/] [pci/] [trunk/] [syn/] [scr/] [cons_vs_umc18.inc] - Blame information for rev 154
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| Line No. |
Rev |
Author |
Line |
| 1 |
18 |
mihad |
/* Constraints */
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| 2 |
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CLK_UNCERTAINTY = 0.1 /* 100 ps */
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| 3 |
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DFFPQ2_CKQ = 0.2 /* Clk to Q in technology time units */
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| 4 |
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DFFPQ2_SETUP = 0.1 /* Setup time in technology time units */
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| 5 |
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| 6 |
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/* Clocks constraints */
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| 7 |
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set_clock_skew all_clocks() -uncertainty CLK_UNCERTAINTY
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| 8 |
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set_dont_touch_network all_clocks()
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| 9 |
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| 10 |
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/* Reset constraints */
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| 11 |
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set_driving_cell -none RST
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| 12 |
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set_drive 0 RST
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| 13 |
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set_dont_touch_network RST
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| 14 |
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| 15 |
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/* All inputs except reset and clock */
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| 16 |
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all_inputs_wo_rst_clk = all_inputs() - PCI_CLK - WB_CLK - RST
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| 17 |
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| 18 |
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/* Set output delays and load for output signals
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| 19 |
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*
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| 20 |
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* All outputs are assumed to go directly into
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| 21 |
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* external flip-flops for the purpose of this
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| 22 |
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* synthesis
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| 23 |
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*/
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| 24 |
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set_load load_of(umcl18u250t2_typ/DFFPQ2/D) * 4 all_outputs()
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| 25 |
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| 26 |
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/* Input delay and driving cell of all inputs
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| 27 |
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*
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| 28 |
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* All these signals are assumed to come directly from
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| 29 |
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* flip-flops for the purpose of this synthesis
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| 30 |
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*
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| 31 |
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*/
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| 32 |
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set_driving_cell -cell DFFPQ2 -pin Q all_inputs_wo_rst_clk
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| 33 |
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| 34 |
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/* Set design fanout */
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| 35 |
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/*
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| 36 |
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set_max_fanout 10 TOPLEVEL
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| 37 |
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*/
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| 38 |
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| 39 |
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/* Set area constraint */
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| 40 |
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set_max_area MAX_AREA
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| 41 |
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| 42 |
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set_operating_conditions -max WORST -max_library umcl18u250t2_wc
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