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[/] [pci/] [trunk/] [syn/] [scr/] [tech_vs_umc18.inc] - Blame information for rev 154
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mihad |
/* Set Virtual Silicon UMC 0.18u standard cell library */
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search_path = {. /projects/libs/Virtual_silicon/UMCL18U250D2_2.1/design_compiler/ /projects/libs/Artisan/artisan_rams/art_hsdp_256x40/}
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snps = get_unix_variable("SYNOPSYS")
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synthetic_library = { \
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snps + "/libraries/syn/dw01.sldb" \
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snps + "/libraries/syn/dw02.sldb" \
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snps + "/libraries/syn/dw03.sldb" \
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snps + "/libraries/syn/dw04.sldb" \
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snps + "/libraries/syn/dw05.sldb" \
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snps + "/libraries/syn/dw06.sldb" \
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snps + "/libraries/syn/dw07.sldb" }
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target_library = { umcl18u250t2_bc.db umcl18u250t2_wc.db art_hsdp_256x40_slow_syn.db art_hsdp_256x40_fast_syn.db}
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link_library = target_library + synthetic_library
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symbol_library = { umcl18u250t2.sdb }
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set_min_library umcl18u250t2_wc.db -min_version umcl18u250t2_bc.db
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