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<!--# include virtual="/ssi/ssi_start.shtml" -->
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<b><font size=+2 face="Helvetica, Arial"color=#bf0000>Project Name: PCI bridge</font></b>
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<p><table align=center border=1 cellPadding=2 cellSpacing=0 width="100%" valign="top">
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<tbody><tr bgcolor=#bbccff> <td align=center valign=center>
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<a href="http://www.opencores.org/cores/pci/index.shtml">Introduction</a> |
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<a href="http://www.opencores.org/cores/pci/documentation.shtml">Documentation</a> |
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<a href="http://www.opencores.org/cores/pci/charact.shtml">Characteristics</a> |
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<a href="http://www.opencores.org/cores/pci/current_stat.shtml">Current Status</a> |
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<a href="http://www.opencores.org/cores/pci/todo_list.shtml">To Do list</a> |
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<a href="http://www.opencores.org/cores/pci/test_app.shtml">Test Application</a> |
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<a href="http://www.opencores.org/cores/pci/download.shtml">Download</a> |
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<a href="http://www.opencores.org/cores/pci/testbench.shtml">Testbench</a> |
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<a href="http://www.opencores.org/cores/pci/references.shtml">References</a> |
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<a href="http://www.opencores.org/cores/pci/links.shtml">Links</a> |
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<a href="mailto:pci@opencores.org">Mailing list</a> |
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<a href="http://www.opencores.org/cores/pci/contacts.shtml">Contacts</a>
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</td></tr></tbody>
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</table>
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<table border=0 cellPadding=0 cellSpacing=0 width="100%">
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<tbody><tr><td>
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<p><center><font color="#bf0000" size=+3><b>Characteristics</b></font></center>
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</p></td></tr>
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<tr><td align=left>
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<font color="000088"size=+1>
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<b>Supported targets<br>
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</b></font>
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</td></tr>
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<tr><td align=left>
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<font>
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<br>We prepared PCI bridge core to be implemented into the Xilinx FPGA (tested on Spartan II).
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Now we are preparing it for ASIC. Artisan memory blocks are already prepared.
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<br><br>
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</font>
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</td></tr>
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<tr><td align=left>
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<font color="000088"size=+1>
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<b>Size in FPGAs<br>
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</b></font>
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</td></tr>
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<tr><td align=left>
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<font>
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<br>We implement PCI bridge into Spartan II 150 Kgates -5 speed grade. We used 2 base addresses
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for accessing the WISHBONE bus from PCI side and 2 base addresses for accessing the PCI bus from
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WISHBONE side. We used 6 Block Select+ RAMs for FIFOs and all synchronization for two clock
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domains. PCI bridge also consists all Image and Control registers beside PCI Header.
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With all these features PCI bridge occupies about 1300 Xilinx FPGA slices (76% of Spartan II 150).
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<br><br>
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This will be updated soon for other FPGAs.
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<br><br>
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</font>
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</td></tr>
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</table><!--# include virtual="/ssi/ssi_end.shtml" -->
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