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<!--# include virtual="/ssi/ssi_start.shtml" -->
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<b><font size=+2 face="Helvetica, Arial"color=#bf0000>Project Name: PCI bridge</font></b>
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<p><table align=center border=1 cellPadding=2 cellSpacing=0 width="100%" valign="top">
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<tbody><tr bgcolor=#bbccff> <td align=center valign=center>
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<a href="http://www.opencores.org/cores/pci/index.shtml">Introduction</a> |
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<a href="http://www.opencores.org/cores/pci/documentation.shtml">Documentation</a> |
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<a href="http://www.opencores.org/cores/pci/charact.shtml">Characteristics</a> |
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<a href="http://www.opencores.org/cores/pci/current_stat.shtml">Current Status</a> |
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<a href="http://www.opencores.org/cores/pci/todo_list.shtml">To Do list</a> |
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<a href="http://www.opencores.org/cores/pci/test_app.shtml">Test Application</a> |
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<a href="http://www.opencores.org/cores/pci/download.shtml">Download</a> |
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<a href="http://www.opencores.org/cores/pci/testbench.shtml">Testbench</a> |
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<a href="http://www.opencores.org/cores/pci/references.shtml">References</a> |
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<a href="http://www.opencores.org/cores/pci/links.shtml">Links</a> |
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<a href="mailto:pci@opencores.org">Mailing list</a> |
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<a href="http://www.opencores.org/cores/pci/contacts.shtml">Contacts</a>
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</td></tr></tbody>
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</table>
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<table border=0 cellPadding=0 cellSpacing=0 width="100%">
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<tbody><tr><td>
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<p><center><font color="#bf0000" size=+3><b>Current Status</b></font></center>
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</p></td></tr>
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<tr><td align=left>
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<font color="000088"size=+1>
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<b>Current Status:<br>
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</b></font>
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</td></tr>
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<tr><td align=left>
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<font>
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<br>
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<ul>
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<li>Most of RTL design for 32-bit PCI bridge done. Sources available via CVS.</li>
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<li>Design synthesized and tested with Insight's PCI development kit (Spartan II 150k gates, speed grade -5).</li>
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<li>Sample application, bit-stream for Insight's kit etc. also available via CVS.</li>
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<li>Specification is updated (there have been some minor changes).</li>
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<li>Working on verification suite (PCI BFMs).</li>
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<li>Design document will be done after verification suite is finished.</li>
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</ul>
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<br><br>
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</font>
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</td></tr>
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<tr><td align=left>
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<font color="000088"size=+1>
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<b>Available Blocks on the opencores CVS:<br>
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</b></font>
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</td></tr>
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<tr><td align=left>
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<font>
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<br>
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<ul>
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<li>Verilog RTL sources for 32-bit PCI to WISHBONE bridge.</li>
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<li>Verilog RTL sources for sample application.</li>
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<li>Bit-stream and timing simulation models for sample application (Can be tested with Insight's PCI development kit).</li>
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<li>Also look at PCI blue interface project - its simulation models will probably be used in this project too (thanks to Blue Beaver).</li>
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</ul>
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<br><br>
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</font>
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</td></tr>
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</table><!--# include virtual="/ssi/ssi_end.shtml" -->
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