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[/] [pci32tlite_oc/] [trunk/] [rtl/] [onalib.vhd] - Blame information for rev 10

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--+-------------------------------------------------------------------------------------------------+
--|                                                                                                                                                                                                     |
--|  Fileo:                     onalib.vhd                                                                                      |       
--|                                                                                                                                                                                                     |
--|  Project:           onalib                                                                                                                                                  |
--|                                                                                                                                                                                                     |
--|  Description:       Libreria de componentes en VHDL.                                                |
--|                                                                                                                                                                                                     |
--+-------------------------------------------------------------------------------------------------+
--|                              Component                                              |                                       Descripcion                                             |
--+-------------------------------------------------------------------------------------------------+
--|     sync(clk, d, q)                                                         | Sincronizacion de una se�al a traves de un FF.        |
--|                                                                                             | Sin reset.                                                                            |
--+-------------------------------------------------------------------------------------------------+
--|     sync2(clk, d, q)                                                        | Doble Sincronizacion de una se�al a traves de dos |
--|                                                                                             | FF. Sin reset.                                                                        |
--+-------------------------------------------------------------------------------------------------+
--|     sync2h(clk, rst, d, q)                                          | Doble Sincronizacion de una se�al a traves de dos |
--|                                                                                             | FF. Con reset e inicializacion a '1'.                         |
--+-------------------------------------------------------------------------------------------------+
--|     sync2l(clk, rst, d, q)                                          | Doble Sincronizacion de una se�al a traves de dos |
--|                                                                                             | FF. Con reset e inicializacion a '0'.                         |
--+-------------------------------------------------------------------------------------------------+
--|     syncrsld(clk, rst, ld, d, q)                            | Sincronizacion de una se�al a traves de un FF         |
--|                                                                                             | con reset y load.                                                                     |
--+-------------------------------------------------------------------------------------------------+
--|     syncv(size)(clock, d, q)                                        | Sincronizacion de un vector (generic)                         |
--|                                                                                             | con reset y load.                                                                     |
--+-------------------------------------------------------------------------------------------------+
--|     decoder3to8(i, o)                                                       | Decoder 3 to 8                                                                        |
--+-------------------------------------------------------------------------------------------------+
--|     pfs(clk, a, y)                                                          | Pulso a '1' en Flanco de Subida                                       |
--+-------------------------------------------------------------------------------------------------+
--|     pfb(clk, a, y)                                                          | Pulso a '1' en Flanco de bajada                                       |
--+-------------------------------------------------------------------------------------------------+
--+-----------------------------------------------------------------+
--|                                                                                                                             |
--|  Copyright (C) 2005-2008 Peio Azkarate, peio.azkarate@gmail.com     | 
--|                                                                                                                             |
--|  This source file may be used and distributed without               |
--|  restriction provided that this copyright statement is not          |
--|  removed from the file and that any derivative work contains        |
--|  the original copyright notice and the associated disclaimer.       |
--|                                                                     |
--|  This source file is free software; you can redistribute it     |
--|  and/or modify it under the terms of the GNU Lesser General     |
--|  Public License as published by the Free Software Foundation;   |
--|  either version 2.1 of the License, or (at your option) any     |
--|  later version.                                                 |
--|                                                                                                                             |
--|  This source is distributed in the hope that it will be         |
--|  useful, but WITHOUT ANY WARRANTY; without even the implied     |
--|  warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR        |
--|  PURPOSE.  See the GNU Lesser General Public License for more   |
--|  details.                                                       |
--|                                                                                                                             |
--|  You should have received a copy of the GNU Lesser General      |
--|  Public License along with this source; if not, download it     |
--|  from http://www.opencores.org/lgpl.shtml                       |
--|                                                                                                                             |
--+-----------------------------------------------------------------+ 
 
--+-----------------------------------------------------------------------------+
--|                                                     PACKAGE COMPONENTS DECLARATION                                          |
--+-----------------------------------------------------------------------------+
 
library ieee;
use ieee.std_logic_1164.all;
 
package onapackage is
 
        component sync
        port (
 
                clk             : in std_logic;
        d               : in std_logic;
        q               : out std_logic
 
        );
        end component;
 
        component synch
        port (
 
                clk             : in std_logic;
        rst             : in std_logic;
        d               : in std_logic;
        q               : out std_logic
 
        );
        end component;
 
        component syncl
        port (
 
                clk             : in std_logic;
        rst             : in std_logic;
        d               : in std_logic;
        q               : out std_logic
 
        );
        end component;
 
        component sync2
        port (
 
                clk             : in std_logic;
        d               : in std_logic;
        q               : out std_logic
 
        );
        end component;
 
        component sync2h
        port (
 
                clk             : in std_logic;
        rst             : in std_logic;
        d               : in std_logic;
        q               : out std_logic
 
        );
        end component;
 
        component sync2l
        port (
 
                clk             : in std_logic;
        rst             : in std_logic;
        d               : in std_logic;
        q               : out std_logic
 
        );
        end component;
 
        component syncv
        generic ( size: integer := 8 );
        port (
 
                clk             : in std_logic;
        d               : in std_logic_vector(size-1 downto 0);
        q               : out std_logic_vector(size-1 downto 0)
 
        );
        end component;
 
        component syncv2h
        generic ( size: integer := 8 );
        port (
 
                clk             : in std_logic;
        rst             : in std_logic;
        d               : in std_logic_vector(size-1 downto 0);
        q               : out std_logic_vector(size-1 downto 0)
 
        );
        end component;
 
        component decoder3to8
        port (
 
        i               : in std_logic_vector(2 downto 0);
        o               : out std_logic_vector(7 downto 0)
 
        );
        end component;
 
        component pfs
        port (
 
                clk             : in std_logic;
                rst             : in std_logic;
        a               : in std_logic;
        y               : out std_logic
 
        );
        end component;
 
        component pfb
        port (
 
                clk             : in std_logic;
                rst             : in std_logic;
        a               : in std_logic;
        y               : out std_logic
 
        );
        end component;
 
end onapackage;
 
 
 
--+-----------------------------------------------------------------------------+
--|                                                             ENTITY & ARCHITECTURE                                                   |
--+-----------------------------------------------------------------------------+
 
 
--+-----------------------------------------+
--|  sync                                                                       |
--+-----------------------------------------+
 
library ieee;
use ieee.std_logic_1164.all;
 
entity sync is
port (
 
        clk             : in std_logic;
    d           : in std_logic;
        q               : out std_logic
 
);
end sync;
 
architecture rtl of sync is
begin
 
        SYNCP: process( clk, d )
        begin
 
        if ( rising_edge(clk) ) then
                        q <= d;
                end if;
 
        end process SYNCP;
 
end rtl;
 
--+-----------------------------------------+
--|  synch                                                                      |
--+-----------------------------------------+
 
library ieee;
use ieee.std_logic_1164.all;
 
entity synch is
port (
 
        clk             : in std_logic;
        rst             : in std_logic;
    d           : in std_logic;
        q               : out std_logic
 
);
end synch;
 
architecture rtl of synch is
begin
 
        SYNCHP: process( clk, rst, d )
        begin
                if (rst = '1') then
                        q       <= '1';
        elsif ( rising_edge(clk) ) then
                        q <= d;
                end if;
 
        end process SYNCHP;
 
end rtl;
 
--+-----------------------------------------+
--|  syncl                                                                      |
--+-----------------------------------------+
 
library ieee;
use ieee.std_logic_1164.all;
 
entity syncl is
port (
 
        clk             : in std_logic;
        rst             : in std_logic;
    d           : in std_logic;
        q               : out std_logic
 
);
end syncl;
 
architecture rtl of syncl is
begin
 
        SYNCLP: process( clk, rst, d )
        begin
                if (rst = '1') then
                        q       <= '0';
        elsif ( rising_edge(clk) ) then
                        q <= d;
                end if;
 
        end process SYNCLP;
 
end rtl;
 
 
--+-----------------------------------------+
--|  sync2                                                                      |
--+-----------------------------------------+
 
library ieee;
use ieee.std_logic_1164.all;
 
entity sync2 is
        port (
 
                clk             : in std_logic;
        d               : in std_logic;
        q               : out std_logic
 
        );
end sync2;
 
architecture rtl of sync2 is
        signal tmp:     std_logic;
begin
 
        SYNC2P: process ( clk, d, tmp)
        begin
 
        if ( rising_edge(clk) ) then
                tmp <= d;
                q <= tmp;
        end if;
 
        end process SYNC2P;
 
end rtl;
 
--+-----------------------------------------+
--|  sync2h                                                                     |
--+-----------------------------------------+
-- sync2 con inicializacion a '1' con el reset
library ieee;
use ieee.std_logic_1164.all;
 
entity sync2h is
        port (
 
                clk             : in std_logic;
                rst             : in std_logic;
        d               : in std_logic;
        q               : out std_logic
 
        );
end sync2h;
 
architecture rtl of sync2h is
        signal tmp:     std_logic;
begin
 
        SYNC2HP: process ( clk, rst, d, tmp)
        begin
 
                if (rst = '1') then
                        tmp <= '1';
                        q       <= '1';
        elsif ( rising_edge(clk) ) then
                tmp <= d;
                q <= tmp;
        end if;
 
        end process SYNC2HP;
 
end rtl;
 
--+-----------------------------------------+
--|  sync2l                                                                     |
--+-----------------------------------------+
-- sync2 con inicializacion a '0' con el reset
library ieee;
use ieee.std_logic_1164.all;
 
entity sync2l is
        port (
 
                clk             : in std_logic;
                rst             : in std_logic;
        d               : in std_logic;
        q               : out std_logic
 
        );
end sync2l;
 
architecture rtl of sync2l is
        signal tmp:     std_logic;
begin
 
        SYNC2LP: process ( clk, rst, d, tmp)
        begin
 
                if (rst = '1') then
                        tmp <= '0';
                        q       <= '0';
        elsif ( rising_edge(clk) ) then
                tmp <= d;
                q <= tmp;
        end if;
 
        end process SYNC2LP;
 
end rtl;
 
 
 
--+-----------------------------------------+
--|  syncv                                                                      |
--+-----------------------------------------+
 
library ieee;
use ieee.std_logic_1164.all;
 
entity syncv is
generic ( size: integer := 8 );
port (
 
        clk             : in std_logic;
    d           : in std_logic_vector(size-1 downto 0);
        q               : out std_logic_vector(size-1 downto 0)
 
);
end syncv;
 
architecture rtl of syncv is
begin
 
        SYNCVP: process( clk, d )
        begin
 
        if ( rising_edge(clk) ) then
                        q <= d;
                end if;
 
        end process SYNCVP;
 
end rtl;
 
--+-----------------------------------------+
--|  syncv2h                                                            |
--+-----------------------------------------+
 
library ieee;
use ieee.std_logic_1164.all;
 
entity syncv2h is
generic ( size: integer := 8 );
port (
 
        clk             : in std_logic;
        rst             : in std_logic;
    d           : in std_logic_vector(size-1 downto 0);
        q               : out std_logic_vector(size-1 downto 0)
 
);
end syncv2h;
 
architecture rtl of syncv2h is
        signal tmp:     std_logic_vector(size-1 downto 0);
begin
 
        SYNCV2HP: process( clk, d, rst )
        begin
 
                if (rst = '1') then
                        tmp <= (others => '1');
                        q       <= (others => '1');
        elsif ( rising_edge(clk) ) then
                        tmp <= d;
                        q <= tmp;
                end if;
 
        end process SYNCV2HP;
 
end rtl;
 
 
--+-----------------------------------------+
--|  decoder3to8                                                        |
--+-----------------------------------------+
 
library ieee;
use ieee.std_logic_1164.all;
 
entity decoder3to8 is
port (
 
    i           : in std_logic_vector(2 downto 0);
        o               : out std_logic_vector(7 downto 0)
 
);
end decoder3to8;
 
architecture rtl of decoder3to8 is
begin
 
        DECOD3TO8P: process( i )
        begin
 
        if    ( i = "111" ) then o <= "01111111";
                elsif ( i = "110" ) then o <= "10111111";
                elsif ( i = "101" ) then o <= "11011111";
                elsif ( i = "100" ) then o <= "11101111";
                elsif ( i = "011" ) then o <= "11110111";
                elsif ( i = "010" ) then o <= "11111011";
                elsif ( i = "001" ) then o <= "11111101";
                elsif ( i = "000" ) then o <= "11111110";
                else
                        o <= "11111111";
                end if;
 
        end process DECOD3TO8P;
 
end rtl;
 
 
--+-----------------------------------------+
--|  pfs                                                                        |
--+-----------------------------------------+
 
library ieee;
use ieee.std_logic_1164.all;
 
entity pfs is
port (
 
        clk             : in std_logic;
        rst             : in std_logic;
    a           : in std_logic;
        y               : out std_logic
 
);
end pfs;
 
architecture rtl of pfs is
 
        signal a_s      : std_logic;
        signal a_s2     : std_logic;
 
begin
 
        PFSP: process( clk, rst, a )
        begin
 
                if ( rst = '1' ) then
                        a_s  <= '0';
                        a_s2 <= '1';
        elsif ( rising_edge(clk) ) then
                        a_s  <= a;
                        a_s2 <= a_s;
                end if;
 
        end process PFSP;
 
        y <= a_s and (not a_s2);
 
end rtl;
 
--+-----------------------------------------+
--|  pfb                                                                        |
--+-----------------------------------------+
 
library ieee;
use ieee.std_logic_1164.all;
 
entity pfb is
port (
 
        clk             : in std_logic;
        rst             : in std_logic;
    a           : in std_logic;
        y               : out std_logic
 
);
end pfb;
 
architecture rtl of pfb is
 
        signal a_s      : std_logic;
        signal a_s2     : std_logic;
 
begin
 
        PFBP: process( clk, rst, a )
        begin
 
                if ( rst = '1' ) then
                        a_s  <= '1';
                        a_s2 <= '0';
        elsif ( rising_edge(clk) ) then
                        a_s  <= a;
                        a_s2 <= a_s;
                end if;
 
        end process PFBP;
 
        y <= (not a_s) and a_s2;
 
end rtl;
 

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[/] [pci32tlite_oc/] [trunk/] [rtl/] [onalib.vhd] - Blame information for rev 10

Line No.	Rev	Author	Line
1	10	peio	`--+-------------------------------------------------------------------------------------------------+`
2			`--\| \|`
3			`--\| Fileo: onalib.vhd \|`
4			`--\| \|`
5			`--\| Project: onalib \|`
6			`--\| \|`
7			`--\| Description: Libreria de componentes en VHDL. \|`
8			`--\| \|`
9			`--+-------------------------------------------------------------------------------------------------+`
10			`--\| Component \| Descripcion \|`
11			`--+-------------------------------------------------------------------------------------------------+`
12			`--\| sync(clk, d, q) \| Sincronizacion de una se�al a traves de un FF. \|`
13			`--\| \| Sin reset. \|`
14			`--+-------------------------------------------------------------------------------------------------+`
15			`--\| sync2(clk, d, q) \| Doble Sincronizacion de una se�al a traves de dos \|`
16			`--\| \| FF. Sin reset. \|`
17			`--+-------------------------------------------------------------------------------------------------+`
18			`--\| sync2h(clk, rst, d, q) \| Doble Sincronizacion de una se�al a traves de dos \|`
19			`--\| \| FF. Con reset e inicializacion a '1'. \|`
20			`--+-------------------------------------------------------------------------------------------------+`
21			`--\| sync2l(clk, rst, d, q) \| Doble Sincronizacion de una se�al a traves de dos \|`
22			`--\| \| FF. Con reset e inicializacion a '0'. \|`
23			`--+-------------------------------------------------------------------------------------------------+`
24			`--\| syncrsld(clk, rst, ld, d, q) \| Sincronizacion de una se�al a traves de un FF \|`
25			`--\| \| con reset y load. \|`
26			`--+-------------------------------------------------------------------------------------------------+`
27			`--\| syncv(size)(clock, d, q) \| Sincronizacion de un vector (generic) \|`
28			`--\| \| con reset y load. \|`
29			`--+-------------------------------------------------------------------------------------------------+`
30			`--\| decoder3to8(i, o) \| Decoder 3 to 8 \|`
31			`--+-------------------------------------------------------------------------------------------------+`
32			`--\| pfs(clk, a, y) \| Pulso a '1' en Flanco de Subida \|`
33			`--+-------------------------------------------------------------------------------------------------+`
34			`--\| pfb(clk, a, y) \| Pulso a '1' en Flanco de bajada \|`
35			`--+-------------------------------------------------------------------------------------------------+`
36			`--+-----------------------------------------------------------------+`
37			`--\| \|`
38			`--\| Copyright (C) 2005-2008 Peio Azkarate, peio.azkarate@gmail.com \|`
39			`--\| \|`
40			`--\| This source file may be used and distributed without \|`
41			`--\| restriction provided that this copyright statement is not \|`
42			`--\| removed from the file and that any derivative work contains \|`
43			`--\| the original copyright notice and the associated disclaimer. \|`
44			`--\| \|`
45			`--\| This source file is free software; you can redistribute it \|`
46			`--\| and/or modify it under the terms of the GNU Lesser General \|`
47			`--\| Public License as published by the Free Software Foundation; \|`
48			`--\| either version 2.1 of the License, or (at your option) any \|`
49			`--\| later version. \|`
50			`--\| \|`
51			`--\| This source is distributed in the hope that it will be \|`
52			`--\| useful, but WITHOUT ANY WARRANTY; without even the implied \|`
53			`--\| warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR \|`
54			`--\| PURPOSE. See the GNU Lesser General Public License for more \|`
55			`--\| details. \|`
56			`--\| \|`
57			`--\| You should have received a copy of the GNU Lesser General \|`
58			`--\| Public License along with this source; if not, download it \|`
59			`--\| from http://www.opencores.org/lgpl.shtml \|`
60			`--\| \|`
61			`--+-----------------------------------------------------------------+`
62
63			`--+-----------------------------------------------------------------------------+`
64			`--\| PACKAGE COMPONENTS DECLARATION \|`
65			`--+-----------------------------------------------------------------------------+`
66
67			`library ieee;`
68			`use ieee.std_logic_1164.all;`
69
70			`package onapackage is`
71
72			`component sync`
73			`port (`
74
75			`clk : in std_logic;`
76			`d : in std_logic;`
77			`q : out std_logic`
78
79			`);`
80			`end component;`
81
82			`component synch`
83			`port (`
84
85			`clk : in std_logic;`
86			`rst : in std_logic;`
87			`d : in std_logic;`
88			`q : out std_logic`
89
90			`);`
91			`end component;`
92
93			`component syncl`
94			`port (`
95
96			`clk : in std_logic;`
97			`rst : in std_logic;`
98			`d : in std_logic;`
99			`q : out std_logic`
100
101			`);`
102			`end component;`
103
104			`component sync2`
105			`port (`
106
107			`clk : in std_logic;`
108			`d : in std_logic;`
109			`q : out std_logic`
110
111			`);`
112			`end component;`
113
114			`component sync2h`
115			`port (`
116
117			`clk : in std_logic;`
118			`rst : in std_logic;`
119			`d : in std_logic;`
120			`q : out std_logic`
121
122			`);`
123			`end component;`
124
125			`component sync2l`
126			`port (`
127
128			`clk : in std_logic;`
129			`rst : in std_logic;`
130			`d : in std_logic;`
131			`q : out std_logic`
132
133			`);`
134			`end component;`
135
136			`component syncv`
137			`generic ( size: integer := 8 );`
138			`port (`
139
140			`clk : in std_logic;`
141			`d : in std_logic_vector(size-1 downto 0);`
142			`q : out std_logic_vector(size-1 downto 0)`
143
144			`);`
145			`end component;`
146
147			`component syncv2h`
148			`generic ( size: integer := 8 );`
149			`port (`
150
151			`clk : in std_logic;`
152			`rst : in std_logic;`
153			`d : in std_logic_vector(size-1 downto 0);`
154			`q : out std_logic_vector(size-1 downto 0)`
155
156			`);`
157			`end component;`
158
159			`component decoder3to8`
160			`port (`
161
162			`i : in std_logic_vector(2 downto 0);`
163			`o : out std_logic_vector(7 downto 0)`
164
165			`);`
166			`end component;`
167
168			`component pfs`
169			`port (`
170
171			`clk : in std_logic;`
172			`rst : in std_logic;`
173			`a : in std_logic;`
174			`y : out std_logic`
175
176			`);`
177			`end component;`
178
179			`component pfb`
180			`port (`
181
182			`clk : in std_logic;`
183			`rst : in std_logic;`
184			`a : in std_logic;`
185			`y : out std_logic`
186
187			`);`
188			`end component;`
189
190			`end onapackage;`
191
192
193
194			`--+-----------------------------------------------------------------------------+`
195			`--\| ENTITY & ARCHITECTURE \|`
196			`--+-----------------------------------------------------------------------------+`
197
198
199			`--+-----------------------------------------+`
200			`--\| sync \|`
201			`--+-----------------------------------------+`
202
203			`library ieee;`
204			`use ieee.std_logic_1164.all;`
205
206			`entity sync is`
207			`port (`
208
209			`clk : in std_logic;`
210			`d : in std_logic;`
211			`q : out std_logic`
212
213			`);`
214			`end sync;`
215
216			`architecture rtl of sync is`
217			`begin`
218
219			`SYNCP: process( clk, d )`
220			`begin`
221
222			`if ( rising_edge(clk) ) then`
223			`q <= d;`
224			`end if;`
225
226			`end process SYNCP;`
227
228			`end rtl;`
229
230			`--+-----------------------------------------+`
231			`--\| synch \|`
232			`--+-----------------------------------------+`
233
234			`library ieee;`
235			`use ieee.std_logic_1164.all;`
236
237			`entity synch is`
238			`port (`
239
240			`clk : in std_logic;`
241			`rst : in std_logic;`
242			`d : in std_logic;`
243			`q : out std_logic`
244
245			`);`
246			`end synch;`
247
248			`architecture rtl of synch is`
249			`begin`
250
251			`SYNCHP: process( clk, rst, d )`
252			`begin`
253			`if (rst = '1') then`
254			`q <= '1';`
255			`elsif ( rising_edge(clk) ) then`
256			`q <= d;`
257			`end if;`
258
259			`end process SYNCHP;`
260
261			`end rtl;`
262
263			`--+-----------------------------------------+`
264			`--\| syncl \|`
265			`--+-----------------------------------------+`
266
267			`library ieee;`
268			`use ieee.std_logic_1164.all;`
269
270			`entity syncl is`
271			`port (`
272
273			`clk : in std_logic;`
274			`rst : in std_logic;`
275			`d : in std_logic;`
276			`q : out std_logic`
277
278			`);`
279			`end syncl;`
280
281			`architecture rtl of syncl is`
282			`begin`
283
284			`SYNCLP: process( clk, rst, d )`
285			`begin`
286			`if (rst = '1') then`
287			`q <= '0';`
288			`elsif ( rising_edge(clk) ) then`
289			`q <= d;`
290			`end if;`
291
292			`end process SYNCLP;`
293
294			`end rtl;`
295
296
297			`--+-----------------------------------------+`
298			`--\| sync2 \|`
299			`--+-----------------------------------------+`
300
301			`library ieee;`
302			`use ieee.std_logic_1164.all;`
303
304			`entity sync2 is`
305			`port (`
306
307			`clk : in std_logic;`
308			`d : in std_logic;`
309			`q : out std_logic`
310
311			`);`
312			`end sync2;`
313
314			`architecture rtl of sync2 is`
315			`signal tmp: std_logic;`
316			`begin`
317
318			`SYNC2P: process ( clk, d, tmp)`
319			`begin`
320
321			`if ( rising_edge(clk) ) then`
322			`tmp <= d;`
323			`q <= tmp;`
324			`end if;`
325
326			`end process SYNC2P;`
327
328			`end rtl;`
329
330			`--+-----------------------------------------+`
331			`--\| sync2h \|`
332			`--+-----------------------------------------+`
333			`-- sync2 con inicializacion a '1' con el reset`
334			`library ieee;`
335			`use ieee.std_logic_1164.all;`
336
337			`entity sync2h is`
338			`port (`
339
340			`clk : in std_logic;`
341			`rst : in std_logic;`
342			`d : in std_logic;`
343			`q : out std_logic`
344
345			`);`
346			`end sync2h;`
347
348			`architecture rtl of sync2h is`
349			`signal tmp: std_logic;`
350			`begin`
351
352			`SYNC2HP: process ( clk, rst, d, tmp)`
353			`begin`
354
355			`if (rst = '1') then`
356			`tmp <= '1';`
357			`q <= '1';`
358			`elsif ( rising_edge(clk) ) then`
359			`tmp <= d;`
360			`q <= tmp;`
361			`end if;`
362
363			`end process SYNC2HP;`
364
365			`end rtl;`
366
367			`--+-----------------------------------------+`
368			`--\| sync2l \|`
369			`--+-----------------------------------------+`
370			`-- sync2 con inicializacion a '0' con el reset`
371			`library ieee;`
372			`use ieee.std_logic_1164.all;`
373
374			`entity sync2l is`
375			`port (`
376
377			`clk : in std_logic;`
378			`rst : in std_logic;`
379			`d : in std_logic;`
380			`q : out std_logic`
381
382			`);`
383			`end sync2l;`
384
385			`architecture rtl of sync2l is`
386			`signal tmp: std_logic;`
387			`begin`
388
389			`SYNC2LP: process ( clk, rst, d, tmp)`
390			`begin`
391
392			`if (rst = '1') then`
393			`tmp <= '0';`
394			`q <= '0';`
395			`elsif ( rising_edge(clk) ) then`
396			`tmp <= d;`
397			`q <= tmp;`
398			`end if;`
399
400			`end process SYNC2LP;`
401
402			`end rtl;`
403
404
405
406			`--+-----------------------------------------+`
407			`--\| syncv \|`
408			`--+-----------------------------------------+`
409
410			`library ieee;`
411			`use ieee.std_logic_1164.all;`
412
413			`entity syncv is`
414			`generic ( size: integer := 8 );`
415			`port (`
416
417			`clk : in std_logic;`
418			`d : in std_logic_vector(size-1 downto 0);`
419			`q : out std_logic_vector(size-1 downto 0)`
420
421			`);`
422			`end syncv;`
423
424			`architecture rtl of syncv is`
425			`begin`
426
427			`SYNCVP: process( clk, d )`
428			`begin`
429
430			`if ( rising_edge(clk) ) then`
431			`q <= d;`
432			`end if;`
433
434			`end process SYNCVP;`
435
436			`end rtl;`
437
438			`--+-----------------------------------------+`
439			`--\| syncv2h \|`
440			`--+-----------------------------------------+`
441
442			`library ieee;`
443			`use ieee.std_logic_1164.all;`
444
445			`entity syncv2h is`
446			`generic ( size: integer := 8 );`
447			`port (`
448
449			`clk : in std_logic;`
450			`rst : in std_logic;`
451			`d : in std_logic_vector(size-1 downto 0);`
452			`q : out std_logic_vector(size-1 downto 0)`
453
454			`);`
455			`end syncv2h;`
456
457			`architecture rtl of syncv2h is`
458			`signal tmp: std_logic_vector(size-1 downto 0);`
459			`begin`
460
461			`SYNCV2HP: process( clk, d, rst )`
462			`begin`
463
464			`if (rst = '1') then`
465			`tmp <= (others => '1');`
466			`q <= (others => '1');`
467			`elsif ( rising_edge(clk) ) then`
468			`tmp <= d;`
469			`q <= tmp;`
470			`end if;`
471
472			`end process SYNCV2HP;`
473
474			`end rtl;`
475
476
477			`--+-----------------------------------------+`
478			`--\| decoder3to8 \|`
479			`--+-----------------------------------------+`
480
481			`library ieee;`
482			`use ieee.std_logic_1164.all;`
483
484			`entity decoder3to8 is`
485			`port (`
486
487			`i : in std_logic_vector(2 downto 0);`
488			`o : out std_logic_vector(7 downto 0)`
489
490			`);`
491			`end decoder3to8;`
492
493			`architecture rtl of decoder3to8 is`
494			`begin`
495
496			`DECOD3TO8P: process( i )`
497			`begin`
498
499			`if ( i = "111" ) then o <= "01111111";`
500			`elsif ( i = "110" ) then o <= "10111111";`
501			`elsif ( i = "101" ) then o <= "11011111";`
502			`elsif ( i = "100" ) then o <= "11101111";`
503			`elsif ( i = "011" ) then o <= "11110111";`
504			`elsif ( i = "010" ) then o <= "11111011";`
505			`elsif ( i = "001" ) then o <= "11111101";`
506			`elsif ( i = "000" ) then o <= "11111110";`
507			`else`
508			`o <= "11111111";`
509			`end if;`
510
511			`end process DECOD3TO8P;`
512
513			`end rtl;`
514
515
516			`--+-----------------------------------------+`
517			`--\| pfs \|`
518			`--+-----------------------------------------+`
519
520			`library ieee;`
521			`use ieee.std_logic_1164.all;`
522
523			`entity pfs is`
524			`port (`
525
526			`clk : in std_logic;`
527			`rst : in std_logic;`
528			`a : in std_logic;`
529			`y : out std_logic`
530
531			`);`
532			`end pfs;`
533
534			`architecture rtl of pfs is`
535
536			`signal a_s : std_logic;`
537			`signal a_s2 : std_logic;`
538
539			`begin`
540
541			`PFSP: process( clk, rst, a )`
542			`begin`
543
544			`if ( rst = '1' ) then`
545			`a_s <= '0';`
546			`a_s2 <= '1';`
547			`elsif ( rising_edge(clk) ) then`
548			`a_s <= a;`
549			`a_s2 <= a_s;`
550			`end if;`
551
552			`end process PFSP;`
553
554			`y <= a_s and (not a_s2);`
555
556			`end rtl;`
557
558			`--+-----------------------------------------+`
559			`--\| pfb \|`
560			`--+-----------------------------------------+`
561
562			`library ieee;`
563			`use ieee.std_logic_1164.all;`
564
565			`entity pfb is`
566			`port (`
567
568			`clk : in std_logic;`
569			`rst : in std_logic;`
570			`a : in std_logic;`
571			`y : out std_logic`
572
573			`);`
574			`end pfb;`
575
576			`architecture rtl of pfb is`
577
578			`signal a_s : std_logic;`
579			`signal a_s2 : std_logic;`
580
581			`begin`
582
583			`PFBP: process( clk, rst, a )`
584			`begin`
585
586			`if ( rst = '1' ) then`
587			`a_s <= '1';`
588			`a_s2 <= '0';`
589			`elsif ( rising_edge(clk) ) then`
590			`a_s <= a;`
591			`a_s2 <= a_s;`
592			`end if;`
593
594			`end process PFBP;`
595
596			`y <= (not a_s) and a_s2;`
597
598			`end rtl;`
599