1 |
10 |
peio |
--+-------------------------------------------------------------------------------------------------+
|
2 |
|
|
--| |
|
3 |
|
|
--| File: pci32tLite.vhd |
|
4 |
|
|
--| |
|
5 |
|
|
--| Components: pcidec.vhd |
|
6 |
|
|
--| pciwbsequ.vhd |
|
7 |
|
|
--| pcidmux.vhd |
|
8 |
|
|
--| pciregs.vhd |
|
9 |
|
|
--| pcipargen.vhd |
|
10 |
|
|
--| ona.vhd |
|
11 |
|
|
--| |
|
12 |
|
|
--+-------------------------------------------------------------------------------------------------+
|
13 |
|
|
--| |
|
14 |
|
|
--| Revision history : |
|
15 |
|
|
--| Date Version Author Description |
|
16 |
|
|
--| 2005-05-13 R00A00 PAU First alfa revision |
|
17 |
|
|
--| |
|
18 |
|
|
--| 2006-11-27 R01 PAU * BUG fast back-to-back transactions |
|
19 |
|
|
--| * TIMEOUT: Target termination with RETRY |
|
20 |
|
|
--| 2007-09-19 R02 PAU * "intb" and "serr" signals not defined as TRI. They have to be |
|
21 |
|
|
--| defined Opendrain in the FPGA (externally to the IP Core). |
|
22 |
|
|
--| * Small changes due to onalib.vhd improvement. |
|
23 |
|
|
--| * Removed TIMEOUT. Added wb_rty_i for Target termination with |
|
24 |
|
|
--| RETRY. |
|
25 |
|
|
--| * Support Burst Cicles. |
|
26 |
|
|
--| * Add Whisbone data bus configuration generics: WBSIZE and |
|
27 |
|
|
--| WBENDIAN. |
|
28 |
|
|
--| * Add wb_adr_o(1..0) signals. |
|
29 |
|
|
--| * wb_dat_i,wb_dat_o,wb_sel_o size depends on WBSIZE. |
|
30 |
|
|
--| * Advice: Change WB <-> PCI databus routing for "BIG"/16 WB |
|
31 |
|
|
--| configuration and DWORD PCI transactions (DWORD is not |
|
32 |
|
|
--| recomended when WB 16 configuration). |
|
33 |
|
|
--| 2008-06-16 R03 PAU * Add "1BARIO" configuration option for BARS generic. |
|
34 |
|
|
--| * fix bug with WBENDIAN generic in pciwbsequ. |
|
35 |
|
|
--| * Change PCI Burts to WB traslation behavior. |
|
36 |
|
|
--| * Add "classcode" generic. |
|
37 |
|
|
--| * Change BAR0 reset state to "0". |
|
38 |
|
|
--| * Fix pcidmux bug for LITTLE/8 configuration. |
|
39 |
|
|
--| 2022-01-10 v3.1 Peio Azkarate |
|
40 |
|
|
--| * Project changes, Not rtl changes. |
|
41 |
|
|
--+-------------------------------------------------------------------------------------------------+
|
42 |
|
|
--+-----------------------------------------------------------------+
|
43 |
|
|
--| |
|
44 |
|
|
--| Copyright (C) 2005-2008 Peio Azkarate, peio.azkarate@gmail.com |
|
45 |
|
|
--| |
|
46 |
|
|
--| This source file may be used and distributed without |
|
47 |
|
|
--| restriction provided that this copyright statement is not |
|
48 |
|
|
--| removed from the file and that any derivative work contains |
|
49 |
|
|
--| the original copyright notice and the associated disclaimer. |
|
50 |
|
|
--| |
|
51 |
|
|
--| This source file is free software; you can redistribute it |
|
52 |
|
|
--| and/or modify it under the terms of the GNU Lesser General |
|
53 |
|
|
--| Public License as published by the Free Software Foundation; |
|
54 |
|
|
--| either version 2.1 of the License, or (at your option) any |
|
55 |
|
|
--| later version. |
|
56 |
|
|
--| |
|
57 |
|
|
--| This source is distributed in the hope that it will be |
|
58 |
|
|
--| useful, but WITHOUT ANY WARRANTY; without even the implied |
|
59 |
|
|
--| warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR |
|
60 |
|
|
--| PURPOSE. See the GNU Lesser General Public License for more |
|
61 |
|
|
--| details. |
|
62 |
|
|
--| |
|
63 |
|
|
--| You should have received a copy of the GNU Lesser General |
|
64 |
|
|
--| Public License along with this source; if not, download it |
|
65 |
|
|
--| from http://www.opencores.org/lgpl.shtml |
|
66 |
|
|
--| |
|
67 |
|
|
--+-----------------------------------------------------------------+
|
68 |
|
|
|
69 |
|
|
--+-----------------------------------------------------------------------------+
|
70 |
|
|
--| LIBRARIES |
|
71 |
|
|
--+-----------------------------------------------------------------------------+
|
72 |
|
|
|
73 |
|
|
library ieee;
|
74 |
|
|
use ieee.std_logic_1164.all;
|
75 |
|
|
|
76 |
|
|
--+-----------------------------------------------------------------------------+
|
77 |
|
|
--| ENTITY |
|
78 |
|
|
--+-----------------------------------------------------------------------------+
|
79 |
|
|
entity pci32tLite is
|
80 |
|
|
generic (
|
81 |
|
|
vendorID : std_logic_vector(15 downto 0) := x"4150";
|
82 |
|
|
deviceID : std_logic_vector(15 downto 0) := x"0001";
|
83 |
|
|
revisionID : std_logic_vector(7 downto 0) := x"90";
|
84 |
|
|
subsystemID : std_logic_vector(15 downto 0) := x"0000";
|
85 |
|
|
subsystemvID : std_logic_vector(15 downto 0) := x"1172";
|
86 |
|
|
classcodeID : std_logic_vector(23 downto 0) := x"068000";
|
87 |
|
|
-- BAR&WB_CFG (dont delete)
|
88 |
|
|
BARS : string := "1BARMEM";
|
89 |
|
|
WBSIZE : integer := 16;
|
90 |
|
|
WBENDIAN : string := "BIG"
|
91 |
|
|
);
|
92 |
|
|
port (
|
93 |
|
|
-- General
|
94 |
|
|
clk33 : in std_logic;
|
95 |
|
|
rst : in std_logic;
|
96 |
|
|
|
97 |
|
|
-- PCI target 32bits
|
98 |
|
|
ad : inout std_logic_vector(31 downto 0);
|
99 |
|
|
cbe : in std_logic_vector(3 downto 0);
|
100 |
|
|
par : out std_logic;
|
101 |
|
|
frame : in std_logic;
|
102 |
|
|
irdy : in std_logic;
|
103 |
|
|
trdy : out std_logic;
|
104 |
|
|
devsel : out std_logic;
|
105 |
|
|
stop : out std_logic;
|
106 |
|
|
idsel : in std_logic;
|
107 |
|
|
perr : out std_logic;
|
108 |
|
|
serr : out std_logic;
|
109 |
|
|
intb : out std_logic;
|
110 |
|
|
|
111 |
|
|
-- Master whisbone
|
112 |
|
|
wb_adr_o : out std_logic_vector(24 downto 0);
|
113 |
|
|
wb_dat_i : in std_logic_vector(WBSIZE-1 downto 0);
|
114 |
|
|
wb_dat_o : out std_logic_vector(WBSIZE-1 downto 0);
|
115 |
|
|
wb_sel_o : out std_logic_vector(((WBSIZE/8)-1) downto 0);
|
116 |
|
|
wb_we_o : out std_logic;
|
117 |
|
|
wb_stb_o : out std_logic;
|
118 |
|
|
wb_cyc_o : out std_logic;
|
119 |
|
|
wb_ack_i : in std_logic;
|
120 |
|
|
wb_rty_i : in std_logic;
|
121 |
|
|
wb_err_i : in std_logic;
|
122 |
|
|
wb_int_i : in std_logic
|
123 |
|
|
|
124 |
|
|
);
|
125 |
|
|
end pci32tLite;
|
126 |
|
|
|
127 |
|
|
|
128 |
|
|
--+-----------------------------------------------------------------------------+
|
129 |
|
|
--| ARCHITECTURE |
|
130 |
|
|
--+-----------------------------------------------------------------------------+
|
131 |
|
|
|
132 |
|
|
architecture rtl of pci32tLite is
|
133 |
|
|
|
134 |
|
|
--+-----------------------------------------------------------------------------+
|
135 |
|
|
--| COMPONENTS |
|
136 |
|
|
--+-----------------------------------------------------------------------------+
|
137 |
|
|
|
138 |
|
|
component pcidec
|
139 |
|
|
generic (
|
140 |
|
|
BARS : string := "1BARMEM"
|
141 |
|
|
);
|
142 |
|
|
port (
|
143 |
|
|
clk_i : in std_logic;
|
144 |
|
|
rst_i : in std_logic;
|
145 |
|
|
--
|
146 |
|
|
ad_i : in std_logic_vector(31 downto 0);
|
147 |
|
|
cbe_i : in std_logic_vector(3 downto 0);
|
148 |
|
|
idsel_i : in std_logic;
|
149 |
|
|
bar0_i : in std_logic_vector(31 downto 9);
|
150 |
|
|
memEN_i : in std_logic;
|
151 |
|
|
ioEN_i : in std_logic;
|
152 |
|
|
pciadrLD_i : in std_logic;
|
153 |
|
|
adrcfg_o : out std_logic;
|
154 |
|
|
adrmem_o : out std_logic;
|
155 |
|
|
adr_o : out std_logic_vector(24 downto 0);
|
156 |
|
|
cmd_o : out std_logic_vector(3 downto 0)
|
157 |
|
|
);
|
158 |
|
|
end component;
|
159 |
|
|
|
160 |
|
|
|
161 |
|
|
component pciwbsequ
|
162 |
|
|
generic (
|
163 |
|
|
BARS : string := "1BARMEM";
|
164 |
|
|
WBSIZE : integer := 16;
|
165 |
|
|
WBENDIAN : string := "BIG"
|
166 |
|
|
);
|
167 |
|
|
port (
|
168 |
|
|
-- General
|
169 |
|
|
clk_i : in std_logic;
|
170 |
|
|
rst_i : in std_logic;
|
171 |
|
|
-- pci
|
172 |
|
|
cmd_i : in std_logic_vector(3 downto 0);
|
173 |
|
|
cbe_i : in std_logic_vector(3 downto 0);
|
174 |
|
|
frame_i : in std_logic;
|
175 |
|
|
irdy_i : in std_logic;
|
176 |
|
|
devsel_o : out std_logic;
|
177 |
|
|
trdy_o : out std_logic;
|
178 |
|
|
stop_o : out std_logic;
|
179 |
|
|
-- control
|
180 |
|
|
adrcfg_i : in std_logic;
|
181 |
|
|
adrmem_i : in std_logic;
|
182 |
|
|
pciadrLD_o : out std_logic;
|
183 |
|
|
pcidOE_o : out std_logic;
|
184 |
|
|
parOE_o : out std_logic;
|
185 |
|
|
wbdatLD_o : out std_logic;
|
186 |
|
|
wrcfg_o : out std_logic;
|
187 |
|
|
rdcfg_o : out std_logic;
|
188 |
|
|
-- whisbone
|
189 |
|
|
wb_sel_o : out std_logic_vector(((WBSIZE/8)-1) downto 0);
|
190 |
|
|
wb_we_o : out std_logic;
|
191 |
|
|
wb_stb_o : out std_logic;
|
192 |
|
|
wb_cyc_o : out std_logic;
|
193 |
|
|
wb_ack_i : in std_logic;
|
194 |
|
|
wb_rty_i : in std_logic;
|
195 |
|
|
wb_err_i : in std_logic
|
196 |
|
|
);
|
197 |
|
|
end component;
|
198 |
|
|
|
199 |
|
|
|
200 |
|
|
component pcidmux
|
201 |
|
|
generic (
|
202 |
|
|
BARS : string := "1BARMEM";
|
203 |
|
|
WBSIZE : integer := 16;
|
204 |
|
|
WBENDIAN : string := "BIG"
|
205 |
|
|
);
|
206 |
|
|
port (
|
207 |
|
|
clk_i : in std_logic;
|
208 |
|
|
rst_i : in std_logic;
|
209 |
|
|
--
|
210 |
|
|
d_io : inout std_logic_vector(31 downto 0);
|
211 |
|
|
pcidatout_o : out std_logic_vector(31 downto 0);
|
212 |
|
|
pcidOE_i : in std_logic;
|
213 |
|
|
wbdatLD_i : in std_logic;
|
214 |
|
|
rdcfg_i : in std_logic;
|
215 |
|
|
cbe_i : in std_logic_vector(3 downto 0);
|
216 |
|
|
wb_dat_i : in std_logic_vector((WBSIZE-1) downto 0);
|
217 |
|
|
wb_dat_o : out std_logic_vector((WBSIZE-1) downto 0);
|
218 |
|
|
rg_dat_i : in std_logic_vector(31 downto 0);
|
219 |
|
|
rg_dat_o : out std_logic_vector(31 downto 0)
|
220 |
|
|
);
|
221 |
|
|
end component;
|
222 |
|
|
|
223 |
|
|
|
224 |
|
|
component pciregs
|
225 |
|
|
generic (
|
226 |
|
|
vendorID : std_logic_vector(15 downto 0);
|
227 |
|
|
deviceID : std_logic_vector(15 downto 0);
|
228 |
|
|
revisionID : std_logic_vector(7 downto 0);
|
229 |
|
|
subsystemID : std_logic_vector(15 downto 0);
|
230 |
|
|
subsystemvID : std_logic_vector(15 downto 0);
|
231 |
|
|
classcodeID : std_logic_vector(23 downto 0);
|
232 |
|
|
BARS : string := "1BARMEM"
|
233 |
|
|
);
|
234 |
|
|
port (
|
235 |
|
|
clk_i : in std_logic;
|
236 |
|
|
rst_i : in std_logic;
|
237 |
|
|
--
|
238 |
|
|
adr_i : in std_logic_vector(7 downto 2);
|
239 |
|
|
cbe_i : in std_logic_vector(3 downto 0);
|
240 |
|
|
dat_i : in std_logic_vector(31 downto 0);
|
241 |
|
|
dat_o : out std_logic_vector(31 downto 0);
|
242 |
|
|
wrcfg_i : in std_logic;
|
243 |
|
|
rdcfg_i : in std_logic;
|
244 |
|
|
perr_i : in std_logic;
|
245 |
|
|
serr_i : in std_logic;
|
246 |
|
|
tabort_i : in std_logic;
|
247 |
|
|
bar0_o : out std_logic_vector(31 downto 9);
|
248 |
|
|
perrEN_o : out std_logic;
|
249 |
|
|
serrEN_o : out std_logic;
|
250 |
|
|
memEN_o : out std_logic;
|
251 |
|
|
ioEN_o : out std_logic
|
252 |
|
|
);
|
253 |
|
|
end component;
|
254 |
|
|
|
255 |
|
|
|
256 |
|
|
component pcipargen
|
257 |
|
|
port (
|
258 |
|
|
|
259 |
|
|
clk_i : in std_logic;
|
260 |
|
|
pcidatout_i : in std_logic_vector(31 downto 0);
|
261 |
|
|
cbe_i : in std_logic_vector(3 downto 0);
|
262 |
|
|
parOE_i : in std_logic;
|
263 |
|
|
par_o : out std_logic
|
264 |
|
|
|
265 |
|
|
);
|
266 |
|
|
end component;
|
267 |
|
|
|
268 |
|
|
|
269 |
|
|
--+-----------------------------------------------------------------------------+
|
270 |
|
|
--| CONSTANTS |
|
271 |
|
|
--+-----------------------------------------------------------------------------+
|
272 |
|
|
--+-----------------------------------------------------------------------------+
|
273 |
|
|
--| SIGNALS |
|
274 |
|
|
--+-----------------------------------------------------------------------------+
|
275 |
|
|
|
276 |
|
|
signal bar0 : std_logic_vector(31 downto 9);
|
277 |
|
|
signal memEN : std_logic;
|
278 |
|
|
signal ioEN : std_logic;
|
279 |
|
|
signal pciadrLD : std_logic;
|
280 |
|
|
signal adrcfg : std_logic;
|
281 |
|
|
signal adrmem : std_logic;
|
282 |
|
|
signal adr : std_logic_vector(24 downto 0);
|
283 |
|
|
signal cmd : std_logic_vector(3 downto 0);
|
284 |
|
|
signal pcidOE : std_logic;
|
285 |
|
|
signal parOE : std_logic;
|
286 |
|
|
signal wbdatLD : std_logic;
|
287 |
|
|
signal wrcfg : std_logic;
|
288 |
|
|
signal rdcfg : std_logic;
|
289 |
|
|
signal pcidatread : std_logic_vector(31 downto 0);
|
290 |
|
|
signal pcidatwrite : std_logic_vector(31 downto 0);
|
291 |
|
|
signal pcidatout : std_logic_vector(31 downto 0);
|
292 |
|
|
signal parerr : std_logic;
|
293 |
|
|
signal syserr : std_logic;
|
294 |
|
|
signal tabort : std_logic;
|
295 |
|
|
signal perrEN : std_logic;
|
296 |
|
|
signal serrEN : std_logic;
|
297 |
|
|
|
298 |
|
|
begin
|
299 |
|
|
-- ASSERT
|
300 |
|
|
assert (BARS = "1BARMEM" or BARS = "1BARIO")
|
301 |
|
|
report "ERROR : Bad BAR configuration"
|
302 |
|
|
severity Failure;
|
303 |
|
|
assert ((WBSIZE = 32 and WBENDIAN = "LITTLE") or (WBSIZE = 16) or (WBSIZE = 8 and WBENDIAN = "LITTLE"))
|
304 |
|
|
report "ERROR : Bad WBSIZE/WBENDIAN configuration"
|
305 |
|
|
severity Failure;
|
306 |
|
|
|
307 |
|
|
--+-------------------------------------------------------------------------+
|
308 |
|
|
--| Component instances |
|
309 |
|
|
--+-------------------------------------------------------------------------+
|
310 |
|
|
|
311 |
|
|
--+-----------------------------------------+
|
312 |
|
|
--| PCI decoder |
|
313 |
|
|
--+-----------------------------------------+
|
314 |
|
|
u1: component pcidec
|
315 |
|
|
generic map (
|
316 |
|
|
BARS => BARS
|
317 |
|
|
)
|
318 |
|
|
port map (
|
319 |
|
|
|
320 |
|
|
clk_i => clk33,
|
321 |
|
|
rst_i => rst,
|
322 |
|
|
--
|
323 |
|
|
ad_i => ad,
|
324 |
|
|
cbe_i => cbe,
|
325 |
|
|
idsel_i => idsel,
|
326 |
|
|
bar0_i => bar0,
|
327 |
|
|
memEN_i => memEN,
|
328 |
|
|
ioEN_i => ioEN,
|
329 |
|
|
pciadrLD_i => pciadrLD,
|
330 |
|
|
adrcfg_o => adrcfg,
|
331 |
|
|
adrmem_o => adrmem,
|
332 |
|
|
adr_o => adr,
|
333 |
|
|
cmd_o => cmd
|
334 |
|
|
);
|
335 |
|
|
|
336 |
|
|
|
337 |
|
|
--+-----------------------------------------+
|
338 |
|
|
--| PCI-WB Sequencer |
|
339 |
|
|
--+-----------------------------------------+
|
340 |
|
|
u2: component pciwbsequ
|
341 |
|
|
generic map (
|
342 |
|
|
BARS => BARS,
|
343 |
|
|
WBSIZE => WBSIZE,
|
344 |
|
|
WBENDIAN => WBENDIAN
|
345 |
|
|
)
|
346 |
|
|
port map (
|
347 |
|
|
-- General
|
348 |
|
|
clk_i => clk33,
|
349 |
|
|
rst_i => rst,
|
350 |
|
|
-- pci
|
351 |
|
|
cmd_i => cmd,
|
352 |
|
|
cbe_i => cbe,
|
353 |
|
|
frame_i => frame,
|
354 |
|
|
irdy_i => irdy,
|
355 |
|
|
devsel_o => devsel,
|
356 |
|
|
trdy_o => trdy,
|
357 |
|
|
stop_o => stop,
|
358 |
|
|
-- control
|
359 |
|
|
adrcfg_i => adrcfg,
|
360 |
|
|
adrmem_i => adrmem,
|
361 |
|
|
pciadrLD_o => pciadrLD,
|
362 |
|
|
pcidOE_o => pcidOE,
|
363 |
|
|
parOE_o => parOE,
|
364 |
|
|
wbdatLD_o => wbdatLD,
|
365 |
|
|
wrcfg_o => wrcfg,
|
366 |
|
|
rdcfg_o => rdcfg,
|
367 |
|
|
-- whisbone
|
368 |
|
|
wb_sel_o => wb_sel_o(((WBSIZE/8)-1) downto 0),
|
369 |
|
|
wb_we_o => wb_we_o,
|
370 |
|
|
wb_stb_o => wb_stb_o,
|
371 |
|
|
wb_cyc_o => wb_cyc_o,
|
372 |
|
|
wb_ack_i => wb_ack_i,
|
373 |
|
|
wb_rty_i => wb_rty_i,
|
374 |
|
|
wb_err_i => wb_err_i
|
375 |
|
|
);
|
376 |
|
|
|
377 |
|
|
|
378 |
|
|
--+-----------------------------------------+
|
379 |
|
|
--| PCI-wb datamultiplexer |
|
380 |
|
|
--+-----------------------------------------+
|
381 |
|
|
u3: component pcidmux
|
382 |
|
|
generic map (
|
383 |
|
|
BARS => BARS,
|
384 |
|
|
WBSIZE => WBSIZE,
|
385 |
|
|
WBENDIAN => WBENDIAN
|
386 |
|
|
)
|
387 |
|
|
port map (
|
388 |
|
|
clk_i => clk33,
|
389 |
|
|
rst_i => rst,
|
390 |
|
|
--
|
391 |
|
|
d_io => ad,
|
392 |
|
|
pcidatout_o => pcidatout,
|
393 |
|
|
pcidOE_i => pcidOE,
|
394 |
|
|
wbdatLD_i => wbdatLD,
|
395 |
|
|
rdcfg_i => rdcfg,
|
396 |
|
|
cbe_i => cbe,
|
397 |
|
|
wb_dat_i => wb_dat_i((WBSIZE-1) downto 0),
|
398 |
|
|
wb_dat_o => wb_dat_o((WBSIZE-1) downto 0),
|
399 |
|
|
rg_dat_i => pcidatread,
|
400 |
|
|
rg_dat_o => pcidatwrite
|
401 |
|
|
);
|
402 |
|
|
|
403 |
|
|
|
404 |
|
|
--+-----------------------------------------+
|
405 |
|
|
--| PCI registers |
|
406 |
|
|
--+-----------------------------------------+
|
407 |
|
|
u4: component pciregs
|
408 |
|
|
generic map (
|
409 |
|
|
vendorID => vendorID,
|
410 |
|
|
deviceID => deviceID,
|
411 |
|
|
revisionID => revisionID,
|
412 |
|
|
subsystemID => subsystemID,
|
413 |
|
|
subsystemvID => subsystemvID,
|
414 |
|
|
classcodeID => classcodeID,
|
415 |
|
|
BARS => BARS
|
416 |
|
|
)
|
417 |
|
|
port map (
|
418 |
|
|
clk_i => clk33,
|
419 |
|
|
rst_i => rst,
|
420 |
|
|
--
|
421 |
|
|
adr_i => adr(7 downto 2),
|
422 |
|
|
cbe_i => cbe,
|
423 |
|
|
dat_i => pcidatwrite,
|
424 |
|
|
dat_o => pcidatread,
|
425 |
|
|
wrcfg_i => wrcfg,
|
426 |
|
|
rdcfg_i => rdcfg,
|
427 |
|
|
perr_i => parerr,
|
428 |
|
|
serr_i => syserr,
|
429 |
|
|
tabort_i => tabort,
|
430 |
|
|
bar0_o => bar0,
|
431 |
|
|
perrEN_o => perrEN,
|
432 |
|
|
serrEN_o => serrEN,
|
433 |
|
|
memEN_o => memEN,
|
434 |
|
|
ioEN_o => ioEN
|
435 |
|
|
|
436 |
|
|
);
|
437 |
|
|
|
438 |
|
|
--+-----------------------------------------+
|
439 |
|
|
--| PCI Parity Gnerator |
|
440 |
|
|
--+-----------------------------------------+
|
441 |
|
|
u5: component pcipargen
|
442 |
|
|
port map (
|
443 |
|
|
clk_i => clk33,
|
444 |
|
|
pcidatout_i => pcidatout,
|
445 |
|
|
cbe_i => cbe,
|
446 |
|
|
parOE_i => parOE,
|
447 |
|
|
par_o => par
|
448 |
|
|
);
|
449 |
|
|
|
450 |
|
|
--+-----------------------------------------+
|
451 |
|
|
--| Whisbone Address bus |
|
452 |
|
|
--+-----------------------------------------+
|
453 |
|
|
wb_adr_o <= adr;
|
454 |
|
|
|
455 |
|
|
--+-----------------------------------------+
|
456 |
|
|
--| unimplemented |
|
457 |
|
|
--+-----------------------------------------+
|
458 |
|
|
parerr <= '0';
|
459 |
|
|
syserr <= '0';
|
460 |
|
|
tabort <= '0';
|
461 |
|
|
|
462 |
|
|
--+-----------------------------------------+
|
463 |
|
|
--| unused outputs |
|
464 |
|
|
--+-----------------------------------------+
|
465 |
|
|
-- El pin de interrupcion "serr" debe ser OPENDRAIN.
|
466 |
|
|
-- Definirlo as� en la FPGA.
|
467 |
|
|
-- #perr:
|
468 |
|
|
-- #serr:
|
469 |
|
|
perr <= 'Z';
|
470 |
|
|
--serr <= 'Z';
|
471 |
|
|
serr <= '1';
|
472 |
|
|
|
473 |
|
|
--+-----------------------------------------+
|
474 |
|
|
--| Interrupt |
|
475 |
|
|
--+-----------------------------------------+
|
476 |
|
|
-- El pin de interrupcion "intb" debe ser OPENDRAIN.
|
477 |
|
|
-- Definirlo as� en la FPGA.
|
478 |
|
|
--intb <= '0' when ( wb_int_i = '1' ) else 'Z';
|
479 |
|
|
intb <= not wb_int_i;
|
480 |
|
|
|
481 |
|
|
end rtl;
|