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peio |
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--| File: pcipargen.vhd |
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--| Project: pci32tLite |
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--| Description: PCI Parity Generator. |
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--+-----------------------------------------------------------------+
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--| |
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--| Copyright (C) 2005-2008 Peio Azkarate, peio.azkarate@gmail.com |
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--| This source file may be used and distributed without |
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--| restriction provided that this copyright statement is not |
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--| removed from the file and that any derivative work contains |
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--| the original copyright notice and the associated disclaimer. |
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--| |
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--| This source file is free software; you can redistribute it |
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--| and/or modify it under the terms of the GNU Lesser General |
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--| Public License as published by the Free Software Foundation; |
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--| either version 2.1 of the License, or (at your option) any |
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--| later version. |
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--| |
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--| This source is distributed in the hope that it will be |
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--| useful, but WITHOUT ANY WARRANTY; without even the implied |
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--| warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR |
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--| PURPOSE. See the GNU Lesser General Public License for more |
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--| details. |
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--| |
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--| You should have received a copy of the GNU Lesser General |
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--| Public License along with this source; if not, download it |
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--| from http://www.opencores.org/lgpl.shtml |
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--| |
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--+-----------------------------------------------------------------+
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--+-----------------------------------------------------------------------------+
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--| LIBRARIES |
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--+-----------------------------------------------------------------------------+
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library ieee;
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use ieee.std_logic_1164.all;
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library onalib;
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use onalib.onapackage.all;
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--+-----------------------------------------------------------------------------+
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--| ENTITY |
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--+-----------------------------------------------------------------------------+
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entity pcipargen is
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port (
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clk_i : in std_logic;
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pcidatout_i : in std_logic_vector(31 downto 0);
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cbe_i : in std_logic_vector(3 downto 0);
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parOE_i : in std_logic;
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par_o : out std_logic
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);
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end pcipargen;
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architecture rtl of pcipargen is
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--+-----------------------------------------------------------------------------+
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--| COMPONENTS |
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--+-----------------------------------------------------------------------------+
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--+-----------------------------------------------------------------------------+
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--| CONSTANTS |
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--+-----------------------------------------------------------------------------+
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--+-----------------------------------------------------------------------------+
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--| SIGNALS |
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--+-----------------------------------------------------------------------------+
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signal d : std_logic_vector(31 downto 0);
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signal pardat : std_logic;
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signal parcbe : std_logic;
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signal par : std_logic;
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signal par_s : std_logic;
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begin
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d <= pcidatout_i;
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--+-------------------------------------------------------------------------+
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--| building parity |
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--+-------------------------------------------------------------------------+
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pardat <= d(0) xor d(1) xor d(2) xor d(3) xor d(4) xor d(5) xor d(6) xor d(7) xor
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d(8) xor d(9) xor d(10) xor d(11) xor d(12) xor d(13) xor d(14) xor d(15) xor
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d(16) xor d(17) xor d(18) xor d(19) xor d(20) xor d(21) xor d(22) xor d(23) xor
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d(24) xor d(25) xor d(26) xor d(27) xor d(28) xor d(29) xor d(30) xor d(31);
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parcbe <= cbe_i(0) xor cbe_i(1) xor cbe_i(2) xor cbe_i(3);
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par <= pardat xor parcbe;
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u1: sync port map ( clk => clk_i, d => par, q => par_s );
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--+-------------------------------------------------------------------------+
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--| PAR |
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--+-------------------------------------------------------------------------+
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par_o <= par_s when ( parOE_i = '1' ) else 'Z';
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end rtl;
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