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olupas |
--===================================================================--
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--
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-- www.OpenCores.Org - January 2000
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-- This model adheres to the GNU public license
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--
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-- Design units : TestBench for PCI devices.
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--
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-- File name : Test_PCI.vhd
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--
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-- Purpose : Implements the test bench for PCI 33 MHz, 32 bit devices.
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-- It is included one master device and two target devices.
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--
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-- There can be used more than one target devices in a
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-- design, every device being identified by the three
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-- base addresses in generic.
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--
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--
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-- Library : PCI_Lib
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--
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-- Dependencies : IEEE.Std_Logic_1164
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--
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-- Limitations : None known
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--
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-- Errors : None known
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--
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-- Author : Ovidiu Lupas
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-- olupas@opencores.org
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--
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-- Simulator : ModelSim EE version 5.2 on a Windows95 PC
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-- ActiveVHDL 3.1 on a Windows95 PC
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--===================================================================--
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-----------------------------------------------------------------------
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-- Entity for PCI bus Arbiter and CLK generator
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-----------------------------------------------------------------------
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library ieee,work;
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use ieee.Std_Logic_1164.all;
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use work.Simulation.all;
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use work.PCI_Def.all;
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-----------------------------------------------------------------------
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-----------------------------------------------------------------------
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entity ClkGen is
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generic ( tperiod : Time := 30 ns );
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port (
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REQ_N : in Std_Logic;
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GNT_N : out Std_Logic := '1';
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RST_N : out Std_Logic;
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CLK : out Std_Logic); -- System clock
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end ClkGen; --=================== End of entity =====================--
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--========================== Architecture ===========================--
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architecture BEHAV_ClkGen of ClkGen is
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begin--======================== Architecture =================================--
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---------------------------------------------------------------------
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-- Provide the external clock signal to the processor
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---------------------------------------------------------------------
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ClkDriver : process
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variable clktmp: std_logic := '0';
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begin
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CLK <= clktmp;
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clktmp := not clktmp;
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wait for tperiod/2;
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end process ClkDriver;
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---------------------------------------------------------------------
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-- Simulates an external PCI-bus arbiter, which always grants the
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-- access to the bus :)
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---------------------------------------------------------------------
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Arbiter : process(REQ_N)
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begin
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if Falling_Edge(REQ_N) then
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GNT_N <= '0' after 10 ns;
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elsif Rising_Edge(REQ_N) then
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GNT_N <= '1' after 10 ns;
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end if;
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end process Arbiter;
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---------------------------------------------------------------------
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-- Provides the reset signal
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---------------------------------------------------------------------
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RstGen: process
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begin
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RST_N <= '0';
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wait for 100 ns;
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RST_N <= '1';
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wait for 400 ns;
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end process;
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end BEHAV_ClkGen; --============== End of architecture ==============--
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-----------------------------------------------------------------------
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-- TestBench
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-----------------------------------------------------------------------
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library ieee,work,std;
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use ieee.std_logic_1164.all;
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use work.ClkGen;
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-----------------------------------------------------------------------
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-----------------------------------------------------------------------
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entity TESTPCI is
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end TESTPCI;
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--========================== Architecture ===========================--
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architecture stimulus of TESTPCI is
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---------------------------------------------------------------------
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-- Signal declaration
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---------------------------------------------------------------------
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signal AD_Bus : Std_Logic_Vector (31 downto 0);
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signal C_BE_Bus : Std_Logic_Vector (3 downto 0);
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signal PAR : Std_Logic;
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signal FRAME_N : Std_Logic;
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signal TRDY_N : Std_Logic;
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signal IRDY_N : Std_Logic;
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signal STOP_N : Std_Logic;
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signal DEVSEL_N : Std_Logic;
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signal IDSEL : Std_Logic;
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signal SEL1 : Std_Logic;
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signal SEL2 : Std_Logic;
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signal PERR_N : Std_Logic;
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signal SERR_N : Std_Logic;
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signal REQ_N : Std_Logic;
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signal GNT_N : Std_Logic;
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signal CLK : Std_Logic;
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signal RST_N : Std_Logic;
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---------------------------------------------------------------------
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-- Component declarations
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---------------------------------------------------------------------
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component ClkGen
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generic ( tperiod : Time := 30 ns );
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port (
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REQ_N : in Std_Logic;
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GNT_N : out Std_Logic;
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RST_N : out Std_Logic;
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CLK : out Std_Logic); -- System clock
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end component;
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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component MS32PCI
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generic (
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cmd_file : string(1 to 7);
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tdelay : Time;
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tsetup : Time;
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thold : Time);
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port (
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-- Address, Data and Command buses (37)
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AD_Bus : inout STD_LOGIC_VECTOR (31 downto 0);
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C_BE_Bus : inout STD_LOGIC_VECTOR (3 downto 0);
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PAR : inout STD_LOGIC;
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-- Interface control signals (6)
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FRAME_N : inout STD_LOGIC;
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TRDY_N : in STD_LOGIC;
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IRDY_N : inout STD_LOGIC;
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STOP_N : in STD_LOGIC;
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DEVSEL_N : in STD_LOGIC;
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IDSEL : in STD_LOGIC; -- in
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-- Error reporting signals (2)
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PERR_N : inout STD_LOGIC;
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SERR_N : inout STD_LOGIC;
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-- Arbitration signals (2)
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REQ_N : out STD_LOGIC;
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GNT_N : in STD_LOGIC; -- in
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-- System signals (2)
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CLK : in STD_LOGIC;
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RST_N : in STD_LOGIC); --in
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end component;
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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component TG32PCI
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generic (
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devtype : string(1 to 4);
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tdelay : Time;
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tsetup : Time;
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thold : Time;
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bamem : Std_Logic_Vector(31 downto 0); -- hex value
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baio : Std_Logic_Vector(31 downto 0); -- hex value
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bacfg : Std_Logic_Vector(31 downto 0));-- hex value
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port (
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-- Address, Data and Command buses (37)
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AD_Bus : inout Std_Logic_Vector (31 downto 0);
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C_BE_Bus : in Std_Logic_Vector (3 downto 0);
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PAR : inout Std_Logic;
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-- Interface control signals (6)
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FRAME_N : in Std_Logic;
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TRDY_N : inout Std_Logic;
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IRDY_N : in Std_Logic;
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STOP_N : out Std_Logic;
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DEVSEL_N : inout Std_Logic;
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IDSEL : in Std_Logic;
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-- Error reporting signals (2)
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PERR_N : inout Std_Logic;
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SERR_N : inout Std_Logic;
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-- System signals (2)
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CLK : in Std_Logic;
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RST_N : in Std_Logic);
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end component;
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begin --====================== Architecture =========================--
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---------------------------------------------------------------------
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-- Component instantiation
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---------------------------------------------------------------------
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UUT1: MS32PCI
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generic map (
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"PCI.CMD",0 ns, 7 ns, 5 ns)
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port map (
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AD_Bus,C_BE_Bus,PAR,FRAME_N,TRDY_N,IRDY_N,STOP_N,DEVSEL_N,
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IDSEL,PERR_N,SERR_N,REQ_N,GNT_N,CLK,RST_N);
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SEL1 <= AD_Bus(16);
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UUT2: TG32PCI
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generic map (
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"Fast",0 ns,0 ns,0 ns,x"00005000",x"00000800",x"00010CF0")
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port map (
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AD_Bus => AD_Bus,C_BE_Bus => C_BE_Bus,PAR => PAR,
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FRAME_N => FRAME_N,TRDY_N => TRDY_N,IRDY_N => IRDY_N,
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STOP_N => STOP_N,DEVSEL_N => DEVSEL_N,IDSEL => SEL1,
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PERR_N => PERR_N,SERR_N => SERR_N,CLK => CLK,RST_N => RST_N);
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SEL2 <= AD_Bus(17);
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UUT3: TG32PCI
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generic map (
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"Medi",0 ns,7 ns,0 ns,x"00006000",x"00001800",x"00020CF0")
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port map (
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AD_Bus => AD_Bus,C_BE_Bus => C_BE_Bus,PAR => PAR,
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FRAME_N => FRAME_N,TRDY_N => TRDY_N,IRDY_N => IRDY_N,
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STOP_N => STOP_N,DEVSEL_N => DEVSEL_N,IDSEL => SEL2,
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PERR_N => PERR_N,SERR_N => SERR_N,CLK => CLK,RST_N => RST_N);
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GEN: ClkGen port map (
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REQ_N,GNT_N,RST_N,CLK);
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---------------------------------------------------------------------
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end stimulus; --=============== End of architecture =================--
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-----------------------------------------------------------------------
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-- Revision list
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-- Version Author Date Changes
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--
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-- 0.1 Ovidiu Lupas June 09, 2000 New model
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-----------------------------------------------------------------------
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