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// *************************************************************** //
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//                                                                                                                                                                               //
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//                      PCI_TARGET-Wishbone_MASTER INTERFACE MODULE     (PCI-mini)       //
4
//                                                                                      v2.0                                                                             //
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//                                                                                                                                                                               //
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//   The original PCI module is from:   Ben Jackson                                              //
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//                              http://www.ben.com/minipci/verilog.php                                           //
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//                                                                                                                                                                               //
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//        Redesigned for wishbone : Istvan Nagy, buenos@freemail.hu              //
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//                                              PEC Products, Industrial Technologies                            //
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//                                                                                                                                                                               //
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// *************************************************************** //
13
 
14
// The core implements a 16MB relocable memory image. Relocable on the
15
//   wb bus. the wb address = 4M*wb_baseaddr_reg + PCI_addr[23:2]
16
//   Only Dword aligned Dword accesses allowed on the PCI. This way
17
//   we can access to the 4GB wb-space through a 16MB PCI-window.
18
//   The addressing on the wb-bus, is Dword addressing, while on the
19
//   PCI bus, the addressing is byte addressing. A(pci)=A(wb)*4
20
//   The PCI address is increasing by 4, and we get 4 bytes. The wb
21
//   address is increasing by 1, and we get 1 Dword (= 4 bytes also).
22
//   The wb_baseaddr_reg is the wb image relocation register, can be
23
//   accessed at 50h address in the PCI configuration space.
24
//   Other bridge status and command is at the 54h and 58h addresses.
25
//   if access fails with timeout, then the address will be in the 
26
//   wb address will be stored in the failed_addr_reg at 5Ch address.
27
//
28
// Wishbone compatibility:
29
//  Wishbone signals: wb_address, wb_dat_o, wb_dat_i, wb_sel_o, wb_cyc_o, 
30
//  wb_stb_o, wb_wr_o, wb_reset_o, wb_clk_o, wb_ack_i.
31
//  Not implemented wb signals: error, lock, retry, tag-signals.
32
//  The peripheral has to response with ack in 16 clk cycles.
33
//  The core has wishbone clk and reset outputs, just like a Syscon module.
34
//  The core generates single reads/writes. These are made of 4 phases, so
35
//  dont write new data, until internal data movement finishes: about 300...500ns
36
//
37
// PCI compatibility: 
38
// Only single DWORD reads/writes are supported. between them, the software has 
39
//   to wait 300...500nsec, to prevent data corrupting. STOP signaling is not 
40
//   implemented, so target terminations also not. 
41
//   Single Byte access is NOT supported! It may cause corrupt data.
42
//   The core uses INTA interrupt signal. There are some special PCI config
43
//   registers, from 50h...60h config-space addresses.
44
//   PCI-parity: it generates parity, but doesnt check incoming parity.
45
//   Because of the PC chipset, if you read a value and write it back,
46
//   the chipset will not write anything, because it can see the data is not 
47
//   changed. This is important at some peripherals, where you write, to control.
48
// Device specific PCI config header registers:
49
//   name:                                      addr:           function:
50
//   wb_baseaddr_reg;   50h             A(wb)=(A(pci)-BAR0)/4 + wb_baseaddr_reg
51
//   user_status_reg;   54h             not used yet
52
//   user_command_reg;  58h             not used yet
53
//   failed_addr_reg;   5Ch             address, when timeout occurs on the wb bus.
54
//
55
// Local bus arbitration: 
56
// This is not really wishbone compatible, but needed for the PCI.
57
//  The method is: "brute force". it means if the PCI interface wants to
58
//  be mastering on the local (wishbone) bus, then it will be mastering,
59
//  so, the other master(s) must stop anything immediately. The req signal
60
//  goes high when there is an Address hit on teh PCI bus. so the other
61
//  master has few clk cycles to finish.
62
// Restrictions: the peripherals have to be fast: If the other master
63
//  starts a transaction before req goes high, the ack has to arrive before 
64
//  the PCI interface starts its own transaction. (max 4clk ACK delay)
65
//  The other master or the bus unit must sense the req, and give bus
66
//  mastering to the PCI-IF immediatelly, not just when the other master
67
//  finished everything, like at normal arbitration schemes.
68
//
69
// Buffering:
70
//  There is a single Dword buffering only.
71
//
72
// The led_out interface: 
73
//  only for system-debug: we can write to the LEDs, at any address. 
74
//  (in the same time there is a wishbone write also)
75
//
76
// Changes since original version: wishbone interface,
77
//  bigger memory-image, parity-generation,
78
//  interrupt handling. Code size is 3x bigger. New registers, 
79
//
80
// *************************************************************** //
81
 
82
 
83
 
84
module pci(reset,clk,frame,irdy,trdy,devsel,idsel,ad,cbe,par,stop,inta,serr,perr,led_out, wb_address, wb_dat_o, wb_dat_i, wb_sel_o, wb_cyc_o, wb_stb_o, wb_wr_o, wb_reset_o, wb_clk_o, wb_ack_i, wb_irq, wb_req, wb_gnt, wb_req_other);
85
    input reset;
86
    input clk;
87
    input frame;
88
    input irdy;
89
    output trdy;
90
    output devsel;
91
    input idsel;
92
    inout [31:0] ad;
93
    input [3:0] cbe;
94
    inout par;
95
    output stop;
96
    output inta;
97
    output serr;
98
    output perr;
99
    output [3:0] led_out;
100
                output [31:0] wb_address;
101
                output [31:0] wb_dat_o;
102
                input [31:0] wb_dat_i;
103
                output [3:0] wb_sel_o;
104
                output wb_cyc_o;
105
                output wb_stb_o;
106
                output wb_wr_o;
107
                output wb_reset_o;
108
                output wb_clk_o;
109
                input wb_ack_i;
110
                input wb_irq;
111
                output wb_req;
112
                input wb_gnt;
113
                input wb_req_other;
114
 
115
 
116
 
117
parameter DEVICE_ID = 16'h9500;
118
parameter VENDOR_ID = 16'h10EE; //       16'h10EE=xilinx, 16'h106d; // Sequent!
119
parameter DEVICE_CLASS = 24'h068000;    // Bridge device - other_bridge_type (original:FF0000 Misc)
120
parameter DEVICE_REV = 8'h01;
121
parameter SUBSYSTEM_ID = 16'h0001;      // Card identifier
122
parameter SUBSYSTEM_VENDOR_ID = 16'hBEBE; // Card identifier
123
parameter DEVSEL_TIMING = 2'b00;        // Fast!
124
 
125
reg [2:0] state;
126
reg [31:0] data;
127
 
128
reg [1:0] enable;
129
parameter EN_NONE = 0;
130
parameter EN_RD = 1;
131
parameter EN_WR = 2;
132
parameter EN_TR = 3;
133
 
134
reg memen; // respond to baseaddr?
135
reg [7:0] baseaddr;
136
reg [5:0] address;
137
 
138
reg [9:0] wb_baseaddr_reg; //remap the image on the wishbone bus
139
reg [31:0] wb_address_1;
140
reg [31:0] user_status_reg;
141
reg [31:0] user_command_reg;
142
reg [31:0] failed_addr_reg;
143
reg [31:0] dummy_reg;
144
reg [31:0] pci_read_reg;
145
reg [31:0] pci_write_reg;
146
reg [31:0] wb_read_reg;
147
reg [31:0] wb_write_reg;
148
reg [3:0] pci_read_sel_reg;
149
reg [3:0] pci_write_sel_reg;
150
reg [3:0] wb_read_sel_reg;
151
reg [3:0] wb_write_sel_reg;
152
 
153
parameter ST_IDLE = 3'b000;
154
parameter ST_BUSY = 3'b010;
155
parameter ST_MEMREAD = 3'b100;
156
parameter ST_MEMWRITE = 3'b101;
157
parameter ST_CFGREAD = 3'b110;
158
parameter ST_CFGWRITE = 3'b111;
159
 
160
parameter MEMREAD = 4'b0110;
161
parameter MEMWRITE = 4'b0111;
162
parameter CFGREAD = 4'b1010;
163
parameter CFGWRITE = 4'b1011;
164
 
165
`define LED
166
`ifdef LED
167
reg [3:0] led;
168
`endif
169
 
170
`undef STATE_DEBUG_LED
171
`ifdef STATE_DEBUG_LED
172
assign led_out = ~state;
173
`else
174
`ifdef LED
175
assign led_out = ~led;
176
`endif
177
`endif
178
 
179
assign ad = (enable == EN_RD) ? data : 32'bZ;
180
assign trdy = (enable == EN_NONE) ? 'bZ : (enable == EN_TR ? 1 : 0);
181
//assign par = (enable == EN_RD) ? 0 : 'bZ;
182
reg devsel;
183
 
184
assign stop = 1'bZ;
185
//assign inta = 1'bZ;
186
assign serr = 1'bZ;
187
assign perr = 1'bZ;
188
 
189
 
190
wire cfg_hit = ((cbe == CFGREAD || cbe == CFGWRITE) && idsel && ad[1:0] == 2'b00);
191
wire addr_hit = ((cbe == MEMREAD || cbe == MEMWRITE) && memen && ad[31:24] == {baseaddr});
192
wire hit = cfg_hit | addr_hit;
193
 
194
// Wishbone SYSCON: output signals------------------------------------
195
assign wb_reset_o = ~reset;
196
assign wb_clk_o = clk;
197
//reg wb_clk_o;
198
   //always @(posedge clk)
199
                //wb_clk_o = wb_clk_o+ 1;
200
 
201
 
202
// PCI parity generation:---------------------------------------------
203
// during read, the parity on AD, and delayen by one clk.
204
reg par_en;
205
reg par_latched;
206
reg EN_RDd;
207
wire data_par = (data[31] ^ data[30] ^ data[29] ^ data[28]) ^
208
                (data[27] ^ data[26] ^ data[25] ^ data[24]) ^
209
                (data[23] ^ data[22] ^ data[21] ^ data[20]) ^
210
                (data[19] ^ data[18] ^ data[17] ^ data[16]) ^
211
                (data[15] ^ data[14] ^ data[13] ^ data[12]) ^
212
                (data[11] ^ data[10] ^ data[9]  ^ data[8])  ^
213
                (data[7]  ^ data[6]  ^ data[5]  ^ data[4])  ^
214
                                          (cbe[3]  ^ cbe[2]  ^ cbe[1]  ^ cbe[0])  ^
215
                (data[3]  ^ data[2]  ^ data[1]  ^ data[0]) ;
216
 
217
   always @(posedge clk) //delaying of parity
218
      if ((enable == EN_RD)|(enable == EN_TR)) begin
219
         par_latched = data_par; end
220
      else
221
         begin par_latched = 0; end
222
 
223
   always @(posedge clk) //delaying of EN_RD
224
                        EN_RDd = EN_RD;
225
 
226
        //assign par = (enable == EN_RD) ? 0 : 'bZ;
227
        assign par = ((enable == EN_RD)|(enable == EN_RDd)) ? par_latched : 'bZ; //output control
228
 
229
 
230
 
231
// Interrupt handling:--------------------------------------------------------------------
232
reg int_dis;
233
wire int_stat;
234
reg [7:0] int_line;
235
assign inta = ((wb_irq == 1) && (int_dis == 0)) ? 1'b0 : 1'bZ;
236
assign int_stat = wb_irq;
237
 
238
 
239
 
240
// WB bus arbitration:--------------------------------------------------------------------
241
//assign wb_req = mastering;
242
reg arb_start;
243
reg arb_stop;
244
reg wb_req;
245
 
246
   parameter arb_state1 = 2'b00;
247
   parameter arb_state2 = 2'b01;
248
   reg  arb_state = arb_state1;
249
   always@(posedge clk) begin
250
      if (wb_reset_o) begin
251
         arb_state <= arb_state1;
252
         wb_req <= 0;
253
      end
254
      else
255
         case (arb_state)
256
            arb_state1 : begin //arbitration is not needed: IDLE
257
               wb_req <= 0;
258
               if (arb_start == 1)
259
                  arb_state <= arb_state2;
260
            end
261
            arb_state2 : begin //arbitration is needed
262
               wb_req <= 1;
263
               if (arb_stop == 1)
264
                  arb_state <= arb_state1;
265
            end
266
            default : begin  // Fault Recovery
267
               arb_state <= arb_state1;
268
               wb_req <= 0;
269
            end
270
         endcase
271
                end
272
 
273
 
274
 
275
// -------------- wishbone state machine --------------------------------------------------
276
//write FIFO buffer:
277
reg [31:0] wb_wr_buf [5:0]; //64 Dwords wb write buffer: wb_wr_buf[index] <= value;
278
reg [3:0] wb_wr_sel_buf [5:0]; //select lines, write buffer: wb_wr_buf[index] <= value;
279
reg [31:0] fifo_start_wb_addr;
280
reg [31:0] fifo_act_wb_addr;
281
reg [5:0] fifo_max_count;
282
reg [5:0] fifo_wb_counter;
283
reg [5:0] fifo_wb_counter_o;
284
reg fifo_flush; //wb output mux control
285
reg fifo_flush_start; //start pulse
286
reg fifo_fill; //disable wb during filling fifo
287
reg [3:0] wbw_timeout_count_new;
288
reg [1:0] wbw_phase;
289
//read FIFO buffer:
290
reg [31:0] wb_rd_buf [5:0]; //64 Dwords wb read buffer: wb_rd_buf[index] <= value;
291
reg [3:0] wb_rd_sel_buf [5:0]; //select lines, write buffer: wb_wr_buf[index] <= value;
292
reg [31:0] fifo_start_wb_addr_rd;
293
reg [31:0] fifo_act_wb_addr_rd;
294
reg [5:0] fifo_max_count_rd;
295
reg [5:0] fifo_wb_counter_rd;
296
reg [5:0] fifo_wb_counter_o_rd;
297
reg fifo_flush_rd; //wb output mux control
298
reg fifo_fill_start_rd; //start pulse
299
reg fifo_fill_rd; //disable wb during filling fifo
300
reg [3:0] wbr_timeout_count_new;
301
reg [1:0] wbr_phase;
302
//
303
reg wb_cyc_o;
304
reg wb_stb_o;
305
reg wb_wr_o;
306
reg [31:0] wb_address;
307
reg [3:0] wb_sel_o;
308
reg [31:0] wb_dat_o;
309
reg machinereset;
310
reg mastering;
311
//assign wb_req = mastering;
312
 
313
 
314
   parameter machine_waiting = 2'b00;
315
   parameter machine_flushing = 2'b01;
316
   parameter machine_read_filling = 2'b11;
317
   reg [1:0] wbwf_state = machine_waiting;
318
 
319
   always@(posedge wb_clk_o)
320
      if (wb_reset_o) begin
321
         wbwf_state <= machine_waiting;
322
                         wbw_phase <= 0;
323
                        wbw_timeout_count_new <= 0;
324
                        fifo_wb_counter_o<=0;
325
                        fifo_flush <= 0;
326
                        wb_cyc_o <= 0;
327
                        wb_stb_o <= 0;
328
                        wb_wr_o <= 0;
329
                         wbr_phase <= 0;
330
                        wbr_timeout_count_new <= 0;
331
                        fifo_wb_counter_o_rd<=0;
332
                        fifo_fill_rd <= 0;
333
                        wb_address[31:0] = 32'b0;
334
                        wb_sel_o = 4'b0;
335
                        wb_dat_o = 32'b0;
336
                        pci_read_reg <= 0;
337
                        mastering <= 0;
338
                        arb_stop <= 0;
339
                        failed_addr_reg <= 0;
340
      end
341
      else
342
         case (wbwf_state)
343
 
344
            machine_waiting : begin //no operation on Wishbone bus **************
345
                                        wbw_phase <= 0;
346
                                        wbw_timeout_count_new <= 0;
347
                                        wbr_phase <= 0;
348
                                        wbr_timeout_count_new <= 0;
349
                                        wb_address[31:0] = 32'b0;
350
                                        wb_cyc_o <= 0;
351
                                        wb_stb_o <= 0;
352
                                        wb_wr_o <= 0;
353
                                        wb_sel_o = 4'b0;
354
                                        wb_dat_o = 32'b0;
355
                                        arb_stop <= 0;
356
               if (fifo_flush_start  == 1)
357
                  begin fifo_flush <= 1; wbwf_state <= machine_flushing; fifo_wb_counter_o<=0; mastering <= 1; end
358
                                        else if (fifo_fill_start_rd == 1)
359
                  begin fifo_fill_rd <= 1; wbwf_state <= machine_read_filling; fifo_wb_counter_o_rd<=0; mastering <= 1; end
360
            end
361
 
362
            machine_flushing : begin //wr-FIFO flushing: wb write***********************
363
                                        wb_sel_o = pci_write_sel_reg;
364
                                        wb_dat_o  = pci_write_reg; //wb_wr_buf[fifo_wb_counter_o];
365
                                        wb_address[31:0]  = fifo_start_wb_addr; //[31:0]+fifo_wb_counter_o ;
366
               if ( wbw_phase== 0 ) begin //phase 0: setup
367
                  wb_cyc_o <= 0;
368
                                                wb_stb_o <= 0;
369
                                                wb_wr_o <= 0;
370
                                                wbw_phase <= wbw_phase + 1;
371
                                                //address and data also changes now, from FIFO
372
                                        end
373
                                        else if ( wbw_phase== 1 ) begin //phase 1: access
374
                  wb_cyc_o <= 1;
375
                                                wb_stb_o <= 1;
376
                                                wb_wr_o <= 1;
377
                                                wbw_phase <= wbw_phase + 1;
378
                                        end
379
                                        else if ( wbw_phase== 2 ) begin //phase 2: wait for ack
380
                                                wbw_timeout_count_new <= wbw_timeout_count_new +1;
381
                                                if ((wb_ack_i==1) | (wbw_timeout_count_new==15)) begin
382
                                                        wbw_phase <= wbw_phase + 1;
383
                                                        wb_cyc_o <= 0;
384
                                                        wb_stb_o <= 0;
385
                                                        wb_wr_o <= 0;
386
                                                        if (wbw_timeout_count_new==15) begin failed_addr_reg <= wb_address; end
387
                                                        end
388
                                                else begin wb_cyc_o <= 1;       wb_stb_o <= 1;  wb_wr_o <= 1; end
389
                                        end
390
                                        else  if ( wbw_phase== 3 ) begin //phase 3: hold (finish)
391
                                           wb_cyc_o <= 0;
392
                                                wb_stb_o <= 0;
393
                                                wb_wr_o <= 0;
394
                                                wbw_phase <= wbw_phase + 1;
395
                                                wbw_timeout_count_new <=0;
396
                                                fifo_wb_counter_o <= fifo_wb_counter_o + 1; //for next word
397
                                                //if ((fifo_wb_counter_o == fifo_max_count-1)|(machinereset == 1)) begin 
398
                                                        fifo_flush <= 0;
399
                                                        wbwf_state <= machine_waiting;
400
                                                        fifo_wb_counter_o<=0;
401
                                                        mastering <= 0;
402
                                                        arb_stop <= 1;
403
                                                //end
404
                                        end
405
            end
406
 
407
            machine_read_filling : begin //rd-FIFO filling: wb read********************
408
                                   wb_sel_o = pci_read_sel_reg;
409
                                        wb_dat_o = 32'b0;
410
                                        wb_address[31:0]  = fifo_start_wb_addr_rd; //[31:0]+fifo_wb_counter_o_rd ;
411
               if ( wbr_phase== 0 ) begin //phase 0: setup
412
                  wb_cyc_o <= 0;
413
                                                wb_stb_o <= 0;
414
                                                wb_wr_o <= 0;
415
                                                wbr_phase <= wbr_phase + 1;
416
                                                //address and data also changes now, from FIFO
417
                                        end
418
                                        else if ( wbr_phase== 1 ) begin //phase 1: access
419
                  wb_cyc_o <= 1;
420
                                                wb_stb_o <= 1;
421
                                                wb_wr_o <= 0;
422
                                                wbr_phase <= wbr_phase + 1;
423
                                        end
424
                                        else if ( wbr_phase== 2 ) begin //phase 2: wait for ack
425
                                                wbr_timeout_count_new <= wbr_timeout_count_new +1;
426
                                                if ((wb_ack_i==1) | (wbr_timeout_count_new==15)) begin
427
                                                        //wb_rd_buf[fifo_wb_counter_o_rd] <= wb_dat_i; //sampling
428
                                                        pci_read_reg <= wb_dat_i; //sampling
429
                                                        wbr_phase <= wbr_phase + 1;
430
                                                        wb_cyc_o <= 0;
431
                                                        wb_stb_o <= 0;
432
                                                        wb_wr_o <= 0;
433
                                                        if (wbw_timeout_count_new==15) begin failed_addr_reg <= wb_address; end
434
                                                        end
435
                                                else begin wb_cyc_o <= 1;       wb_stb_o <= 1;  wb_wr_o <= 0; end
436
                                        end
437
                                        else  if ( wbr_phase== 3 ) begin //phase 3: hold (finish)
438
                                           wb_cyc_o <= 0;
439
                                                wb_stb_o <= 0;
440
                                                wb_wr_o <= 0;
441
                                                wbr_phase <= wbw_phase + 1;
442
                                                wbr_timeout_count_new <=0;
443
                                                fifo_wb_counter_o_rd <= fifo_wb_counter_o_rd + 1; //for next word
444
                                                //if ((fifo_wb_counter_o_rd == fifo_max_count_rd-1)|(machinereset == 1)) begin 
445
                                                        fifo_fill_rd <= 0;
446
                                                        wbwf_state <= machine_waiting;
447
                                                        fifo_wb_counter_o_rd<=0;
448
                                                        mastering <= 0;
449
                                                        arb_stop <= 1;
450
                                                //end
451
                                        end
452
            end
453
 
454
            default : begin  // Fault Recovery
455
               wbwf_state <= machine_waiting;
456
            end
457
 
458
 
459
         endcase
460
 
461
 
462
 
463
 
464
 
465
 
466
 
467
// main PCI state machine: ---------------------------------------------------------------
468
always @(posedge clk)
469
begin
470
    if (~reset) begin
471
        state <= ST_IDLE;
472
        enable <= EN_NONE;
473
        baseaddr <= 0;
474
        devsel <= 'bZ;
475
        memen <= 0;
476
                  int_line <= 8'b0;
477
                  int_dis <= 0;
478
                  wb_baseaddr_reg <= 0;
479
                  wb_address_1[31:0] <= 0;
480
                  user_status_reg <= 0;
481
                  user_command_reg <= 0;
482
                  fifo_flush_start <= 0;
483
                  fifo_fill_start_rd <= 0;
484
                  fifo_wb_counter <= 0;
485
                  fifo_wb_counter_rd <= 0;
486
                        dummy_reg  <= 0;
487
                        pci_write_reg <= 0;
488
                        machinereset   <= 0;
489
        led <= 0;
490
                  arb_start <= 0;
491
 
492
    end
493
    else    begin
494
 
495
    case (state)
496
        ST_IDLE: begin
497
            enable <= EN_NONE;
498
            devsel <= 'bZ;
499
                                fifo_flush_start <= 0;
500
                                fifo_fill_start_rd <= 0;
501
                                fifo_wb_counter <= 0;
502
                                fifo_wb_counter_rd <= 0;
503
                                machinereset   <= 0;
504
            if (~frame) begin
505
                address <= ad[7:2];
506
                if (hit) begin
507
                    state <= {1'b1, cbe[3], cbe[0]};
508
                                                  if (addr_hit) begin  arb_start <= 1; end
509
                    devsel <= 0;
510
                                                  wb_address_1[31:0] <= {wb_baseaddr_reg, ad[23:2]};
511
                                                  //if (wbwf_state == machine_waiting) begin //sample address, if FIFO is not busy
512
                                                                fifo_start_wb_addr <= {wb_baseaddr_reg, ad[23:2]};
513
                                                                fifo_start_wb_addr_rd <= {wb_baseaddr_reg, ad[23:2]};
514
                                                  //end         
515
                    // pipeline the write enable
516
                    if (cbe[0])
517
                        enable <= EN_WR;
518
                end
519
                else begin
520
                    state <= ST_BUSY;
521
                    enable <= EN_NONE;
522
                end
523
            end
524
        end
525
 
526
        ST_BUSY: begin
527
            devsel <= 'bZ;
528
            enable <= EN_NONE;
529
                                arb_start <= 0;
530
            if (frame)
531
                state <= ST_IDLE;
532
        end
533
 
534
        ST_CFGREAD: begin
535
            enable <= EN_RD;
536
            if (~irdy || trdy) begin
537
                case (address)
538
                    0: data <= { DEVICE_ID, VENDOR_ID };
539
                    1: data <= { 5'b0, DEVSEL_TIMING,  5'b0, int_stat, 8'b0, int_dis, 8'b0, memen, 1'b0};
540
                    2: data <= { DEVICE_CLASS, DEVICE_REV };
541
                    4: data <= { baseaddr, 12'b0, 8'b0, 4'b0000 }; // baseaddr + request mem < 1Mbyte
542
                    11: data <= {SUBSYSTEM_ID, SUBSYSTEM_VENDOR_ID };
543
                                                  15: data <= {16'b0, 7'b0, 1'b1, int_line}; //irq pin and line
544
                    16: data <= { 24'b0, baseaddr };
545
                                                  20: data <= { wb_baseaddr_reg, 22'b0}; //wb base address: for wb-local relocation
546
                                                  21: data <= user_status_reg;
547
                                                  22: data <= user_command_reg;
548
                                                  23: data <= failed_addr_reg; //actual addr, at a timeout
549
                    default: data <= 'h00000000;
550
                endcase
551
                address <= address + 1;
552
                                         arb_start <= 0;
553
            end
554
            if (frame && ~irdy && ~trdy) begin
555
                devsel <= 1;
556
                state <= ST_IDLE;
557
                enable <= EN_TR;
558
            end
559
        end
560
 
561
        ST_CFGWRITE: begin
562
            enable <= EN_WR;
563
            if (~irdy) begin
564
                case (address)
565
                    4: baseaddr <= ad[31:24];  // XXX examine cbe
566
                    1: begin memen <= ad[1]; int_dis <= ad[10]; end
567
                                                  15: int_line <= ad[7:0];
568
                                                  20: wb_baseaddr_reg <= ad[31:22];
569
                                                  22: user_command_reg  <= ad[31:0];
570
                                                  24: machinereset   <= 1;      //resetting the wb state machine (60h)
571
                    default: ;
572
                endcase
573
                address <= address + 1;
574
                                         arb_start <= 0;
575
                if (frame) begin
576
                    devsel <= 1;
577
                    state <= ST_IDLE;
578
                    enable <= EN_TR;
579
                end
580
            end
581
        end
582
 
583
        ST_MEMREAD: begin
584
            enable <= EN_RD;
585
                                arb_start <= 0;
586
            if (~irdy || trdy) begin
587
                address <= address + 1;
588
                                         data <= pci_read_reg;
589
                                         pci_read_sel_reg  <= ~cbe;
590
            end
591
            if (frame && ~irdy && ~trdy) begin
592
                devsel <= 1;
593
                state <= ST_IDLE;
594
                enable <= EN_TR;
595
                                                  fifo_fill_rd<=0;
596
                                                  //if (wbwf_state == machine_waiting) begin 
597
                                                                fifo_fill_start_rd <= 1;
598
                                                  //end                                          
599
            end
600
        end
601
 
602
        ST_MEMWRITE: begin
603
            enable <= EN_WR;
604
                                arb_start <= 0;
605
            if (~irdy) begin
606
                                         led <= ad[3:0];
607
                                         pci_write_reg  <= ad[31:0];
608
                                         pci_write_sel_reg <= ~cbe;
609
                address <= address + 1;
610
                if (frame) begin
611
                    devsel <= 1;
612
                    state <= ST_IDLE;
613
                    enable <= EN_TR;
614
                                                  fifo_fill<=0;
615
                                                  //if (wbwf_state == machine_waiting) begin 
616
                                                                fifo_flush_start <= 1;
617
                                                  //end         
618
               end
619
            end
620
 
621
        end
622
 
623
    endcase
624
    end
625
end
626
endmodule

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