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# Synopsys, Inc. constraint file

# Written on Wed Apr 13 17:34:51 2011

# by Synplify Pro, D-2009.12A Scope Editor

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# Collections

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# Clocks

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define_clock   {pciclk} -name {pciclk}  -freq 33 -clockgroup default_clkgroup_2

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# Clock to Clock

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# Inputs/Outputs

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define_input_delay               {serr}  7.00 -improve 0.00 -route 0.00 -ref {pciclk:r}

define_input_delay               {perr}  7.00 -improve 0.00 -route 0.00 -ref {pciclk:r}

define_input_delay               {idsel}  7.00 -improve 0.00 -route 0.00 -ref {pciclk:r}

define_input_delay               {stop}  7.00 -improve 0.00 -route 0.00 -ref {pciclk:r}

define_input_delay               {devsel}  7.00 -improve 0.00 -route 0.00 -ref {pciclk:r}

define_input_delay               {trdy}  7.00 -improve 0.00 -route 0.00 -ref {pciclk:r}

define_input_delay               {irdy}  7.00 -improve 0.00 -route 0.00 -ref {pciclk:r}

define_input_delay               {frame}  7.00 -improve 0.00 -route 0.00 -ref {pciclk:r}

define_input_delay               {par}  7.00 -improve 0.00 -route 0.00 -ref {pciclk:r}

define_input_delay               {cbe[3:0]}  7.00 -improve 0.00 -route 0.00 -ref {pciclk:r}

define_input_delay               {AD[31:0]}  7.00 -improve 0.00 -route 0.00 -ref {pciclk:r}

define_output_delay              {serr}  22.00 -improve 0.00 -route 0.00 -ref {pciclk:r}

define_output_delay              {perr}  22.00 -improve 0.00 -route 0.00 -ref {pciclk:r}

define_output_delay              {stop}  22.00 -improve 0.00 -route 0.00 -ref {pciclk:r}

define_output_delay              {devsel}  22.00 -improve 0.00 -route 0.00 -ref {pciclk:r}

define_output_delay              {trdy}  22.00 -improve 0.00 -route 0.00 -ref {pciclk:r}

define_output_delay              {par}  22.00 -improve 0.00 -route 0.00 -ref {pciclk:r}

define_output_delay              {AD[31:0]}  22.00 -improve 0.00 -route 0.00 -ref {pciclk:r}

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# Registers

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# Delay Paths

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# Attributes

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# I/O Standards

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# Compile Points

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# Other

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