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--
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-- Title : adm2_pkg
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-- Author : Dmitry Smekhov
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-- Company : Instrumental System
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--
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-- Version : 2.1
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--
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--
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-- Description : Определение типов данных и общих модулей
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--
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--
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-- Version 2.1 18.07.2007
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-- Добавлено описание типа std_logic_array16x6
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--
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--
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-- Version 2.0 15.12.2006
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-- Добавлены описания типов std_logic_array16x ...
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--
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--
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-- Version 1.4 17.06.2005
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-- Удалены описания компонентов
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--
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--
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-- Version 1.3 31.10.2003
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-- Добавлены описания модулей cl_fifo256x32_v2
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--
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library ieee;
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use ieee.std_logic_1164.all;
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package adm2_pkg is
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type bl_cmd is record
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data_we : std_logic; -- 1 - запись в регистр DATA
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cmd_data_we : std_logic; -- 1 - запись в регистр CMD_DATA
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status_cs : std_logic; -- 0 - чтение из регистра STATUS
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data_cs : std_logic; -- 0 - чтение из регистра DATA
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cmd_data_cs : std_logic; -- 0 - чтение из регистра CMD_DATA
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cmd_adr_we : std_logic; -- 1 - запись в регистр косвенного адреса
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adr : std_logic_vector( 9 downto 0 ); -- косвенный адрес
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data_oe : std_logic; -- 0 - разрешение выхода регистра DATA
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end record;
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type bl_drq is record
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en : std_logic; -- 1 - разрешение запроса DMA
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req : std_logic; -- 1 - запрос на выполнение цикла DMA
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ack : std_logic; -- 1 - выполнение цикла DMA
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end record;
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type bl_trd_rom is array( 31 downto 0 ) of std_logic_vector( 15 downto 0 );
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type bl_fifo_flag is record
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ef : std_logic; -- 0 - FIFO пустое
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pae : std_logic; -- 0 - FIFO почти пустое
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hf : std_logic; -- 0 - FIFO заполнено наполовину
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paf : std_logic; -- 0 - FIFO почти полное
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ff : std_logic; -- 0 - FIFO полное
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ovr : std_logic; -- 1 - запись в полное FIFO
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und : std_logic; -- 1 - чтение из пустого FIFO
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end record;
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type std_logic_array_16x64 is array (15 downto 0) of std_logic_vector(63 downto 0);
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type std_logic_array_16x16 is array (15 downto 0) of std_logic_vector(15 downto 0);
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type std_logic_array_16x6 is array (15 downto 0) of std_logic_vector(6 downto 0);
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type std_logic_array_16xbl_cmd is array (15 downto 0) of bl_cmd;
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type std_logic_array_16xbl_drq is array (15 downto 0) of bl_drq;
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type std_logic_array_16xbl_irq is array (15 downto 0) of std_logic;
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type std_logic_array_16xbl_reset_fifo is array (15 downto 0) of std_logic;
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type std_logic_array_16xbl_trd_rom is array (15 downto 0) of bl_trd_rom;
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type std_logic_array_16x7 is array (15 downto 0) of std_logic_vector(6 downto 0);
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type std_logic_array_16xbl_fifo_flag is array (15 downto 0) of bl_fifo_flag;
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component ctrl_buft16 is
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port (
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t: in std_logic;
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i: in std_logic_vector(15 downto 0);
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o: out std_logic_vector(15 downto 0));
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end component;
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component ctrl_buft32 is
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port (
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t: in std_logic;
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i: in std_logic_vector(31 downto 0);
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o: out std_logic_vector(31 downto 0));
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end component;
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component ctrl_buft64 is
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port (
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t: in std_logic;
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i: in std_logic_vector(63 downto 0);
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o: out std_logic_vector(63 downto 0));
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end component;
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end package;
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