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--
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-- Title : pb_adm_ctrl_m2
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-- Author : Dmitry Smekhov
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-- Company : Instrumental System
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-- E-mail : dsmv@insys.ru
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--
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-- Version : 1.0
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--
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---------------------------------------------------------------------------------------------------
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--
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-- Description : Óçåë äåêîäèðîâàíèÿ àäðåñà è ïîäêëþ÷åíèÿ ê òåòðàäàì äëÿ øèíû PLD_BUS
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-- Ïîääåðæèâàåòñÿ âîñåìü òåòðàä
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--
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-- Ìîäèôèêàöèÿ 2.
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-- Óâåëè÷åíî ÷èñëî òàêòîâ íà îòâåò.
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--
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---------------------------------------------------------------------------------------------------
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--
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-- Version 1.0 01.04.2010
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-- Ñîçäàí èç pb_adm_ctrl v1.6
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--
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---------------------------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use ieee.std_logic_arith.all;
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library work;
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use work.adm2_pkg.all;
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package pb_adm_ctrl_m2_pkg is
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component pb_adm_ctrl_m2 is
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generic (
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---- Ðàçðåøåíèå ÷òåíèÿ èç ðåãèñòðà DATA ----
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trd1_in : in integer:=0;
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trd2_in : in integer:=0;
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trd3_in : in integer:=0;
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trd4_in : in integer:=0;
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trd5_in : in integer:=0;
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trd6_in : in integer:=0;
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trd7_in : in integer:=0;
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---- Ðàçðåøåíèå ÷òåíèÿ èç ðåãèñòðà STATUS ----
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trd1_st : in integer:=0;
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trd2_st : in integer:=0;
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trd3_st : in integer:=0;
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trd4_st : in integer:=0;
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trd5_st : in integer:=0;
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trd6_st : in integer:=0;
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trd7_st : in integer:=0;
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---- Êîíñòàíòû òåòðàäû ----
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rom0 : in bl_trd_rom;
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rom1 : in bl_trd_rom;
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rom2 : in bl_trd_rom;
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rom3 : in bl_trd_rom;
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rom4 : in bl_trd_rom;
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rom5 : in bl_trd_rom;
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rom6 : in bl_trd_rom;
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rom7 : in bl_trd_rom;
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---- Ðåæèì óïðàâëåíèÿ ïåðåïàêîâêîé äëÿ òåòðàäû 4 ----
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---- 0 - ïåðåïàêîâêà 32->64 ðàçðåøàåòñÿ áèòîì MAIN.MODE2[4] ----
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---- 2 - ïåðåïàêîâêà ðàçðåøàåòñÿ ïðè ðàçðåøåíèè DRQ2 ----
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trd4_mode : in integer:=0
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);
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port (
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---- GLOBAL ----
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reset : in std_logic; -- 0 - ñáðîñ
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clk : in std_logic; -- òàêòîâàÿ ÷àñòîòà
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---- PLD_BUS ----
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lc_adr : in std_logic_vector( 6 downto 0 ); -- øèíà àäðåñà
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lc_host_data : in std_logic_vector( 63 downto 0 ); -- øèíà äàííûõ, âõîä
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lc_data : out std_logic_vector( 63 downto 0 ); -- øèíà äàííûõ, âûõîä
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lc_wr : in std_logic; -- 1 - çàïèñü
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lc_rd : in std_logic; -- 1 - ÷òåíèå
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test_mode : in std_logic; -- 1 - òåñòîâûé ðåæèì
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---- Øèíà àäðåñà äëÿ ïîäêëþ÷åíèÿ ê óçëó íà÷àëüíîãî òåñòèðîâàíèÿ òåòðàäû MAIN ----
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trd_host_adr : out std_logic_vector( 6 downto 0 );
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---- Øèíà äàííûõ, ÷åðåç êîòîðóþ ïðîèçâîäèòüñÿ çàïèñü â ðåãèñòðû òåòðàäû ----
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trd_host_data : out std_logic_vector( 63 downto 0 );
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---- Øèíà äàííûõ, ÷åðåç êîòîðóþ ïðîèçâîäèòüñÿ çàïèñü â ðåãèñòð DATA òåòðàäû 4 ----
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trd4_host_data : out std_logic_vector( 63 downto 0 );
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---- Êîìàäà óïðàâëåíèÿ äëÿ êàæäîé òåòðàäû ----
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trd_host_cmd : out std_logic_array_16xbl_cmd;
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---- Âûõîäû ðåãèñòà DATA îò êàæäîé òåòðàäû ----
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trd_data : in std_logic_array_16x64:=(others=>(others=>'0'));
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---- Âûõîäû ðåãèñòðîâ STATUS, CMD_ADR, CMD_DATA îò êàæäîé òåòðàäû ----
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trd_cmd_data : in std_logic_array_16x16:=(others=>(others=>'0'));
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---- Ñáðîñ FIFO îò êàæäîé òåòðàäû ----
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trd_reset_fifo : in std_logic_array_16xbl_reset_fifo:=(others=>'0');
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---- Çàïðîñû DMA îò êàæäîé òåòðàäû ----
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trd_drq : in std_logic_array_16xbl_drq:=(others=>(others=>'0'));
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---- Èñòî÷íèêè ïðåðûâàíèé è DRQ ----
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int1 : in std_logic:='0';
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drq0 : in bl_drq:=('0', '0', '0');
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drq1 : in bl_drq:=('0', '0', '0');
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drq2 : in bl_drq:=('0', '0', '0');
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drq3 : in bl_drq:=('0', '0', '0');
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---- Âûõîä DRQ è IRQ ----
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irq1 : out std_logic;
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dmar0 : out std_logic;
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dmar1 : out std_logic;
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dmar2 : out std_logic;
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dmar3 : out std_logic
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);
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end component;
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end package pb_adm_ctrl_m2_pkg;
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use ieee.std_logic_arith.all;
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-- synopsys translate_off
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library ieee;
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use ieee.vital_timing.all;
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library unisim;
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use unisim.VCOMPONENTS.all;
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-- synopsys translate_on
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library work;
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use work.adm2_pkg.all;
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entity pb_adm_ctrl_m2 is
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generic (
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---- Ðàçðåøåíèå ÷òåíèÿ èç ðåãèñòðà DATA ----
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trd1_in : in integer:=0;
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trd2_in : in integer:=0;
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trd3_in : in integer:=0;
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trd4_in : in integer:=0;
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trd5_in : in integer:=0;
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trd6_in : in integer:=0;
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trd7_in : in integer:=0;
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---- Ðàçðåøåíèå ÷òåíèÿ èç ðåãèñòðà STATUS ----
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trd1_st : in integer:=0;
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trd2_st : in integer:=0;
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trd3_st : in integer:=0;
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trd4_st : in integer:=0;
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trd5_st : in integer:=0;
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trd6_st : in integer:=0;
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trd7_st : in integer:=0;
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---- Êîíñòàíòû òåòðàäû ----
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rom0 : in bl_trd_rom;
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rom1 : in bl_trd_rom;
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rom2 : in bl_trd_rom;
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rom3 : in bl_trd_rom;
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rom4 : in bl_trd_rom;
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rom5 : in bl_trd_rom;
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rom6 : in bl_trd_rom;
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rom7 : in bl_trd_rom;
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---- Ðåæèì óïðàâëåíèÿ ïåðåïàêîâêîé äëÿ òåòðàäû 4 ----
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---- 0 - ïåðåïàêîâêà 32->64 ðàçðåøàåòñÿ áèòîì MAIN.MODE2[4] ----
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---- 2 - ïåðåïàêîâêà ðàçðåøàåòñÿ ïðè ðàçðåøåíèè DRQ2 ----
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trd4_mode : in integer:=0
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);
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port (
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---- GLOBAL ----
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reset : in std_logic; -- 0 - ñáðîñ
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clk : in std_logic; -- òàêòîâàÿ ÷àñòîòà
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---- PLD_BUS ----
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lc_adr : in std_logic_vector( 6 downto 0 ); -- øèíà àäðåñà
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lc_host_data : in std_logic_vector( 63 downto 0 ); -- øèíà äàííûõ, âõîä
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lc_data : out std_logic_vector( 63 downto 0 ); -- øèíà äàííûõ, âûõîä
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lc_wr : in std_logic; -- 1 - çàïèñü
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lc_rd : in std_logic; -- 1 - ÷òåíèå
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test_mode : in std_logic; -- 1 - òåñòîâûé ðåæèì
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---- Øèíà àäðåñà äëÿ ïîäêëþ÷åíèÿ ê óçëó íà÷àëüíîãî òåñòèðîâàíèÿ òåòðàäû MAIN ----
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trd_host_adr : out std_logic_vector( 6 downto 0 );
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---- Øèíà äàííûõ, ÷åðåç êîòîðóþ ïðîèçâîäèòüñÿ çàïèñü â ðåãèñòðû òåòðàäû ----
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trd_host_data : out std_logic_vector( 63 downto 0 );
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---- Øèíà äàííûõ, ÷åðåç êîòîðóþ ïðîèçâîäèòüñÿ çàïèñü â ðåãèñòð DATA òåòðàäû 4 ----
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trd4_host_data : out std_logic_vector( 63 downto 0 );
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---- Êîìàäà óïðàâëåíèÿ äëÿ êàæäîé òåòðàäû ----
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trd_host_cmd : out std_logic_array_16xbl_cmd;
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---- Âûõîäû ðåãèñòà DATA îò êàæäîé òåòðàäû ----
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trd_data : in std_logic_array_16x64:=(others=>(others=>'0'));
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---- Âûõîäû ðåãèñòðîâ STATUS, CMD_ADR, CMD_DATA îò êàæäîé òåòðàäû ----
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trd_cmd_data : in std_logic_array_16x16:=(others=>(others=>'0'));
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---- Ñáðîñ FIFO îò êàæäîé òåòðàäû ----
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trd_reset_fifo : in std_logic_array_16xbl_reset_fifo:=(others=>'0');
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---- Çàïðîñû DMA îò êàæäîé òåòðàäû ----
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trd_drq : in std_logic_array_16xbl_drq:=(others=>(others=>'0'));
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---- Èñòî÷íèêè ïðåðûâàíèé è DRQ ----
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int1 : in std_logic:='0';
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drq0 : in bl_drq:=('0', '0', '0');
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drq1 : in bl_drq:=('0', '0', '0');
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drq2 : in bl_drq:=('0', '0', '0');
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drq3 : in bl_drq:=('0', '0', '0');
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---- Âûõîä DRQ è IRQ ----
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irq1 : out std_logic;
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dmar0 : out std_logic;
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dmar1 : out std_logic;
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dmar2 : out std_logic;
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dmar3 : out std_logic
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);
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end pb_adm_ctrl_m2;
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architecture pb_adm_ctrl_m2 of pb_adm_ctrl_m2 is
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component ctrl_dram256x16_v2 is
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port (
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addra: in std_logic_vector(7 downto 0);
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addrb: in std_logic_vector(7 downto 0);
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clka: in std_logic;
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clkb: in std_logic;
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dina: in std_logic_vector(15 downto 0);
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doutb: out std_logic_vector(15 downto 0);
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sinita: in std_logic;
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ena: in std_logic;
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enb: in std_logic;
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wea: in std_logic);
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end component;
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component RAMB16_S18
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-- synopsys translate_off
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generic (
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WRITE_MODE : string := "WRITE_FIRST";
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INIT : bit_vector := X"00000";
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SRVAL : bit_vector := X"00000";
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INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
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303 |
|
|
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
304 |
|
|
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
305 |
|
|
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
306 |
|
|
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
307 |
|
|
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
308 |
|
|
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
309 |
|
|
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
310 |
|
|
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
311 |
|
|
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
312 |
|
|
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
313 |
|
|
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
314 |
|
|
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
315 |
|
|
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
316 |
|
|
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
317 |
|
|
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
318 |
|
|
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
319 |
|
|
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
320 |
|
|
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
321 |
|
|
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
322 |
|
|
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
323 |
|
|
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
324 |
|
|
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
325 |
|
|
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
326 |
|
|
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
327 |
|
|
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
328 |
|
|
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
329 |
|
|
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
330 |
|
|
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
331 |
|
|
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
332 |
|
|
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
333 |
|
|
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
334 |
|
|
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
335 |
|
|
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
336 |
|
|
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
337 |
|
|
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
338 |
|
|
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
339 |
|
|
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
340 |
|
|
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
341 |
|
|
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
342 |
|
|
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
343 |
|
|
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
344 |
|
|
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
345 |
|
|
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
346 |
|
|
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
347 |
|
|
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
348 |
|
|
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
349 |
|
|
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
|
350 |
|
|
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
|
351 |
|
|
);
|
352 |
|
|
-- synopsys translate_on
|
353 |
|
|
port (
|
354 |
|
|
DO : out STD_LOGIC_VECTOR (15 downto 0);
|
355 |
|
|
DOP : out STD_LOGIC_VECTOR (1 downto 0);
|
356 |
|
|
ADDR : in STD_LOGIC_VECTOR (9 downto 0);
|
357 |
|
|
CLK : in STD_ULOGIC;
|
358 |
|
|
DI : in STD_LOGIC_VECTOR (15 downto 0);
|
359 |
|
|
DIP : in STD_LOGIC_VECTOR (1 downto 0);
|
360 |
|
|
EN : in STD_ULOGIC;
|
361 |
|
|
SSR : in STD_ULOGIC;
|
362 |
|
|
WE : in STD_ULOGIC
|
363 |
|
|
);
|
364 |
|
|
end component;
|
365 |
|
|
|
366 |
|
|
component ctrl_adsp_v2_decode_data_cs is
|
367 |
|
|
generic(
|
368 |
|
|
trd : in integer; -- íîìåð òåòðàäû
|
369 |
|
|
reg : in integer -- íîìåð ðåãèñòðà
|
370 |
|
|
-- 0 - STATUS
|
371 |
|
|
-- 1 - DATA
|
372 |
|
|
-- 2 - CMD_ADR
|
373 |
|
|
-- 3 - CMD_DATA
|
374 |
|
|
);
|
375 |
|
|
port (
|
376 |
|
|
reset : in std_logic; -- 0 - ñáðîñ
|
377 |
|
|
clk : in std_logic; -- òàêòîâàÿ ÷àñòîòà
|
378 |
|
|
cmd_data_en : in std_logic; -- 1 - ðàçðåøåíèå äåêîäèðîâàíèÿ CMD_DATA
|
379 |
|
|
adr : in std_logic_vector( 4 downto 0 ); -- øèíà àäðåñà
|
380 |
|
|
rd : in std_logic; -- 0 - ÷òåíèå äàííûõ
|
381 |
|
|
data_cs : out std_logic -- 0 - ÷òåíèå äàííûõ
|
382 |
|
|
);
|
383 |
|
|
end component;
|
384 |
|
|
|
385 |
|
|
component ctrl_adsp_v2_decode_data_in_cs is
|
386 |
|
|
port (
|
387 |
|
|
reset : in std_logic; -- 0 - ñáðîñ
|
388 |
|
|
clk : in std_logic; -- òàêòîâàÿ ÷àñòîòà
|
389 |
|
|
cmd_adr : in std_logic_vector( 9 downto 8 ); -- êîñâåííûé àäðåñ
|
390 |
|
|
adr : in std_logic_vector( 4 downto 0 ); -- øèíà àäðåñà
|
391 |
|
|
rd : in std_logic; -- 0 - ÷òåíèå äàííûõ
|
392 |
|
|
data_cs : out std_logic -- 0 - ÷òåíèå äàííûõ
|
393 |
|
|
);
|
394 |
|
|
end component;
|
395 |
|
|
|
396 |
|
|
|
397 |
|
|
component ctrl_adsp_v2_decode_ram_cs is
|
398 |
|
|
generic (
|
399 |
|
|
reg : in integer -- íîìåð ðåãèñòðà
|
400 |
|
|
-- 0 - RAM
|
401 |
|
|
-- 1 - ROM
|
402 |
|
|
);
|
403 |
|
|
port (
|
404 |
|
|
reset : in std_logic; -- 0 - ñáðîñ
|
405 |
|
|
clk : in std_logic; -- òàêòîâàÿ ÷àñòîòà
|
406 |
|
|
cmd_adr : in std_logic_vector( 9 downto 8 ); -- êîñâåííûé àäðåñ
|
407 |
|
|
adr : in std_logic_vector( 4 downto 0 ); -- øèíà àäðåñà
|
408 |
|
|
rd : in std_logic; -- 0 - ÷òåíèå äàííûõ
|
409 |
|
|
data_cs : out std_logic -- 0 - ÷òåíèå äàííûõ
|
410 |
|
|
);
|
411 |
|
|
end component;
|
412 |
|
|
|
413 |
|
|
component ctrl_adsp_v2_decode_data_we is
|
414 |
|
|
generic(
|
415 |
|
|
trd : in integer; -- íîìåð òåòðàäû
|
416 |
|
|
reg : in integer -- íîìåð ðåãèñòðà
|
417 |
|
|
-- 0 - STATUS
|
418 |
|
|
-- 1 - DATA
|
419 |
|
|
-- 2 - CMD_ADR
|
420 |
|
|
-- 3 - CMD_DATA
|
421 |
|
|
);
|
422 |
|
|
port (
|
423 |
|
|
reset : in std_logic; -- 0 - ñáðîñ
|
424 |
|
|
clk : in std_logic; -- òàêòîâàÿ ÷àñòîòà
|
425 |
|
|
adr : in std_logic_vector( 4 downto 0 ); -- øèíà àäðåñà
|
426 |
|
|
wr : in std_logic; -- 0 - çàïèñü äàííûõ
|
427 |
|
|
data_we : out std_logic -- 1 - çàïèñü äàííûõ
|
428 |
|
|
);
|
429 |
|
|
end component;
|
430 |
|
|
|
431 |
|
|
|
432 |
|
|
component ctrl_adsp_v2_decode_cmd_adr_cs is
|
433 |
|
|
port (
|
434 |
|
|
reset : in std_logic; -- 0 - ñáðîñ
|
435 |
|
|
clk : in std_logic; -- òàêòîâàÿ ÷àñòîòà
|
436 |
|
|
adr : in std_logic_vector( 4 downto 0 ); -- øèíà àäðåñà
|
437 |
|
|
rd : in std_logic; -- 0 - ÷òåíèå äàííûõ
|
438 |
|
|
data_cs : out std_logic -- 0 - ÷òåíèå äàííûõ
|
439 |
|
|
);
|
440 |
|
|
end component;
|
441 |
|
|
|
442 |
|
|
|
443 |
|
|
|
444 |
|
|
component ctrl_mux8x48 is
|
445 |
|
|
port (
|
446 |
|
|
ma: in std_logic_vector(47 downto 0);
|
447 |
|
|
mb: in std_logic_vector(47 downto 0);
|
448 |
|
|
mc: in std_logic_vector(47 downto 0);
|
449 |
|
|
md: in std_logic_vector(47 downto 0);
|
450 |
|
|
me: in std_logic_vector(47 downto 0);
|
451 |
|
|
mf: in std_logic_vector(47 downto 0);
|
452 |
|
|
mg: in std_logic_vector(47 downto 0);
|
453 |
|
|
mh: in std_logic_vector(47 downto 0);
|
454 |
|
|
s: in std_logic_vector(2 downto 0);
|
455 |
|
|
o: out std_logic_vector(47 downto 0));
|
456 |
|
|
end component;
|
457 |
|
|
|
458 |
|
|
|
459 |
|
|
component ctrl_mux16x16 is
|
460 |
|
|
port (
|
461 |
|
|
ma: in std_logic_vector(15 downto 0);
|
462 |
|
|
mb: in std_logic_vector(15 downto 0);
|
463 |
|
|
mc: in std_logic_vector(15 downto 0);
|
464 |
|
|
md: in std_logic_vector(15 downto 0);
|
465 |
|
|
me: in std_logic_vector(15 downto 0);
|
466 |
|
|
mf: in std_logic_vector(15 downto 0);
|
467 |
|
|
mg: in std_logic_vector(15 downto 0);
|
468 |
|
|
mh: in std_logic_vector(15 downto 0);
|
469 |
|
|
maa: in std_logic_vector(15 downto 0);
|
470 |
|
|
mab: in std_logic_vector(15 downto 0);
|
471 |
|
|
mac: in std_logic_vector(15 downto 0);
|
472 |
|
|
mad: in std_logic_vector(15 downto 0);
|
473 |
|
|
mae: in std_logic_vector(15 downto 0);
|
474 |
|
|
maf: in std_logic_vector(15 downto 0);
|
475 |
|
|
mag: in std_logic_vector(15 downto 0);
|
476 |
|
|
mah: in std_logic_vector(15 downto 0);
|
477 |
|
|
s: in std_logic_vector(3 downto 0);
|
478 |
|
|
o: out std_logic_vector(15 downto 0));
|
479 |
|
|
end component;
|
480 |
|
|
|
481 |
|
|
component ctrl_mux8x16r is
|
482 |
|
|
port (
|
483 |
|
|
ma: in std_logic_vector(15 downto 0);
|
484 |
|
|
mb: in std_logic_vector(15 downto 0);
|
485 |
|
|
mc: in std_logic_vector(15 downto 0);
|
486 |
|
|
md: in std_logic_vector(15 downto 0);
|
487 |
|
|
me: in std_logic_vector(15 downto 0);
|
488 |
|
|
mf: in std_logic_vector(15 downto 0);
|
489 |
|
|
mg: in std_logic_vector(15 downto 0);
|
490 |
|
|
mh: in std_logic_vector(15 downto 0);
|
491 |
|
|
s: in std_logic_vector(2 downto 0);
|
492 |
|
|
q: out std_logic_vector(15 downto 0);
|
493 |
|
|
clk: in std_logic);
|
494 |
|
|
end component;
|
495 |
|
|
|
496 |
|
|
|
497 |
|
|
--component s_delay is
|
498 |
|
|
-- port(
|
499 |
|
|
-- i : in std_logic; -- âõîäíîé ñèãíàë
|
500 |
|
|
-- o : out std_logic -- âûõîäíîé ñèãíàä
|
501 |
|
|
-- );
|
502 |
|
|
--end component;
|
503 |
|
|
|
504 |
|
|
-- XST black box declaration
|
505 |
|
|
--attribute box_type : string;
|
506 |
|
|
--attribute BOX_TYPE of RAMB16_S18 : component is "BLACK_BOX";
|
507 |
|
|
|
508 |
|
|
|
509 |
|
|
|
510 |
|
|
signal ms1 : std_logic;
|
511 |
|
|
signal wrl1, wrl2, rd1, rd2: std_logic;
|
512 |
|
|
signal adr1, adr2 : std_logic_vector( 6 downto 0 );
|
513 |
|
|
signal data2 : std_logic_vector( 63 downto 0 );
|
514 |
|
|
signal rd2z : std_logic;
|
515 |
|
|
|
516 |
|
|
signal data_out2 : std_logic_vector( 63 downto 0 );
|
517 |
|
|
|
518 |
|
|
|
519 |
|
|
|
520 |
|
|
signal cmd_data2 : std_logic_vector( 15 downto 0 );
|
521 |
|
|
signal rom_data2 : std_logic_vector( 15 downto 0 );
|
522 |
|
|
signal sinit, dpram_en : std_logic;
|
523 |
|
|
signal dpram_en0 : std_logic;
|
524 |
|
|
signal addra : std_logic_vector( 9 downto 0 );
|
525 |
|
|
signal addra2 : std_logic_vector( 15 downto 0 );
|
526 |
|
|
signal dpram_cs2 : std_logic;
|
527 |
|
|
|
528 |
|
|
signal bl_status_cs : std_logic_vector( 7 downto 0 );
|
529 |
|
|
signal bl_data_cs : std_logic_vector( 7 downto 0 );
|
530 |
|
|
signal bl_cmd_data_cs : std_logic_vector( 7 downto 0 );
|
531 |
|
|
|
532 |
|
|
signal bl_data_we : std_logic_vector( 7 downto 0 );
|
533 |
|
|
signal bl_cmd_adr_we : std_logic_vector( 7 downto 0 );
|
534 |
|
|
signal bl_cmd_adr_we1 : std_logic_vector( 7 downto 0 );
|
535 |
|
|
signal bl_cmd_data_we : std_logic_vector( 7 downto 0 );
|
536 |
|
|
signal bl_cmd_data_we1 : std_logic_vector( 7 downto 0 );
|
537 |
|
|
|
538 |
|
|
signal ram_cs1, ram_cs2 : std_logic;
|
539 |
|
|
signal rom_cs2 : std_logic;
|
540 |
|
|
signal data_in_cs2 : std_logic;
|
541 |
|
|
signal data_in_cs2_0 : std_logic;
|
542 |
|
|
signal cmd_adr_cs2 : std_logic;
|
543 |
|
|
|
544 |
|
|
signal cmd0_adr, cmd1_adr, cmd2_adr, cmd3_adr: std_logic_vector( 15 downto 0 );
|
545 |
|
|
signal cmd4_adr, cmd5_adr, cmd6_adr, cmd7_adr: std_logic_vector( 15 downto 0 );
|
546 |
|
|
|
547 |
|
|
signal rom_di : std_logic_vector( 15 downto 0 );
|
548 |
|
|
|
549 |
|
|
signal sel_cmd_data : std_logic; -- 1 - ÷òåíèå íåïîñðåäñòâåííûõ ðåãèñòðîâ
|
550 |
|
|
signal sel_cmd_ram : std_logic; -- 1 - ÷òåíèå êîìàíäíûõ ðåãèñòðîâ
|
551 |
|
|
signal sel_cmd_rom : std_logic; -- 1 - ÷òåíèå êîíñòàíò
|
552 |
|
|
|
553 |
|
|
signal flyby1 : std_logic; -- 1 - âûïîëíåíèå öèêëà DMA
|
554 |
|
|
signal ram_rom_cs : std_logic;
|
555 |
|
|
signal en_ram : std_logic;
|
556 |
|
|
|
557 |
|
|
|
558 |
|
|
signal ma, mb, mc, md, me, mf, mg, mh : std_logic_vector( 63 downto 0 );
|
559 |
|
|
signal maa, mab, mac, mad, mae, maf, mag, mah : std_logic_vector( 15 downto 0 );
|
560 |
|
|
|
561 |
|
|
signal na, nb, nc, nd, ne, nf, ng, nh : std_logic_vector( 15 downto 0 );
|
562 |
|
|
|
563 |
|
|
signal mux_sel : std_logic_vector( 3 downto 0 );
|
564 |
|
|
|
565 |
|
|
signal flyby2 : std_logic;
|
566 |
|
|
signal flag_data_we : std_logic_vector( 7 downto 0 );
|
567 |
|
|
signal main_mode2_4 : std_logic:='0';
|
568 |
|
|
signal trd4i_host_data : std_logic_vector( 63 downto 0 );
|
569 |
|
|
|
570 |
|
|
signal flag_rd_block : std_logic_vector( 15 downto 0 );
|
571 |
|
|
signal flag_rd_repack : std_logic_vector( 15 downto 0 );
|
572 |
|
|
signal trd_repack_data : std_logic_array_16x64:=(others=>(others=>'0'));
|
573 |
|
|
|
574 |
|
|
signal lc_data_i : std_logic_vector( 63 downto 0 );
|
575 |
|
|
|
576 |
|
|
function conv_rom( rom: in bl_trd_rom; mode: integer ) return bit_vector is
|
577 |
|
|
variable ret: bit_vector( 255 downto 0 );
|
578 |
|
|
begin
|
579 |
|
|
for i in 0 to 15 loop
|
580 |
|
|
ret( i*16+15 downto i*16 ):=to_bitvector( rom( i+mode*16 ), '0' );
|
581 |
|
|
end loop;
|
582 |
|
|
return ret;
|
583 |
|
|
end conv_rom;
|
584 |
|
|
|
585 |
|
|
function conv_string( rom: in bl_trd_rom; mode: integer ) return string is
|
586 |
|
|
variable str: string( 64 downto 1 );
|
587 |
|
|
|
588 |
|
|
variable d : std_logic_vector( 15 downto 0 );
|
589 |
|
|
variable c : std_logic_vector( 3 downto 0 );
|
590 |
|
|
variable k : integer;
|
591 |
|
|
begin
|
592 |
|
|
|
593 |
|
|
|
594 |
|
|
|
595 |
|
|
for i in 0 to 15 loop
|
596 |
|
|
d:=rom( i+mode*16 );
|
597 |
|
|
for j in 0 to 3 loop
|
598 |
|
|
c:=d( j*4+3 downto j*4 );
|
599 |
|
|
k:=i*4+j+1;
|
600 |
|
|
case c is
|
601 |
|
|
when x"0" => str(k) := '0';
|
602 |
|
|
when x"1" => str(k) := '1';
|
603 |
|
|
when x"2" => str(k) := '2';
|
604 |
|
|
when x"3" => str(k) := '3';
|
605 |
|
|
when x"4" => str(k) := '4';
|
606 |
|
|
when x"5" => str(k) := '5';
|
607 |
|
|
when x"6" => str(k) := '6';
|
608 |
|
|
when x"7" => str(k) := '7';
|
609 |
|
|
when x"8" => str(k) := '8';
|
610 |
|
|
when x"9" => str(k) := '9';
|
611 |
|
|
when x"A" => str(k) := 'A';
|
612 |
|
|
when x"B" => str(k) := 'B';
|
613 |
|
|
when x"C" => str(k) := 'C';
|
614 |
|
|
when x"D" => str(k) := 'D';
|
615 |
|
|
when x"E" => str(k) := 'E';
|
616 |
|
|
when x"F" => str(k) := 'F';
|
617 |
|
|
when others => null;
|
618 |
|
|
end case;
|
619 |
|
|
end loop;
|
620 |
|
|
end loop;
|
621 |
|
|
|
622 |
|
|
return str;
|
623 |
|
|
end conv_string;
|
624 |
|
|
|
625 |
|
|
|
626 |
|
|
constant rom_init_00 : bit_vector( 255 downto 0 ):= conv_rom( rom0, 0 );
|
627 |
|
|
constant rom_init_01 : bit_vector( 255 downto 0 ):= conv_rom( rom0, 1 );
|
628 |
|
|
constant rom_init_02 : bit_vector( 255 downto 0 ):= conv_rom( rom1, 0 );
|
629 |
|
|
constant rom_init_03 : bit_vector( 255 downto 0 ):= conv_rom( rom1, 1 );
|
630 |
|
|
constant rom_init_04 : bit_vector( 255 downto 0 ):= conv_rom( rom2, 0 );
|
631 |
|
|
constant rom_init_05 : bit_vector( 255 downto 0 ):= conv_rom( rom2, 1 );
|
632 |
|
|
constant rom_init_06 : bit_vector( 255 downto 0 ):= conv_rom( rom3, 0 );
|
633 |
|
|
constant rom_init_07 : bit_vector( 255 downto 0 ):= conv_rom( rom3, 1 );
|
634 |
|
|
constant rom_init_08 : bit_vector( 255 downto 0 ):= conv_rom( rom4, 0 );
|
635 |
|
|
constant rom_init_09 : bit_vector( 255 downto 0 ):= conv_rom( rom4, 1 );
|
636 |
|
|
constant rom_init_0A : bit_vector( 255 downto 0 ):= conv_rom( rom5, 0 );
|
637 |
|
|
constant rom_init_0B : bit_vector( 255 downto 0 ):= conv_rom( rom5, 1 );
|
638 |
|
|
constant rom_init_0C : bit_vector( 255 downto 0 ):= conv_rom( rom6, 0 );
|
639 |
|
|
constant rom_init_0D : bit_vector( 255 downto 0 ):= conv_rom( rom6, 1 );
|
640 |
|
|
constant rom_init_0E : bit_vector( 255 downto 0 ):= conv_rom( rom7, 0 );
|
641 |
|
|
constant rom_init_0F : bit_vector( 255 downto 0 ):= conv_rom( rom7, 1 );
|
642 |
|
|
|
643 |
|
|
|
644 |
|
|
|
645 |
|
|
constant str_init_00 : string:= conv_string( rom0, 0 );
|
646 |
|
|
constant str_init_01 : string:= conv_string( rom0, 1 );
|
647 |
|
|
constant str_init_02 : string:= conv_string( rom1, 0 );
|
648 |
|
|
constant str_init_03 : string:= conv_string( rom1, 1 );
|
649 |
|
|
constant str_init_04 : string:= conv_string( rom2, 0 );
|
650 |
|
|
constant str_init_05 : string:= conv_string( rom2, 1 );
|
651 |
|
|
constant str_init_06 : string:= conv_string( rom3, 0 );
|
652 |
|
|
constant str_init_07 : string:= conv_string( rom3, 1 );
|
653 |
|
|
constant str_init_08 : string:= conv_string( rom4, 0 );
|
654 |
|
|
constant str_init_09 : string:= conv_string( rom4, 1 );
|
655 |
|
|
constant str_init_0A : string:= conv_string( rom5, 0 );
|
656 |
|
|
constant str_init_0B : string:= conv_string( rom5, 1 );
|
657 |
|
|
constant str_init_0C : string:= conv_string( rom6, 0 );
|
658 |
|
|
constant str_init_0D : string:= conv_string( rom6, 1 );
|
659 |
|
|
constant str_init_0E : string:= conv_string( rom7, 0 );
|
660 |
|
|
constant str_init_0F : string:= conv_string( rom7, 1 );
|
661 |
|
|
|
662 |
|
|
|
663 |
|
|
attribute rom_style : string;
|
664 |
|
|
attribute rom_style of rom : label is "block";
|
665 |
|
|
|
666 |
|
|
attribute init_10 : string;
|
667 |
|
|
attribute init_11 : string;
|
668 |
|
|
attribute init_12 : string;
|
669 |
|
|
attribute init_13 : string;
|
670 |
|
|
attribute init_14 : string;
|
671 |
|
|
attribute init_15 : string;
|
672 |
|
|
attribute init_16 : string;
|
673 |
|
|
attribute init_17 : string;
|
674 |
|
|
attribute init_18 : string;
|
675 |
|
|
attribute init_19 : string;
|
676 |
|
|
attribute init_1A : string;
|
677 |
|
|
attribute init_1B : string;
|
678 |
|
|
attribute init_1C : string;
|
679 |
|
|
attribute init_1D : string;
|
680 |
|
|
attribute init_1E : string;
|
681 |
|
|
attribute init_1F : string;
|
682 |
|
|
|
683 |
|
|
attribute init_10 of rom : label is str_init_00;
|
684 |
|
|
attribute init_11 of rom : label is str_init_01;
|
685 |
|
|
attribute init_12 of rom : label is str_init_02;
|
686 |
|
|
attribute init_13 of rom : label is str_init_03;
|
687 |
|
|
attribute init_14 of rom : label is str_init_04;
|
688 |
|
|
attribute init_15 of rom : label is str_init_05;
|
689 |
|
|
attribute init_16 of rom : label is str_init_06;
|
690 |
|
|
attribute init_17 of rom : label is str_init_07;
|
691 |
|
|
attribute init_18 of rom : label is str_init_08;
|
692 |
|
|
attribute init_19 of rom : label is str_init_09;
|
693 |
|
|
attribute init_1A of rom : label is str_init_0A;
|
694 |
|
|
attribute init_1B of rom : label is str_init_0B;
|
695 |
|
|
attribute init_1C of rom : label is str_init_0C;
|
696 |
|
|
attribute init_1D of rom : label is str_init_0D;
|
697 |
|
|
attribute init_1E of rom : label is str_init_0E;
|
698 |
|
|
attribute init_1F of rom : label is str_init_0F;
|
699 |
|
|
|
700 |
|
|
begin
|
701 |
|
|
|
702 |
|
|
|
703 |
|
|
rd1<= not lc_rd;
|
704 |
|
|
|
705 |
|
|
wrl1<= not lc_wr;
|
706 |
|
|
|
707 |
|
|
pr_ms2: process( reset, clk ) begin
|
708 |
|
|
if( reset='0' ) then
|
709 |
|
|
wrl2<='1'; rd2<='1';
|
710 |
|
|
elsif( rising_edge( clk ) ) then
|
711 |
|
|
wrl2<=wrl1 after 1 ns; rd2<=rd1 after 1 ns;
|
712 |
|
|
end if;
|
713 |
|
|
end process;
|
714 |
|
|
|
715 |
|
|
|
716 |
|
|
adr1<=lc_adr( 6 downto 0 ) when test_mode='0' else "0000010";
|
717 |
|
|
|
718 |
|
|
pr_adr_in: process( clk ) begin
|
719 |
|
|
if( rising_edge( clk ) ) then
|
720 |
|
|
if( test_mode='1' ) then
|
721 |
|
|
adr2<="0000010";
|
722 |
|
|
else
|
723 |
|
|
adr2<=adr1;
|
724 |
|
|
end if;
|
725 |
|
|
end if;
|
726 |
|
|
end process;
|
727 |
|
|
|
728 |
|
|
data2<=lc_host_data when rising_edge( clk );
|
729 |
|
|
trd_host_data<=data2;
|
730 |
|
|
|
731 |
|
|
pr_bl_adr_out: process( clk ) begin
|
732 |
|
|
if( rising_edge( clk ) ) then
|
733 |
|
|
trd_host_adr( 6 downto 0 )<=lc_adr( 6 downto 0 );
|
734 |
|
|
end if;
|
735 |
|
|
end process;
|
736 |
|
|
|
737 |
|
|
rom: RAMB16_S18
|
738 |
|
|
-- synopsys translate_off
|
739 |
|
|
generic map (
|
740 |
|
|
INIT_10 => rom_init_00,
|
741 |
|
|
INIT_11 => rom_init_01,
|
742 |
|
|
INIT_12 => rom_init_02,
|
743 |
|
|
INIT_13 => rom_init_03,
|
744 |
|
|
INIT_14 => rom_init_04,
|
745 |
|
|
INIT_15 => rom_init_05,
|
746 |
|
|
INIT_16 => rom_init_06,
|
747 |
|
|
INIT_17 => rom_init_07,
|
748 |
|
|
INIT_18 => rom_init_08,
|
749 |
|
|
INIT_19 => rom_init_09,
|
750 |
|
|
INIT_1A => rom_init_0A,
|
751 |
|
|
INIT_1B => rom_init_0B,
|
752 |
|
|
INIT_1C => rom_init_0C,
|
753 |
|
|
INIT_1D => rom_init_0D,
|
754 |
|
|
INIT_1E => rom_init_0E,
|
755 |
|
|
INIT_1F => rom_init_0F
|
756 |
|
|
)
|
757 |
|
|
-- synopsys translate_on
|
758 |
|
|
port map (
|
759 |
|
|
DO => rom_data2,
|
760 |
|
|
ADDR(8 downto 0) => addra( 8 downto 0 ),
|
761 |
|
|
ADDR(9) => '0',
|
762 |
|
|
CLK => clk,
|
763 |
|
|
DI => data2( 15 downto 0 ),
|
764 |
|
|
DIP => "00",
|
765 |
|
|
EN => '1',
|
766 |
|
|
SSR => '0',
|
767 |
|
|
WE => dpram_en
|
768 |
|
|
);
|
769 |
|
|
|
770 |
|
|
en_ram <= ((dpram_en or ram_cs1) and not (addra(8)) )or (ram_cs1 and addra(8));
|
771 |
|
|
|
772 |
|
|
addra2( 7 downto 5 )<=(others=>'0'); -- íå èñïîëüçóþòñÿ
|
773 |
|
|
addra2( 15 downto 10 )<=(others=>'0'); -- íå èñïîëüçóåòñÿ
|
774 |
|
|
|
775 |
|
|
pr_addra: process( clk )
|
776 |
|
|
variable vsel: bit_vector( 2 downto 0 );
|
777 |
|
|
begin
|
778 |
|
|
vsel:=to_bitvector( adr1( 5 downto 3 ), '0' );
|
779 |
|
|
if( rising_edge( clk ) ) then
|
780 |
|
|
addra( 7 downto 5 )<=adr1( 5 downto 3 );
|
781 |
|
|
ram_cs1<=not rd1;
|
782 |
|
|
case vsel is
|
783 |
|
|
when "000" =>
|
784 |
|
|
addra( 4 downto 0 )<=cmd0_adr( 4 downto 0 );
|
785 |
|
|
addra( 9 downto 8 )<=cmd0_adr( 9 downto 8 );
|
786 |
|
|
when "001" =>
|
787 |
|
|
addra( 4 downto 0 )<=cmd1_adr( 4 downto 0 );
|
788 |
|
|
addra( 9 downto 8 )<=cmd1_adr( 9 downto 8);
|
789 |
|
|
when "010" =>
|
790 |
|
|
addra( 4 downto 0 )<=cmd2_adr( 4 downto 0 );
|
791 |
|
|
addra( 9 downto 8 )<=cmd2_adr( 9 downto 8);
|
792 |
|
|
when "011" =>
|
793 |
|
|
addra( 4 downto 0 )<=cmd3_adr( 4 downto 0 );
|
794 |
|
|
addra( 9 downto 8 )<=cmd3_adr( 9 downto 8);
|
795 |
|
|
when "100" =>
|
796 |
|
|
addra( 4 downto 0 )<=cmd4_adr( 4 downto 0 );
|
797 |
|
|
addra( 9 downto 8 )<=cmd4_adr( 9 downto 8);
|
798 |
|
|
when "101" =>
|
799 |
|
|
addra( 4 downto 0 )<=cmd5_adr( 4 downto 0 );
|
800 |
|
|
addra( 9 downto 8 )<=cmd5_adr( 9 downto 8);
|
801 |
|
|
when "110" =>
|
802 |
|
|
addra( 4 downto 0 )<=cmd6_adr( 4 downto 0 );
|
803 |
|
|
addra( 9 downto 8 )<=cmd6_adr( 9 downto 8);
|
804 |
|
|
when "111" =>
|
805 |
|
|
addra( 4 downto 0 )<=cmd7_adr( 4 downto 0 );
|
806 |
|
|
addra( 9 downto 8 )<=cmd7_adr( 9 downto 8);
|
807 |
|
|
end case;
|
808 |
|
|
addra2( 9 downto 8 )<=addra( 9 downto 8 );
|
809 |
|
|
addra2( 4 downto 0 )<=addra( 4 downto 0 );
|
810 |
|
|
end if;
|
811 |
|
|
end process;
|
812 |
|
|
|
813 |
|
|
pr_dpram_en: process( clk )
|
814 |
|
|
variable ven: std_logic;
|
815 |
|
|
begin
|
816 |
|
|
ven:='0';
|
817 |
|
|
if( rising_edge( clk ) ) then
|
818 |
|
|
if( test_mode='0' ) then
|
819 |
|
|
if( wrl1='0' and adr1(2)='1' and adr1(1)='1' ) then ven:='1'; end if;
|
820 |
|
|
end if;
|
821 |
|
|
dpram_en0<=ven;
|
822 |
|
|
end if;
|
823 |
|
|
end process;
|
824 |
|
|
|
825 |
|
|
dpram_en <='1' when dpram_en0='1' and addra(9)='0' and addra(8)='0' else '0';
|
826 |
|
|
|
827 |
|
|
|
828 |
|
|
rd2z <= rd2 after 1 ns when rising_edge( clk );
|
829 |
|
|
gen_data_cs: for i in 0 to 7 generate
|
830 |
|
|
|
831 |
|
|
xstatus: ctrl_adsp_v2_decode_data_cs
|
832 |
|
|
generic map( trd=>i, reg=>0 )
|
833 |
|
|
port map (
|
834 |
|
|
reset => reset,
|
835 |
|
|
clk => clk,
|
836 |
|
|
cmd_data_en =>'0',
|
837 |
|
|
adr => adr1(5 downto 1),
|
838 |
|
|
rd => rd1,
|
839 |
|
|
data_cs => bl_status_cs(i)
|
840 |
|
|
);
|
841 |
|
|
|
842 |
|
|
xdata: ctrl_adsp_v2_decode_data_cs
|
843 |
|
|
generic map( trd=>i, reg=>1 )
|
844 |
|
|
port map (
|
845 |
|
|
reset => reset,
|
846 |
|
|
clk => clk,
|
847 |
|
|
cmd_data_en =>'0',
|
848 |
|
|
adr => adr2(5 downto 1),
|
849 |
|
|
rd => rd2z,
|
850 |
|
|
data_cs => bl_data_cs(i)
|
851 |
|
|
);
|
852 |
|
|
|
853 |
|
|
|
854 |
|
|
xcmd_data: ctrl_adsp_v2_decode_data_cs
|
855 |
|
|
generic map( trd=>i, reg=>3 )
|
856 |
|
|
port map(
|
857 |
|
|
reset => reset,
|
858 |
|
|
clk => clk,
|
859 |
|
|
cmd_data_en =>sel_cmd_data,
|
860 |
|
|
adr => adr1( 5 downto 1 ),
|
861 |
|
|
rd => rd1,
|
862 |
|
|
data_cs => bl_cmd_data_cs(i)
|
863 |
|
|
);
|
864 |
|
|
|
865 |
|
|
xdata_we: ctrl_adsp_v2_decode_data_we
|
866 |
|
|
generic map( trd=>i, reg=>1 )
|
867 |
|
|
port map(
|
868 |
|
|
reset => reset,
|
869 |
|
|
clk => clk,
|
870 |
|
|
adr => adr1( 5 downto 1 ),
|
871 |
|
|
wr => wrl1,
|
872 |
|
|
data_we => bl_data_we(i)
|
873 |
|
|
);
|
874 |
|
|
|
875 |
|
|
xcmd_adr_we: ctrl_adsp_v2_decode_data_we
|
876 |
|
|
generic map( trd=>i, reg=>2 )
|
877 |
|
|
port map(
|
878 |
|
|
reset => reset,
|
879 |
|
|
clk => clk,
|
880 |
|
|
adr => adr1( 5 downto 1 ),
|
881 |
|
|
wr => wrl1,
|
882 |
|
|
data_we => bl_cmd_adr_we(i)
|
883 |
|
|
);
|
884 |
|
|
|
885 |
|
|
xcmd_data_we: ctrl_adsp_v2_decode_data_we
|
886 |
|
|
generic map( trd=>i, reg=>3 )
|
887 |
|
|
port map(
|
888 |
|
|
reset => reset,
|
889 |
|
|
clk => clk,
|
890 |
|
|
adr => adr1( 5 downto 1 ),
|
891 |
|
|
wr => wrl1,
|
892 |
|
|
data_we => bl_cmd_data_we(i)
|
893 |
|
|
);
|
894 |
|
|
|
895 |
|
|
|
896 |
|
|
end generate;
|
897 |
|
|
|
898 |
|
|
xcmd_ram: ctrl_adsp_v2_decode_ram_cs
|
899 |
|
|
generic map( reg => 0 )
|
900 |
|
|
port map (
|
901 |
|
|
reset => reset,
|
902 |
|
|
clk => clk,
|
903 |
|
|
cmd_adr => addra( 9 downto 8 ),
|
904 |
|
|
adr => adr2( 5 downto 1 ),
|
905 |
|
|
rd => rd2,
|
906 |
|
|
data_cs => ram_cs2
|
907 |
|
|
);
|
908 |
|
|
|
909 |
|
|
xcmd_rom: ctrl_adsp_v2_decode_ram_cs
|
910 |
|
|
generic map( reg => 1 )
|
911 |
|
|
port map (
|
912 |
|
|
reset => reset,
|
913 |
|
|
clk => clk,
|
914 |
|
|
cmd_adr => addra( 9 downto 8 ),
|
915 |
|
|
adr => adr2( 5 downto 1 ),
|
916 |
|
|
rd => rd2,
|
917 |
|
|
data_cs => rom_cs2
|
918 |
|
|
);
|
919 |
|
|
|
920 |
|
|
|
921 |
|
|
xcmd_adr: ctrl_adsp_v2_decode_cmd_adr_cs
|
922 |
|
|
port map(
|
923 |
|
|
reset => reset,
|
924 |
|
|
clk => clk,
|
925 |
|
|
adr => adr2( 5 downto 1 ),
|
926 |
|
|
rd => rd2,
|
927 |
|
|
data_cs => cmd_adr_cs2
|
928 |
|
|
);
|
929 |
|
|
|
930 |
|
|
--sel_cmd_data <= addra(9);
|
931 |
|
|
sel_cmd_ram <= '1' when addra(9)='0' and addra(8)='0' else '0';
|
932 |
|
|
sel_cmd_rom <= '1' when addra(9)='0' and addra(8)='1' else '0';
|
933 |
|
|
|
934 |
|
|
pr_sel_cmd_data: process( adr1, cmd0_adr, cmd1_adr, cmd2_adr, cmd3_adr,
|
935 |
|
|
cmd4_adr, cmd5_adr, cmd6_adr, cmd7_adr )
|
936 |
|
|
variable vsel: bit_vector( 2 downto 0 );
|
937 |
|
|
begin
|
938 |
|
|
vsel:=to_bitvector( adr1( 5 downto 3 ), '0' );
|
939 |
|
|
case vsel is
|
940 |
|
|
when "000" => sel_cmd_data <= cmd0_adr( 9 );
|
941 |
|
|
when "001" => sel_cmd_data <= cmd1_adr( 9 );
|
942 |
|
|
when "010" => sel_cmd_data <= cmd2_adr( 9 );
|
943 |
|
|
when "011" => sel_cmd_data <= cmd3_adr( 9 );
|
944 |
|
|
when "100" => sel_cmd_data <= cmd4_adr( 9 );
|
945 |
|
|
when "101" => sel_cmd_data <= cmd5_adr( 9 );
|
946 |
|
|
when "110" => sel_cmd_data <= cmd6_adr( 9 );
|
947 |
|
|
when "111" => sel_cmd_data <= cmd7_adr( 9 );
|
948 |
|
|
end case;
|
949 |
|
|
end process;
|
950 |
|
|
|
951 |
|
|
|
952 |
|
|
pr_cmd_adr: process( reset, clk ) begin
|
953 |
|
|
if( reset='0' ) then
|
954 |
|
|
cmd0_adr<=(others=>'0');
|
955 |
|
|
cmd1_adr<=(others=>'0');
|
956 |
|
|
cmd2_adr<=(others=>'0');
|
957 |
|
|
cmd3_adr<=(others=>'0');
|
958 |
|
|
cmd4_adr<=(others=>'0');
|
959 |
|
|
cmd5_adr<=(others=>'0');
|
960 |
|
|
cmd6_adr<=(others=>'0');
|
961 |
|
|
cmd7_adr<=(others=>'0');
|
962 |
|
|
elsif( rising_edge( clk ) ) then
|
963 |
|
|
if( bl_cmd_adr_we(0)='1' ) then cmd0_adr( 9 downto 0 )<=data2( 9 downto 0 ); end if;
|
964 |
|
|
if( bl_cmd_adr_we(1)='1' ) then cmd1_adr( 9 downto 0 )<=data2( 9 downto 0 ); end if;
|
965 |
|
|
if( bl_cmd_adr_we(2)='1' ) then cmd2_adr( 9 downto 0 )<=data2( 9 downto 0 ); end if;
|
966 |
|
|
if( bl_cmd_adr_we(3)='1' ) then cmd3_adr( 9 downto 0 )<=data2( 9 downto 0 ); end if;
|
967 |
|
|
if( bl_cmd_adr_we(4)='1' ) then cmd4_adr( 9 downto 0 )<=data2( 9 downto 0 ); end if;
|
968 |
|
|
if( bl_cmd_adr_we(5)='1' ) then cmd5_adr( 9 downto 0 )<=data2( 9 downto 0 ); end if;
|
969 |
|
|
if( bl_cmd_adr_we(6)='1' ) then cmd6_adr( 9 downto 0 )<=data2( 9 downto 0 ); end if;
|
970 |
|
|
if( bl_cmd_adr_we(7)='1' ) then cmd7_adr( 9 downto 0 )<=data2( 9 downto 0 ); end if;
|
971 |
|
|
end if;
|
972 |
|
|
end process;
|
973 |
|
|
|
974 |
|
|
pr_adr_we1: process( clk ) begin
|
975 |
|
|
if( rising_edge( clk ) ) then
|
976 |
|
|
bl_cmd_adr_we1<=bl_cmd_adr_we;
|
977 |
|
|
end if;
|
978 |
|
|
end process;
|
979 |
|
|
|
980 |
|
|
cmd0_adr( 15 downto 10 ) <= ( others=>'0' );
|
981 |
|
|
cmd1_adr( 15 downto 10 ) <= ( others=>'0' );
|
982 |
|
|
cmd2_adr( 15 downto 10 ) <= ( others=>'0' );
|
983 |
|
|
cmd3_adr( 15 downto 10 ) <= ( others=>'0' );
|
984 |
|
|
cmd4_adr( 15 downto 10 ) <= ( others=>'0' );
|
985 |
|
|
cmd5_adr( 15 downto 10 ) <= ( others=>'0' );
|
986 |
|
|
cmd6_adr( 15 downto 10 ) <= ( others=>'0' );
|
987 |
|
|
cmd7_adr( 15 downto 10 ) <= ( others=>'0' );
|
988 |
|
|
|
989 |
|
|
ram_rom_cs <= ram_cs2 and rom_cs2;
|
990 |
|
|
|
991 |
|
|
|
992 |
|
|
pr_irq: process( clk ) begin
|
993 |
|
|
if( rising_edge( clk ) ) then
|
994 |
|
|
irq1 <= int1;
|
995 |
|
|
end if;
|
996 |
|
|
end process;
|
997 |
|
|
|
998 |
|
|
|
999 |
|
|
dmar0 <= '1' when drq0.en='1' and drq0.req='1' else '0';
|
1000 |
|
|
dmar1 <= '1' when drq1.en='1' and drq1.req='1' else '0';
|
1001 |
|
|
dmar2 <= '1' when drq2.en='1' and drq2.req='1' else '0';
|
1002 |
|
|
dmar3 <= '1' when drq3.en='1' and drq3.req='1' else '0';
|
1003 |
|
|
|
1004 |
|
|
--
|
1005 |
|
|
--gen_cmd_data_we: for i in 0 to 7 generate
|
1006 |
|
|
--
|
1007 |
|
|
--xcmd_data_we: s_delay port map( o=>bl_cmd_data_we1(i), i=>bl_cmd_data_we(i) );
|
1008 |
|
|
--
|
1009 |
|
|
--end generate;
|
1010 |
|
|
--
|
1011 |
|
|
|
1012 |
|
|
bl_cmd_data_we1 <= bl_cmd_data_we;
|
1013 |
|
|
|
1014 |
|
|
gen_trd_cmd: for i in 0 to 7 generate
|
1015 |
|
|
|
1016 |
|
|
trd_host_cmd(i).data_we <=bl_data_we(i) and flag_data_we(i);
|
1017 |
|
|
trd_host_cmd(i).cmd_data_we <=bl_cmd_data_we1(i);
|
1018 |
|
|
trd_host_cmd(i).status_cs <=bl_status_cs(i);
|
1019 |
|
|
trd_host_cmd(i).data_cs <=bl_data_cs(i) or flag_rd_block(i); --flag_rd_repack(i);
|
1020 |
|
|
trd_host_cmd(i).data_oe <=bl_data_cs(i);
|
1021 |
|
|
trd_host_cmd(i).cmd_data_cs <=bl_cmd_data_cs(i);
|
1022 |
|
|
trd_host_cmd(i).cmd_adr_we <=bl_cmd_adr_we1(i);
|
1023 |
|
|
|
1024 |
|
|
end generate;
|
1025 |
|
|
|
1026 |
|
|
trd_host_cmd(0).adr <=cmd0_adr( 9 downto 0 );
|
1027 |
|
|
trd_host_cmd(1).adr <=cmd1_adr( 9 downto 0 );
|
1028 |
|
|
trd_host_cmd(2).adr <=cmd2_adr( 9 downto 0 );
|
1029 |
|
|
trd_host_cmd(3).adr <=cmd3_adr( 9 downto 0 );
|
1030 |
|
|
trd_host_cmd(4).adr <=cmd4_adr( 9 downto 0 );
|
1031 |
|
|
trd_host_cmd(5).adr <=cmd5_adr( 9 downto 0 );
|
1032 |
|
|
trd_host_cmd(6).adr <=cmd6_adr( 9 downto 0 );
|
1033 |
|
|
trd_host_cmd(7).adr <=cmd7_adr( 9 downto 0 );
|
1034 |
|
|
|
1035 |
|
|
|
1036 |
|
|
|
1037 |
|
|
|
1038 |
|
|
|
1039 |
|
|
|
1040 |
|
|
mux8: ctrl_mux8x48
|
1041 |
|
|
port map (
|
1042 |
|
|
ma => ma( 63 downto 16 ),
|
1043 |
|
|
mb => mb( 63 downto 16 ),
|
1044 |
|
|
mc => mc( 63 downto 16 ),
|
1045 |
|
|
md => md( 63 downto 16 ),
|
1046 |
|
|
me => me( 63 downto 16 ),
|
1047 |
|
|
mf => mf( 63 downto 16 ),
|
1048 |
|
|
mg => mg( 63 downto 16 ),
|
1049 |
|
|
mh => mh( 63 downto 16 ),
|
1050 |
|
|
s => mux_sel( 2 downto 0 ),
|
1051 |
|
|
o => lc_data_i( 63 downto 16 ) );
|
1052 |
|
|
|
1053 |
|
|
|
1054 |
|
|
|
1055 |
|
|
mux16: ctrl_mux16x16
|
1056 |
|
|
port map(
|
1057 |
|
|
ma => ma( 15 downto 0 ),
|
1058 |
|
|
mb => mb( 15 downto 0 ),
|
1059 |
|
|
mc => mc( 15 downto 0 ),
|
1060 |
|
|
md => md( 15 downto 0 ),
|
1061 |
|
|
me => me( 15 downto 0 ),
|
1062 |
|
|
mf => mf( 15 downto 0 ),
|
1063 |
|
|
mg => mg( 15 downto 0 ),
|
1064 |
|
|
mh => mh( 15 downto 0 ),
|
1065 |
|
|
maa => maa( 15 downto 0 ),
|
1066 |
|
|
mab => mab( 15 downto 0 ),
|
1067 |
|
|
mac => mac( 15 downto 0 ),
|
1068 |
|
|
mad => mad( 15 downto 0 ),
|
1069 |
|
|
mae => mae( 15 downto 0 ),
|
1070 |
|
|
maf => maf( 15 downto 0 ),
|
1071 |
|
|
mag => mag( 15 downto 0 ),
|
1072 |
|
|
mah => mah( 15 downto 0 ),
|
1073 |
|
|
s => mux_sel( 3 downto 0 ),
|
1074 |
|
|
o => lc_data_i( 15 downto 0 ) );
|
1075 |
|
|
|
1076 |
|
|
lc_data <= lc_data_i after 1 ns when rising_edge( clk );
|
1077 |
|
|
|
1078 |
|
|
ma <= trd_repack_data(0) after 1 ns when rising_edge( clk );
|
1079 |
|
|
|
1080 |
|
|
xd1p: if( trd1_in=1 ) generate mb <= trd_repack_data(1) after 1 ns when rising_edge( clk ); end generate;
|
1081 |
|
|
xd1n: if( trd1_in=0 ) generate mb <= (others=>'0'); end generate;
|
1082 |
|
|
|
1083 |
|
|
xd2p: if( trd2_in=1 ) generate mc <= trd_repack_data(2) after 1 ns when rising_edge( clk ); end generate;
|
1084 |
|
|
xd2n: if( trd2_in=0 ) generate mc <= (others=>'0'); end generate;
|
1085 |
|
|
|
1086 |
|
|
xd3p: if( trd3_in=1 ) generate md <= trd_repack_data(3) after 1 ns when rising_edge( clk ); end generate;
|
1087 |
|
|
xd3n: if( trd3_in=0 ) generate md <= (others=>'0'); end generate;
|
1088 |
|
|
|
1089 |
|
|
xd4p: if( trd4_in=1 ) generate me <= trd_repack_data(4) after 1 ns when rising_edge( clk ); end generate;
|
1090 |
|
|
xd4n: if( trd4_in=0 ) generate me <= (others=>'0'); end generate;
|
1091 |
|
|
|
1092 |
|
|
xd5p: if( trd5_in=1 ) generate mf <= trd_repack_data(5) after 1 ns when rising_edge( clk ); end generate;
|
1093 |
|
|
xd5n: if( trd5_in=0 ) generate mf <= (others=>'0'); end generate;
|
1094 |
|
|
|
1095 |
|
|
xd6p: if( trd6_in=1 ) generate mg <= trd_repack_data(6) after 1 ns when rising_edge( clk ); end generate;
|
1096 |
|
|
xd6n: if( trd6_in=0 ) generate mg <= (others=>'0'); end generate;
|
1097 |
|
|
|
1098 |
|
|
xd7p: if( trd6_in=1 ) generate mh <= trd_repack_data(7) after 1 ns when rising_edge( clk ); end generate;
|
1099 |
|
|
xd7n: if( trd6_in=0 ) generate mh <= (others=>'0'); end generate;
|
1100 |
|
|
|
1101 |
|
|
|
1102 |
|
|
gen_repack: for ii in 0 to 7 generate
|
1103 |
|
|
|
1104 |
|
|
trd_repack_data(ii)( 31 downto 0 ) <= trd_data(ii)( 31 downto 0 ) when flag_rd_repack(ii)='0' else trd_data(ii)( 63 downto 32 );
|
1105 |
|
|
trd_repack_data(ii)( 63 downto 32 ) <= trd_data(ii)( 63 downto 32 );
|
1106 |
|
|
|
1107 |
|
|
pr_flag4: process( clk ) begin
|
1108 |
|
|
if( rising_edge( clk ) ) then
|
1109 |
|
|
if( trd_drq(ii).en='1' ) then
|
1110 |
|
|
flag_rd_repack(ii) <= '0' after 1 ns;
|
1111 |
|
|
flag_rd_block(ii) <= '0' after 1 ns;
|
1112 |
|
|
elsif( trd_reset_fifo(ii)='0' ) then
|
1113 |
|
|
flag_rd_repack(ii) <= '0' after 1 ns;
|
1114 |
|
|
flag_rd_block(ii) <= '1' after 1 ns;
|
1115 |
|
|
elsif( bl_data_cs(ii)='0' ) then
|
1116 |
|
|
flag_rd_repack(ii) <= not flag_rd_repack(ii) after 1 ns;
|
1117 |
|
|
flag_rd_block(ii) <= not flag_rd_block(ii) after 1 ns;
|
1118 |
|
|
end if;
|
1119 |
|
|
end if;
|
1120 |
|
|
end process;
|
1121 |
|
|
|
1122 |
|
|
end generate;
|
1123 |
|
|
|
1124 |
|
|
|
1125 |
|
|
|
1126 |
|
|
|
1127 |
|
|
maa <= rom_data2 after 1 ns when rising_edge( clk );
|
1128 |
|
|
mab <= cmd_data2 after 1 ns when rising_edge( clk );
|
1129 |
|
|
mac <= addra2 after 1 ns when rising_edge( clk );
|
1130 |
|
|
|
1131 |
|
|
mad <= (others=>'-');
|
1132 |
|
|
mae <= (others=>'-');
|
1133 |
|
|
maf <= (others=>'-');
|
1134 |
|
|
mag <= (others=>'-');
|
1135 |
|
|
mah <= (others=>'-');
|
1136 |
|
|
|
1137 |
|
|
|
1138 |
|
|
pr_mux_sel: process( clk ) begin
|
1139 |
|
|
if( rising_edge( clk ) ) then
|
1140 |
|
|
case( adr2( 2 downto 1 ) ) is
|
1141 |
|
|
when "00" => -- STATUS
|
1142 |
|
|
mux_sel <= "1001";
|
1143 |
|
|
when "01" => -- DATA
|
1144 |
|
|
mux_sel( 2 downto 0 ) <= adr2( 5 downto 3 );
|
1145 |
|
|
mux_sel( 3 ) <= '0';
|
1146 |
|
|
when "10" => -- CMD_ADR
|
1147 |
|
|
mux_sel <= "1010";
|
1148 |
|
|
when "11" => -- CMD_DATA
|
1149 |
|
|
mux_sel( 3 downto 1 ) <= "100";
|
1150 |
|
|
mux_sel( 0 ) <= addra( 9 );
|
1151 |
|
|
when others => null;
|
1152 |
|
|
end case;
|
1153 |
|
|
end if;
|
1154 |
|
|
end process;
|
1155 |
|
|
|
1156 |
|
|
|
1157 |
|
|
|
1158 |
|
|
mux_cmd: ctrl_mux8x16r
|
1159 |
|
|
port map (
|
1160 |
|
|
ma => na,
|
1161 |
|
|
mb => nb,
|
1162 |
|
|
mc => nc,
|
1163 |
|
|
md => nd,
|
1164 |
|
|
me => ne,
|
1165 |
|
|
mf => nf,
|
1166 |
|
|
mg => ng,
|
1167 |
|
|
mh => nh,
|
1168 |
|
|
s => adr2( 5 downto 3 ),
|
1169 |
|
|
q => cmd_data2,
|
1170 |
|
|
clk => clk
|
1171 |
|
|
);
|
1172 |
|
|
|
1173 |
|
|
na <= trd_cmd_data(0) after 1 ns when rising_edge( clk );
|
1174 |
|
|
|
1175 |
|
|
xc1p: if( trd1_st=1 ) generate nb <= trd_cmd_data(1) after 1 ns when rising_edge( clk ); end generate;
|
1176 |
|
|
xc1n: if( trd1_st=0 ) generate nb <= (others=>'1'); end generate;
|
1177 |
|
|
|
1178 |
|
|
xc2p: if( trd2_st=1 ) generate nc <= trd_cmd_data(2) after 1 ns when rising_edge( clk ); end generate;
|
1179 |
|
|
xc2n: if( trd2_st=0 ) generate nc <= (others=>'1'); end generate;
|
1180 |
|
|
|
1181 |
|
|
xc3p: if( trd3_st=1 ) generate nd <= trd_cmd_data(3) after 1 ns when rising_edge( clk ); end generate;
|
1182 |
|
|
xc3n: if( trd3_st=0 ) generate nd <= (others=>'1'); end generate;
|
1183 |
|
|
|
1184 |
|
|
xc4p: if( trd4_st=1 ) generate ne <= trd_cmd_data(4) after 1 ns when rising_edge( clk ); end generate;
|
1185 |
|
|
xc4n: if( trd4_st=0 ) generate ne <= (others=>'1'); end generate;
|
1186 |
|
|
|
1187 |
|
|
xc5p: if( trd5_st=1 ) generate nf <= trd_cmd_data(5) after 1 ns when rising_edge( clk ); end generate;
|
1188 |
|
|
xc5n: if( trd5_st=0 ) generate nf <= (others=>'1'); end generate;
|
1189 |
|
|
|
1190 |
|
|
xc6p: if( trd6_st=1 ) generate ng <= trd_cmd_data(6) after 1 ns when rising_edge( clk ); end generate;
|
1191 |
|
|
xc6n: if( trd6_st=0 ) generate ng <= (others=>'1'); end generate;
|
1192 |
|
|
|
1193 |
|
|
xc7p: if( trd7_st=1 ) generate nh <= trd_cmd_data(7) after 1 ns when rising_edge( clk ); end generate;
|
1194 |
|
|
xc7n: if( trd7_st=0 ) generate nh <= (others=>'1'); end generate;
|
1195 |
|
|
|
1196 |
|
|
|
1197 |
|
|
|
1198 |
|
|
pr_flag_data_we4: process( clk ) begin
|
1199 |
|
|
if( rising_edge( clk ) ) then
|
1200 |
|
|
if( main_mode2_4='0' ) then
|
1201 |
|
|
flag_data_we(4) <= '1' after 1 ns;
|
1202 |
|
|
elsif( trd_reset_fifo( 4 )='0' ) then
|
1203 |
|
|
flag_data_we(4) <= '0' after 1 ns;
|
1204 |
|
|
elsif( bl_data_we( 4 )='1' ) then
|
1205 |
|
|
flag_data_we( 4 ) <= not flag_data_we( 4 ) after 1 ns;
|
1206 |
|
|
end if;
|
1207 |
|
|
end if;
|
1208 |
|
|
end process;
|
1209 |
|
|
|
1210 |
|
|
trd4i_host_data( 31 downto 0 ) <= data2( 31 downto 0 ) when rising_edge( clk ) and flag_data_we(4)='0' and bl_data_we(4)='1';
|
1211 |
|
|
trd4i_host_data( 63 downto 32 ) <= data2( 31 downto 0 );
|
1212 |
|
|
|
1213 |
|
|
trd4_host_data <= trd4i_host_data when main_mode2_4='1' else data2;
|
1214 |
|
|
|
1215 |
|
|
flag_data_we( 3 downto 0 ) <= (others=>'1');
|
1216 |
|
|
flag_data_we( 7 downto 5 ) <= (others=>'1');
|
1217 |
|
|
|
1218 |
|
|
|
1219 |
|
|
gen_mode2: if( trd4_mode=0 ) generate
|
1220 |
|
|
|
1221 |
|
|
pr_main_mode2: process( clk ) begin
|
1222 |
|
|
if( rising_edge( clk ) ) then
|
1223 |
|
|
if( reset='0' ) then
|
1224 |
|
|
main_mode2_4 <= '0' after 1 ns;
|
1225 |
|
|
elsif( bl_cmd_data_we1(0)='1' and cmd0_adr( 9 downto 8 )="00" and cmd0_adr( 4 downto 0 )="01010" ) then
|
1226 |
|
|
main_mode2_4 <= data2(4) after 1 ns;
|
1227 |
|
|
end if;
|
1228 |
|
|
end if;
|
1229 |
|
|
end process;
|
1230 |
|
|
|
1231 |
|
|
end generate;
|
1232 |
|
|
|
1233 |
|
|
gen_dmar2: if( trd4_mode=2 ) generate
|
1234 |
|
|
|
1235 |
|
|
main_mode2_4 <= not trd_drq(4).en;
|
1236 |
|
|
|
1237 |
|
|
end generate;
|
1238 |
|
|
|
1239 |
|
|
|
1240 |
|
|
end pb_adm_ctrl_m2;
|