Subversion Repositories pcie_ds_dma

(edif test (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0))

(status (written (timeStamp 2006 12 26 11 0 53)

   (author "Xilinx, Inc.")

   (program "Xilinx CORE Generator" (version "Xilinx CORE Generator 8.2.03i; Cores Update # 2"))))

   (comment "

      This file is owned and controlled by Xilinx and must be used

      solely for design, simulation, implementation and creation of

      design files limited to Xilinx devices or technologies. Use

      with non-Xilinx devices or technologies is expressly prohibited

      and immediately terminates your license.

      XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION 'AS IS'

      SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR

      XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION

      AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION

      OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS

      IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,

      AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE

      FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY

      WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE

      IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR

      REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF

      INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS

      FOR A PARTICULAR PURPOSE.

      Xilinx products are not intended for use in life support

      appliances, devices, or systems. Use in such applications are

      expressly prohibited.

      (c) Copyright 1995-2006 Xilinx, Inc.

      All rights reserved.

   ")

   (comment "Core parameters: ")

       (comment "c_rd_freq = 100 ")

       (comment "c_wr_response_latency = 1 ")

       (comment "c_has_srst = 0 ")

       (comment "c_has_rd_data_count = 1 ")

       (comment "c_din_width = 65 ")

       (comment "c_has_wr_data_count = 1 ")

       (comment "InstanceName = ctrl_fifo1024x65_v5 ")

       (comment "c_implementation_type = 2 ")

       (comment "c_family = spartan3 ")

       (comment "c_has_wr_rst = 0 ")

       (comment "c_wr_freq = 100 ")

       (comment "c_underflow_low = 0 ")

       (comment "c_has_meminit_file = 0 ")

       (comment "c_has_overflow = 0 ")

       (comment "c_preload_latency = 1 ")

       (comment "c_dout_width = 65 ")

       (comment "c_rd_depth = 1024 ")

       (comment "c_default_value = BlankString ")

       (comment "c_mif_file_name = BlankString ")

       (comment "c_has_underflow = 0 ")

       (comment "c_has_rd_rst = 0 ")

       (comment "c_has_almost_full = 0 ")

       (comment "c_has_rst = 1 ")

       (comment "c_data_count_width = 10 ")

       (comment "c_has_wr_ack = 0 ")

       (comment "c_wr_ack_low = 0 ")

       (comment "c_common_clock = 0 ")

       (comment "c_rd_pntr_width = 10 ")

       (comment "c_has_almost_empty = 0 ")

       (comment "c_rd_data_count_width = 1 ")

       (comment "c_enable_rlocs = 0 ")

       (comment "c_wr_pntr_width = 10 ")

       (comment "c_overflow_low = 0 ")

       (comment "c_prog_empty_type = 1 ")

       (comment "c_optimization_mode = 0 ")

       (comment "c_wr_data_count_width = 1 ")

       (comment "c_preload_regs = 0 ")

       (comment "c_dout_rst_val = 0 ")

       (comment "c_has_data_count = 0 ")

       (comment "c_prog_full_thresh_negate_val = 991 ")

       (comment "c_wr_depth = 1024 ")

       (comment "c_prog_empty_thresh_negate_val = 33 ")

       (comment "c_prog_empty_thresh_assert_val = 32 ")

       (comment "c_has_valid = 0 ")

       (comment "c_init_wr_pntr_val = 0 ")

       (comment "c_prog_full_thresh_assert_val = 992 ")

       (comment "c_use_fifo16_flags = 0 ")

       (comment "c_has_backup = 0 ")

       (comment "c_valid_low = 0 ")

       (comment "c_prim_fifo_type = 1kx36 ")

       (comment "c_count_type = 0 ")

       (comment "c_prog_full_type = 1 ")

       (comment "c_memory_type = 1 ")

   (external xilinxun (edifLevel 0)

      (technology (numberDefinition))

       (cell VCC (cellType GENERIC)

           (view view_1 (viewType NETLIST)

               (interface

                   (port P (direction OUTPUT))

               )

           )

       )

       (cell GND (cellType GENERIC)

           (view view_1 (viewType NETLIST)

               (interface

                   (port G (direction OUTPUT))

               )

           )

       )

   )

   (external ctrl_fifo1024x65_v5_fifo_generator_v3_2_xst_1_lib (edifLevel 0)

       (technology (numberDefinition))

       (cell ctrl_fifo1024x65_v5_fifo_generator_v3_2_xst_1 (cellType GENERIC)

           (view view_1 (viewType NETLIST)

               (interface

                   (port clk (direction INPUT))

                   (port backup (direction INPUT))

                   (port backup_marker (direction INPUT))

                   (port ( array ( rename din "din<64:0>") 65 ) (direction INPUT))

                   (port ( array ( rename prog_empty_thresh "prog_empty_thresh<9:0>") 10 ) (direction INPUT))

                   (port ( array ( rename prog_empty_thresh_assert "prog_empty_thresh_assert<9:0>") 10 ) (direction INPUT))

                   (port ( array ( rename prog_empty_thresh_negate "prog_empty_thresh_negate<9:0>") 10 ) (direction INPUT))

                   (port ( array ( rename prog_full_thresh "prog_full_thresh<9:0>") 10 ) (direction INPUT))

                   (port ( array ( rename prog_full_thresh_assert "prog_full_thresh_assert<9:0>") 10 ) (direction INPUT))

                   (port ( array ( rename prog_full_thresh_negate "prog_full_thresh_negate<9:0>") 10 ) (direction INPUT))

                   (port rd_clk (direction INPUT))

                   (port rd_en (direction INPUT))

                   (port rd_rst (direction INPUT))

                   (port rst (direction INPUT))

                   (port srst (direction INPUT))

                   (port wr_clk (direction INPUT))

                   (port wr_en (direction INPUT))

                   (port wr_rst (direction INPUT))

                   (port almost_empty (direction OUTPUT))

                   (port almost_full (direction OUTPUT))

                   (port ( array ( rename data_count "data_count<9:0>") 10 ) (direction OUTPUT))

                   (port ( array ( rename dout "dout<64:0>") 65 ) (direction OUTPUT))

                   (port empty (direction OUTPUT))

                   (port full (direction OUTPUT))

                   (port overflow (direction OUTPUT))

                   (port prog_empty (direction OUTPUT))

                   (port prog_full (direction OUTPUT))

                   (port valid (direction OUTPUT))

                   (port ( array ( rename rd_data_count "rd_data_count<0:0>") 1 ) (direction OUTPUT))

                   (port underflow (direction OUTPUT))

                   (port wr_ack (direction OUTPUT))

                   (port ( array ( rename wr_data_count "wr_data_count<0:0>") 1 ) (direction OUTPUT))

               )

           )

       )

   )

(library test_lib (edifLevel 0) (technology (numberDefinition (scale 1 (E 1 -12) (unit Time))))

(cell ctrl_fifo1024x65_v5

 (cellType GENERIC) (view view_1 (viewType NETLIST)

  (interface

   (port ( array ( rename din "din<64:0>") 65 ) (direction INPUT))

   (port ( rename rd_clk "rd_clk") (direction INPUT))

   (port ( rename rd_en "rd_en") (direction INPUT))

   (port ( rename rst "rst") (direction INPUT))

   (port ( rename wr_clk "wr_clk") (direction INPUT))

   (port ( rename wr_en "wr_en") (direction INPUT))

   (port ( array ( rename dout "dout<64:0>") 65 ) (direction OUTPUT))

   (port ( rename empty "empty") (direction OUTPUT))

   (port ( rename full "full") (direction OUTPUT))

   (port ( rename prog_empty "prog_empty") (direction OUTPUT))

   (port ( rename prog_full "prog_full") (direction OUTPUT))

   (port ( array ( rename rd_data_count "rd_data_count<0:0>") 1 ) (direction OUTPUT))

   (port ( array ( rename wr_data_count "wr_data_count<0:0>") 1 ) (direction OUTPUT))

   )

  (contents

   (instance VCC (viewRef view_1 (cellRef VCC  (libraryRef xilinxun))))

   (instance GND (viewRef view_1 (cellRef GND  (libraryRef xilinxun))))

   (instance BU2

      (viewRef view_1 (cellRef ctrl_fifo1024x65_v5_fifo_generator_v3_2_xst_1 (libraryRef ctrl_fifo1024x65_v5_fifo_generator_v3_2_xst_1_lib)))

   )

   (net (rename N5 "din<64>")

    (joined

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    )

   )

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