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[/] [pcie_ds_dma/] [trunk/] [core/] [adm/] [coregen/] [ctrl_fifo1024x65_v5.vhd] - Blame information for rev 2

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--     This file is owned and controlled by Xilinx and must be used           --
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--     solely for design, simulation, implementation and creation of          --
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--     design files limited to Xilinx devices or technologies. Use            --
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--     with non-Xilinx devices or technologies is expressly prohibited        --
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--     and immediately terminates your license.                               --
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--                                                                            --
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--     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"          --
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--     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                --
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--     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION        --
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--     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION            --
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--     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS              --
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--     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                --
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--     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE       --
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--     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY               --
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--     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                --
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--     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR         --
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--     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF        --
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--     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS        --
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--     FOR A PARTICULAR PURPOSE.                                              --
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--                                                                            --
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--     Xilinx products are not intended for use in life support               --
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--     appliances, devices, or systems. Use in such applications are          --
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--     expressly prohibited.                                                  --
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--                                                                            --
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--     (c) Copyright 1995-2006 Xilinx, Inc.                                   --
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--     All rights reserved.                                                   --
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--------------------------------------------------------------------------------
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-- You must compile the wrapper file ctrl_fifo1024x65_v5.vhd when simulating
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-- the core, ctrl_fifo1024x65_v5. When compiling the wrapper file, be sure to
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-- reference the XilinxCoreLib VHDL simulation library. For detailed
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-- instructions, please refer to the "CORE Generator Help".
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-- The synopsys directives "translate_off/translate_on" specified
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-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
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-- synthesis tools. Ensure they are correct for your synthesis tool(s).
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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-- synopsys translate_off
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Library XilinxCoreLib;
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-- synopsys translate_on
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ENTITY ctrl_fifo1024x65_v5 IS
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        port (
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        din: IN std_logic_VECTOR(64 downto 0);
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        rd_clk: IN std_logic;
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        rd_en: IN std_logic;
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        rst: IN std_logic;
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        wr_clk: IN std_logic;
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        wr_en: IN std_logic;
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        dout: OUT std_logic_VECTOR(64 downto 0);
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        empty: OUT std_logic;
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        full: OUT std_logic;
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        prog_empty: OUT std_logic;
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        prog_full: OUT std_logic;
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        rd_data_count: OUT std_logic_VECTOR(0 downto 0);
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        wr_data_count: OUT std_logic_VECTOR(0 downto 0));
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END ctrl_fifo1024x65_v5;
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ARCHITECTURE ctrl_fifo1024x65_v5_a OF ctrl_fifo1024x65_v5 IS
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-- synopsys translate_off
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component wrapped_ctrl_fifo1024x65_v5
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        port (
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        din: IN std_logic_VECTOR(64 downto 0);
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        rd_clk: IN std_logic;
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        rd_en: IN std_logic;
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        rst: IN std_logic;
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        wr_clk: IN std_logic;
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        wr_en: IN std_logic;
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        dout: OUT std_logic_VECTOR(64 downto 0);
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        empty: OUT std_logic;
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        full: OUT std_logic;
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        prog_empty: OUT std_logic;
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        prog_full: OUT std_logic;
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        rd_data_count: OUT std_logic_VECTOR(0 downto 0);
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        wr_data_count: OUT std_logic_VECTOR(0 downto 0));
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end component;
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-- Configuration specification 
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        for all : wrapped_ctrl_fifo1024x65_v5 use entity XilinxCoreLib.fifo_generator_v3_3(behavioral)
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                generic map(
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                        c_rd_freq => 100,
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                        c_wr_response_latency => 1,
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                        c_has_srst => 0,
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                        c_has_rd_data_count => 1,
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                        c_din_width => 65,
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                        c_has_wr_data_count => 1,
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                        c_implementation_type => 2,
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                        c_family => "spartan3",
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                        c_has_wr_rst => 0,
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                        c_wr_freq => 100,
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                        c_underflow_low => 0,
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                        c_has_meminit_file => 0,
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                        c_has_overflow => 0,
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                        c_preload_latency => 1,
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                        c_dout_width => 65,
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                        c_rd_depth => 1024,
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                        c_default_value => "BlankString",
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                        c_mif_file_name => "BlankString",
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                        c_has_underflow => 0,
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                        c_has_rd_rst => 0,
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                        c_has_almost_full => 0,
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                        c_has_rst => 1,
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                        c_data_count_width => 10,
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                        c_has_wr_ack => 0,
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                        c_wr_ack_low => 0,
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                        c_common_clock => 0,
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                        c_rd_pntr_width => 10,
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                        c_has_almost_empty => 0,
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                        c_rd_data_count_width => 1,
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                        c_enable_rlocs => 0,
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                        c_wr_pntr_width => 10,
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                        c_overflow_low => 0,
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                        c_prog_empty_type => 1,
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                        c_optimization_mode => 0,
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                        c_wr_data_count_width => 1,
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                        c_preload_regs => 0,
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                        c_dout_rst_val => "0",
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                        c_has_data_count => 0,
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                        c_prog_full_thresh_negate_val => 991,
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                        c_wr_depth => 1024,
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                        c_prog_empty_thresh_negate_val => 33,
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                        c_prog_empty_thresh_assert_val => 32,
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                        c_has_valid => 0,
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                        c_init_wr_pntr_val => 0,
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                        c_prog_full_thresh_assert_val => 992,
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                        c_use_fifo16_flags => 0,
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                        c_has_backup => 0,
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                        c_valid_low => 0,
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                        c_prim_fifo_type => "1kx36",
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                        c_count_type => 0,
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                        c_prog_full_type => 1,
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                        c_memory_type => 1);
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-- synopsys translate_on
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BEGIN
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-- synopsys translate_off
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U0 : wrapped_ctrl_fifo1024x65_v5
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                port map (
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                        din => din,
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                        rd_clk => rd_clk,
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                        rd_en => rd_en,
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                        rst => rst,
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                        wr_clk => wr_clk,
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                        wr_en => wr_en,
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                        dout => dout,
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                        empty => empty,
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                        full => full,
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                        prog_empty => prog_empty,
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                        prog_full => prog_full,
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                        rd_data_count => rd_data_count,
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                        wr_data_count => wr_data_count);
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-- synopsys translate_on
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END ctrl_fifo1024x65_v5_a;
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