URL https://opencores.org/ocsvn/pcie_ds_dma/pcie_ds_dma/trunk
Subversion Repositories pcie_ds_dma

[/] [pcie_ds_dma/] [trunk/] [core/] [adm/] [coregen/] [ctrl_mux16x16.edn] - Blame information for rev 2

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(edif test (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0))
(status (written (timeStamp 2004 9 22 18 57 23)
   (author "Xilinx, Inc.")
   (program "Xilinx CORE Generator" (version "Xilinx CORE Generator 6.2.03i; Cores Update # 1.1"))))
   (comment "
      This file is owned and controlled by Xilinx and must be used
      solely for design, simulation, implementation and creation of
      design files limited to Xilinx devices or technologies. Use
      with non-Xilinx devices or technologies is expressly prohibited
      and immediately terminates your license.
 
      XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION 'AS IS'
      SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
      XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
      AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
      OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
      IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
      AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
      FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
      WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
      IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
      REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
      INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
      FOR A PARTICULAR PURPOSE.
 
      Xilinx products are not intended for use in life support
      appliances, devices, or systems. Use in such applications are
      expressly prohibited.
 
      (c) Copyright 1995-2003 Xilinx, Inc.
      All rights reserved.
 
   ")
   (comment "Core parameters: ")
       (comment "c_has_aset = false ")
       (comment "c_has_en = false ")
       (comment "c_sync_priority = 1 ")
       (comment "c_has_sclr = false ")
       (comment "c_width = 16 ")
       (comment "c_height = 0 ")
       (comment "c_enable_rlocs = false ")
       (comment "c_sel_width = 4 ")
       (comment "c_latency = 0 ")
       (comment "c_ainit_val = 0000000000000000 ")
       (comment "c_has_ce = false ")
       (comment "c_family = spartan3 ")
       (comment "c_mux_type = 0 ")
       (comment "InstanceName = ctrl_mux16x16 ")
       (comment "c_has_aclr = false ")
       (comment "c_sync_enable = 0 ")
       (comment "c_sinit_val = 0000000000000000 ")
       (comment "c_has_ainit = false ")
       (comment "c_has_sset = false ")
       (comment "c_has_sinit = false ")
       (comment "c_has_q = false ")
       (comment "c_has_o = true ")
       (comment "c_inputs = 16 ")
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               (interface
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           )
       )
       (cell LUT4 (cellType GENERIC)
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               (interface
                   (port I0 (direction INPUT))
                   (port I1 (direction INPUT))
                   (port I2 (direction INPUT))
                   (port I3 (direction INPUT))
                   (port O (direction OUTPUT))
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       )
       (cell MUXF5 (cellType GENERIC)
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                   (port I1 (direction INPUT))
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(library test_lib (edifLevel 0) (technology (numberDefinition (scale 1 (E 1 -12) (unit Time))))
(cell ctrl_mux16x16
 (cellType GENERIC) (view view_1 (viewType NETLIST)
  (interface
   (port ( array ( rename MA "MA<15:0>") 16 ) (direction INPUT))
   (port ( array ( rename MB "MB<15:0>") 16 ) (direction INPUT))
   (port ( array ( rename MC "MC<15:0>") 16 ) (direction INPUT))
   (port ( array ( rename MD "MD<15:0>") 16 ) (direction INPUT))
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   (port ( array ( rename MAE "MAE<15:0>") 16 ) (direction INPUT))
   (port ( array ( rename MAF "MAF<15:0>") 16 ) (direction INPUT))
   (port ( array ( rename MAG "MAG<15:0>") 16 ) (direction INPUT))
   (port ( array ( rename MAH "MAH<15:0>") 16 ) (direction INPUT))
   (port ( array ( rename S "S<3:0>") 4 ) (direction INPUT))
   (port ( array ( rename O "O<15:0>") 16 ) (direction OUTPUT))
   )
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   (instance BU590
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   (instance BU592
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   (instance BU597
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   )
   (instance BU601
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   (instance BU603
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   (instance BU605
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   (instance BU561
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   (instance BU565
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   (instance BU567
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   (instance BU572
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      (property INIT (string "caca"))
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   (instance BU578
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   (instance BU580
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      (property INIT (string "caca"))
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   (instance BU645
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      (property INIT (string "caca"))
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   (instance BU652
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      (property INIT (string "caca"))
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      (property INIT (string "caca"))
   )
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      (property INIT (string "caca"))
   )
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))))
(design ctrl_mux16x16 (cellRef ctrl_mux16x16 (libraryRef test_lib))
  (property X_CORE_INFO (string "C_MUX_BUS_V6_0, Coregen 6.2.03i_ip1.1"))
  (property PART (string "XC3S5000-4-fg900") (owner "Xilinx")))
)
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[/] [pcie_ds_dma/] [trunk/] [core/] [adm/] [coregen/] [ctrl_mux16x16.edn] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	dsmv	`(edif test (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0))`
2			`(status (written (timeStamp 2004 9 22 18 57 23)`
3			`(author "Xilinx, Inc.")`
4			`(program "Xilinx CORE Generator" (version "Xilinx CORE Generator 6.2.03i; Cores Update # 1.1"))))`
5			`(comment "`
6			`This file is owned and controlled by Xilinx and must be used`
7			`solely for design, simulation, implementation and creation of`
8			`design files limited to Xilinx devices or technologies. Use`
9			`with non-Xilinx devices or technologies is expressly prohibited`
10			`and immediately terminates your license.`
11
12			`XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION 'AS IS'`
13			`SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR`
14			`XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION`
15			`AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION`
16			`OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS`
17			`IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,`
18			`AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE`
19			`FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY`
20			`WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE`
21			`IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR`
22			`REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF`
23			`INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS`
24			`FOR A PARTICULAR PURPOSE.`
25
26			`Xilinx products are not intended for use in life support`
27			`appliances, devices, or systems. Use in such applications are`
28			`expressly prohibited.`
29
30			`(c) Copyright 1995-2003 Xilinx, Inc.`
31			`All rights reserved.`
32
33			`")`
34			`(comment "Core parameters: ")`
35			`(comment "c_has_aset = false ")`
36			`(comment "c_has_en = false ")`
37			`(comment "c_sync_priority = 1 ")`
38			`(comment "c_has_sclr = false ")`
39			`(comment "c_width = 16 ")`
40			`(comment "c_height = 0 ")`